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1. 发明授权

US08310276B2 Differential transmission circuit 有权
标题翻译：差分传输电路
公开(公告)号：US08310276B2
公开(公告)日：2012-11-13
申请号：US13000609
申请日：2009-06-16
申请人： Kenji Onuki , Hideyuki Rengakuji
发明人： Kenji Onuki , Hideyuki Rengakuji
IPC分类号： H03K19/0175 , H04B1/38
CPC分类号： H04L25/0278 , H04L25/0272 , H05K1/0245 , H05K1/0248 , H05K1/025
摘要： A differential transmission circuit comprises a sending unit that generates a pair of differential signals from an input signal, and sends the differential signals; a receiver that receives the differential signals sent by the sending unit; and a transmission path that transmits the differential signals from the sending unit to the receiver, wherein the sending unit has a selector that selects one of the input signal and a signal obtained by inverting a polarity of the input signal, and generates the differential signals from the signal selected by the selector.
摘要翻译：差分传输电路包括发送单元，其从输入信号生成一对差分信号，并发送差分信号; 接收由发送单元发送的差分信号的接收机; 以及将差分信号从发送单元发送到接收机的传输路径，其中发送单元具有选择器，其选择输入信号中的一个和通过反相输入信号的极性而获得的信号，并且生成差分信号由选择器选择的信号。

2. 发明申请

US20110109379A1 DIFFERENTIAL TRANSMISSION CIRCUIT 有权
标题翻译：差分传输电路
公开(公告)号：US20110109379A1
公开(公告)日：2011-05-12
申请号：US13000609
申请日：2009-06-16
申请人： Kenji Onuki , Hideyuki Rengakuji
发明人： Kenji Onuki , Hideyuki Rengakuji
IPC分类号： H03K5/00
CPC分类号： H04L25/0278 , H04L25/0272 , H05K1/0245 , H05K1/0248 , H05K1/025
摘要： A differential transmission circuit comprises a sending unit that generates a pair of differential signals from an input signal, and sends the differential signals; a receiver that receives the differential signals sent by the sending unit; and a transmission path that transmits the differential signals from the sending unit to the receiver, wherein the sending unit has a selector that selects one of the input signal and a signal obtained by inverting a polarity of the input signal, and generates the differential signals from the signal selected by the selector.
摘要翻译：差分传输电路包括发送单元，其从输入信号生成一对差分信号，并发送差分信号; 接收由发送单元发送的差分信号的接收机; 以及将差分信号从发送单元发送到接收机的传输路径，其中发送单元具有选择器，其选择输入信号中的一个和通过反相输入信号的极性而获得的信号，并且生成差分信号由选择器选择的信号。

3. 发明申请

US20070098301A1 IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD 有权
标题翻译：图像处理装置和图像处理方法
公开(公告)号：US20070098301A1
公开(公告)日：2007-05-03
申请号：US11550235
申请日：2006-10-17
申请人： Hideyuki Rengakuji , Takayuki Hara
发明人： Hideyuki Rengakuji , Takayuki Hara
IPC分类号： G06K9/32 , G06K9/36
CPC分类号： H04N5/2624 , H04N5/349
摘要： An image processing apparatus includes a determining unit that determines whether image capturing conditions concerning super-resolution processing are satisfied for each piece of image data, and an adding unit that adds data corresponding to a result of determination made by the determining unit to each piece of the image data.
摘要翻译：图像处理装置包括确定单元，其确定关于每个图像数据是否满足关于超分辨率处理的图像捕获条件;以及添加单元，将与由所述确定单元确定的结果相对应的数据添加到每个图像数据。

4. 发明授权

US06212300B1 Image processing apparatus, method and computer-executable program product for converting the format of data for specific image data 失效
标题翻译：用于转换特定图像数据的数据格式的图像处理装置，方法和计算机可执行程序产品
公开(公告)号：US06212300B1
公开(公告)日：2001-04-03
申请号：US09092081
申请日：1998-06-05
申请人： Hideyuki Rengakuji
发明人： Hideyuki Rengakuji
IPC分类号： G06K936
CPC分类号： G06T9/005
摘要： An image processing apparatus, method and computer-executable program product for converting a data format of specific image data and, in particular, for performing block/raster conversion on color image data, converts image data between a raster form and a block form by supplying image data having a plurality of components in a first form, changing the order of the plurality of components and controlling storing of image data to a memory which stores the image data temporarily such that the image data is stored in the memory for each component and by reading out from the memory in a second form which is different from the first form.
摘要翻译：用于转换特定图像数据的数据格式，特别是用于对彩色图像数据执行块/光栅转换的图像处理装置，方法和计算机可执行程序产品，通过提供光栅形式和块形式来转换图像数据具有第一形式的多个分量的图像数据，改变多个分量的顺序并且控制图像数据临时存储图像数据的存储器，使得图像数据被存储在每个分量的存储器中，并且通过以与第一形式不同的第二形式从存储器读出。

5. 发明申请

US20120224087A1 IMAGE CAPTURING APPARATUS AND CONTROL METHOD THEREFOR 有权
标题翻译：图像捕获装置及其控制方法
公开(公告)号：US20120224087A1
公开(公告)日：2012-09-06
申请号：US13474288
申请日：2012-05-17
申请人： Saori Hoda , Hideyuki Rengakuji , Yoshihiro Homma
发明人： Saori Hoda , Hideyuki Rengakuji , Yoshihiro Homma
IPC分类号： H04N5/225
CPC分类号： H04N5/367 , G03B13/36 , H04N5/23212 , H04N5/3696 , H04N5/378
摘要： An image capturing apparatus includes an image sensor 104 in which at least part of pixels arranged in two dimensions are configured as focus detection pixels with divided-pupil, a memory control circuit 113 configured to read out from a memory position information for the focus detection pixels 401, 402 stored in the memory, and a correction circuit 110 configured to identify positions of the focus detection pixels 401, 402 in the image sensor 104 based on the position information for the focus detection pixels 401, 402 and to correct a defective focus detection pixel signal using defect-free focus detection pixel signals.
摘要翻译：图像捕获装置包括图像传感器104，其中以二维排列的至少一部分像素被配置为具有分光瞳的焦点检测像素;存储器控制电路113，被配置为从存储器位置读出焦点检测像素的信息 401,402存储在存储器中，校正电路110被配置为基于焦点检测像素401,402的位置信息来识别图像传感器104中的焦点检测像素401,402的位置，并且校正缺陷焦点检测像素信号使用无缺陷的焦点检测像素信号。

6. 发明授权

US07796136B2 Image signal processing apparatus, memory control method, and program for implementing the method 有权
标题翻译：图像信号处理装置，存储器控制方法和用于实现该方法的程序
公开(公告)号：US07796136B2
公开(公告)日：2010-09-14
申请号：US11176865
申请日：2005-07-07
申请人： Shin Takagi , Hideyuki Rengakuji
发明人： Shin Takagi , Hideyuki Rengakuji
IPC分类号： G06F15/167 , G06F12/02 , G09G5/397
CPC分类号： G09G5/39 , G06F3/147
摘要： An image signal processing apparatus which is capable of preventing the “simultaneous display of an original image and the immediately preceding image” as well as dropping of frames. A signal processor subjects an image pickup signal corresponding to a subject outputted from an image pickup device to signal processing. A VRAM (Video Random Access Memory) section is composed of at least three storage areas that store image signals outputted from the signal processing circuit. A VRAM management information section stores management information indicative of storage states of the respective storage areas of the VRAM section. A compression circuit subjects an image signal read from the VRAM section to compression processing. An image display processing circuit subjects an image signal read from the VRAM section to image display processing. An image display section displays images based on the image signal outputted from the image display processing circuit. A memory controller controls read/write operations for image signals in the respective storage areas of the VRAM section based on the management information stored in the VRAM management information section.
摘要翻译：一种图像信号处理装置，其能够防止“同时显示原始图像和紧接在前的图像”以及帧的丢弃。信号处理器对应于从图像拾取装置输出的对象的图像拾取信号进行信号处理。 VRAM（视频随机存取存储器）部分由存储从信号处理电路输出的图像信号的至少三个存储区域组成。 VRAM管理信息部存储表示VRAM部的各个存储区域的存储状态的管理信息。压缩电路对从VRAM部分读取的图像信号进行压缩处理。图像显示处理电路对从VRAM部分读取的图像信号进行图像显示处理。图像显示部分基于从图像显示处理电路输出的图像信号显示图像。存储器控制器基于存储在VRAM管理信息部分中的管理信息来控制VRAM部分的各个存储区域中的图像信号的读/写操作。

7. 发明申请

US20060250858A1 Register configuration control device, register configuration control method, and program for implementing the method 失效
标题翻译：寄存器配置控制装置，寄存器配置控制方法和实现方法的程序
公开(公告)号：US20060250858A1
公开(公告)日：2006-11-09
申请号：US11429033
申请日：2006-05-05
申请人： Saori Houda , Hideyuki Rengakuji
发明人： Saori Houda , Hideyuki Rengakuji
IPC分类号： G11C7/00
CPC分类号： G06F9/4411 , G06F3/14 , G09G5/02 , G09G5/06 , G09G5/393 , G09G5/395 , G09G2310/061 , G09G2320/0285
摘要： A resister configuration control device which is capable of updating resister configuration values during a non-display period without increasing a circuit scale. A FIFO selector 103 receives register configuration value information comprising a register configuration value and address information, and selects a transmission destination to which the register configuration value information is to be sent, from FIFOs 108 and 109 based on the address information and sends the register configuration value information to the selected destination. The FIFO 108 or 109 temporarily stores the register configuration value information sent from the FIFO selector 103, and reads-out and outputs the register configuration value information in predetermined timing. A data selector 110 selects one of the register configuration value information sent from the FIFO selector 103 and the register configuration value information output from the FIFO 108 or 109, according to a predetermined priority, and outputs the selected register configuration value information.
摘要翻译：一种电阻配置控制装置，其能够在不显示电路规模的情况下在非显示期间更新电阻配置值。 FIFO选择器103接收包括寄存器配置值和地址信息的寄存器配置值信息，并且基于地址信息从FIFO 108和109中选择要发送寄存器配置值信息的发送目的地，并发送寄存器配置价值信息到所选择的目的地。 FIFO 108或109临时存储从FIFO选择器103发送的寄存器配置值信息，并且在预定定时读出并输出寄存器配置值信息。数据选择器110根据预定的优先级，从FIFO选择器103发送的寄存器配置值信息和从FIFO 108或109输出的寄存器配置值信息之一选择一个，并输出所选择的寄存器配置值信息。

8. 发明授权

US06798927B2 Conversion of pixel data for interpolation or image reduction, using a small memory 有权
标题翻译：使用小内存转换插值或图像缩小的像素数据
公开(公告)号：US06798927B2
公开(公告)日：2004-09-28
申请号：US10458301
申请日：2003-06-11
申请人： Masato Kosugi , Hideyuki Rengakuji
发明人： Masato Kosugi , Hideyuki Rengakuji
IPC分类号： G06K932
CPC分类号： G06T9/007
摘要： An image processing apparatus and method capable of decoding and varying at high speed encoded image data having an arbitrary image size by using a memory of a small capacity, and a recording medium storing programs executing such a method are provided. In the image processing apparatus and method, image data encoded in each of block units is decoded in the block unit basis. In order to convert the decoded block scan sequential image data into raster scan sequential image data, the decoded image data is divided in the horizontal direction and converted, and the divided and converted data is varied.
摘要翻译：提供了能够通过使用小容量的存储器对具有任意图像尺寸的高速编码图像数据进行解码和变化的图像处理装置和方法，以及存储执行这种方法的程序的记录介质。在图像处理装置和方法中，以块为单位对每个块单位进行编码的图像数据进行解码。为了将解码块扫描顺序图像数据转换为光栅扫描顺序图像数据，解码图像数据在水平方向上被分割并被转换，并且分割和转换的数据被改变。

9. 发明授权

US06671418B2 Image processing apparatus and method which determines a block size in accordance with a filter structure 有权
标题翻译：根据滤波器结构确定块大小的图像处理装置和方法
公开(公告)号：US06671418B2
公开(公告)日：2003-12-30
申请号：US09264717
申请日：1999-03-09
申请人： Hideyuki Rengakuji , Yuji Sakaegi , Masato Kosugi
发明人： Hideyuki Rengakuji , Yuji Sakaegi , Masato Kosugi
IPC分类号： G06K940
CPC分类号： H04N1/41
摘要： Input image data is divided into blocks so as to make adjacent blocks partially overlap image data, and the divided image data is filtered in the unit of block. An image processing apparatus and method are provided which can process image data of an arbitrary size at high speed independently from the capacity of a buffer memory, and a computer readable storage medium is provided which stores a program realizing such a method.
摘要翻译：输入图像数据被分成块，以使相邻的块部分地重叠图像数据，并且以块为单位对分割的图像数据进行滤波。提供一种图像处理装置和方法，其可以独立于缓冲存储器的容量来处理高速度的任意大小的图像数据，并且提供存储实现这种方法的程序的计算机可读存储介质。

10. 发明授权

US08890968B2 Image capturing apparatus and control method therefor with defect correction information used both for defective pixel and detection pixel identification 有权
标题翻译：用于缺陷像素和检测像素识别的缺陷校正信息的图像捕获设备及其控制方法
公开(公告)号：US08890968B2
公开(公告)日：2014-11-18
申请号：US13474288
申请日：2012-05-17
申请人： Saori Hoda , Hideyuki Rengakuji , Yoshihiro Homma
发明人： Saori Hoda , Hideyuki Rengakuji , Yoshihiro Homma
IPC分类号： H04N5/228 , G03B13/36 , H04N5/367 , H04N5/369 , H04N5/232 , H04N5/217
CPC分类号： H04N5/367 , G03B13/36 , H04N5/23212 , H04N5/3696 , H04N5/378
摘要： An image capturing apparatus includes an image sensor 104 in which at least part of pixels arranged in two dimensions are configured as focus detection pixels with divided-pupil, a memory control circuit 113 configured to read out from a memory position information for the focus detection pixels 401, 402 stored in the memory, and a correction circuit 110 configured to identify positions of the focus detection pixels 401, 402 in the image sensor 104 based on the position information for the focus detection pixels 401, 402 and to correct a defective focus detection pixel signal using defect-free focus detection pixel signals.
摘要翻译：图像捕获装置包括图像传感器104，其中以二维排列的至少一部分像素被配置为具有分光瞳的焦点检测像素;存储器控制电路113，被配置为从存储器位置读出焦点检测像素的信息 401,402存储在存储器中，校正电路110被配置为基于焦点检测像素401,402的位置信息来识别图像传感器104中的焦点检测像素401,402的位置，并且校正缺陷焦点检测像素信号使用无缺陷的焦点检测像素信号。

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