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1. 发明授权

US07965572B2 Semiconductor device and information processing system 有权
标题翻译：半导体器件和信息处理系统
公开(公告)号：US07965572B2
公开(公告)日：2011-06-21
申请号：US12504319
申请日：2009-07-16
申请人： Yutaka Uematsu , Tatsuya Saito , Yoji Nishio , Yukitoshi Hirose
发明人： Yutaka Uematsu , Tatsuya Saito , Yoji Nishio , Yukitoshi Hirose
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40618 , G11C11/4074 , G11C2211/4067
摘要： A semiconductor device or an information processing system comprises a plurality of circuit units, and a control unit for controlling a start timing of large-current operations executed by the respective circuit units within a predetermined period, where the large-current operation involves a relatively large current which flows in a power supply system, as compared with other operations. The control unit controls the start timing of the large-current operation from one circuit unit to another such that the waveform of a current flowing from the power supply system is shaped into the waveform of a half cycle of a sinusoidal wave when the circuit units execute large-current operations within the predetermined period.
摘要翻译：半导体器件或信息处理系统包括多个电路单元，以及控制单元，用于在预定时间段内控制由各个电路单元执行的大电流操作的开始定时，其中大电流操作涉及相对大的与其他操作相比，在电源系统中流动的电流。控制单元控制从一个电路单元到另一个电路单元的大电流操作的开始定时，使得当电路单元执行时，从电源系统流过的电流的波形被成形为正弦波的半周期的波形在预定时段内的大电流操作。

2. 发明申请

US20100013528A1 SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM 有权
标题翻译：半导体器件和信息处理系统
公开(公告)号：US20100013528A1
公开(公告)日：2010-01-21
申请号：US12504319
申请日：2009-07-16
申请人： Yutaka Uematsu , Tatsuya Saito , Yoji Nishio , Yukitoshi Hirose
发明人： Yutaka Uematsu , Tatsuya Saito , Yoji Nishio , Yukitoshi Hirose
IPC分类号： H03L5/00
CPC分类号： G11C11/406 , G11C11/40618 , G11C11/4074 , G11C2211/4067
摘要： A semiconductor device or an information processing system comprises a plurality of circuit units, and a control unit for controlling a start timing of large-current operations executed by the respective circuit units within a predetermined period, where the large-current operation involves a relatively large current which flows in a power supply system, as compared with other operations. The control unit controls the start timing of the large-current operation from one circuit unit to another such that the waveform of a current flowing from the power supply system is shaped into the waveform of a half cycle of a sinusoidal wave when the circuit units execute large-current operations within the predetermined period.
摘要翻译：半导体器件或信息处理系统包括多个电路单元，以及控制单元，用于在预定时间段内控制由各个电路单元执行的大电流操作的开始定时，其中大电流操作涉及相对大的与其他操作相比，在电源系统中流动的电流。控制单元控制从一个电路单元到另一个电路单元的大电流操作的开始定时，使得当电路单元执行时，从电源系统流过的电流的波形被成形为正弦波的半周期的波形在预定时段内的大电流操作。

3. 发明授权

US07319267B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07319267B2
公开(公告)日：2008-01-15
申请号：US11712440
申请日：2007-03-01
申请人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Yukitoshi Hirose
发明人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Yukitoshi Hirose
IPC分类号： H01L23/02 , H01L23/34
CPC分类号： H01L23/642 , H01L23/5223 , H01L23/5228 , H01L23/5286 , H01L23/647 , H01L25/105 , H01L2224/73204 , H01L2924/19105 , H01L2924/3011
摘要： In a prior art, there has been a method in which a power supply line of an output buffer and that of a control circuit are independently provided so that the power supply noise occurring in the control circuit will not affect the output buffer. However, this method has had the problems that it increases both the number of power supply/grounding pins and power feed line inductance.The present invention provides a technique which, without causing the above two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.
摘要翻译：在现有技术中，存在一种方法，其中独立地提供输出缓冲器的电源线和控制电路的电源线，使得控制电路中出现的电源噪声不会影响输出缓冲器。然而，该方法存在增加电源/接地引脚数和馈电线电感的问题。本发明提供一种技术，其不会引起上述两个问题，即（1）增加电源/接地引脚数量和（2）增加的馈电线电感，防止在控制电路中引起问题的噪声变成路由并感应到输出缓冲区。更具体地，可以通过以下两种方法之一来实现上述：（A）为控制电路提供片上旁路电容器，并将控制电路的馈电路径与AC类似的输出缓冲器的馈电路径隔离方式或（B）设计电参数（插入电阻），使得引入馈电路径的任何电参数噪声的振荡模式将变为过阻尼。

4. 发明申请

US20060017144A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060017144A1
公开(公告)日：2006-01-26
申请号：US10981676
申请日：2004-11-05
申请人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Yukitoshi Hirose
发明人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Yukitoshi Hirose
IPC分类号： H01L23/02
CPC分类号： H01L23/642 , H01L23/5223 , H01L23/5228 , H01L23/5286 , H01L23/647 , H01L25/105 , H01L2224/73204 , H01L2924/19105 , H01L2924/3011
摘要： The present invention provides a technique which, without causing two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.
摘要翻译：本发明提供一种技术，其不会引起两个问题，即（1）增加电源/接地引脚的数量和（2）增加的馈电线电感，防止在控制电路中引起问题的噪声变为布线并引入输出缓冲区。更具体地，可以通过以下两种方法之一来实现上述：（A）为控制电路提供片上旁路电容器，并将控制电路的馈电路径与AC类似的输出缓冲器的馈电路径隔离方式或（B）设计电参数（插入电阻），使得引入馈电路径的任何电参数噪声的振荡模式将变为过阻尼。

5. 发明申请

US20070145559A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20070145559A1
公开(公告)日：2007-06-28
申请号：US11712440
申请日：2007-03-01
申请人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Yukitoshi Hirose
发明人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Yukitoshi Hirose
IPC分类号： H01L23/02
CPC分类号： H01L23/642 , H01L23/5223 , H01L23/5228 , H01L23/5286 , H01L23/647 , H01L25/105 , H01L2224/73204 , H01L2924/19105 , H01L2924/3011
摘要： In a prior art, there has been a method in which a power supply line of an output buffer and that of a control circuit are independently provided so that the power supply noise occurring in the control circuit will not affect the output buffer. However, this method has had the problems that it increases both the number of power supply/grounding pins and power feed line inductance. The present invention provides a technique which, without causing the above two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.
摘要翻译：在现有技术中，存在一种方法，其中独立地提供输出缓冲器的电源线和控制电路的电源线，使得控制电路中出现的电源噪声不会影响输出缓冲器。然而，该方法存在增加电源/接地引脚数和馈电线电感的问题。本发明提供一种技术，其不会引起上述两个问题，即（1）增加电源/接地引脚数量和（2）增加的馈电线电感，防止在控制电路中引起问题的噪声变成路由并感应到输出缓冲区。更具体地，可以通过以下两种方法之一来实现上述：（A）为控制电路提供片上旁路电容器，并将控制电路的馈电路径与AC类似的输出缓冲器的馈电路径隔离方式或（B）设计电参数（插入电阻），使得引入馈电路径的任何电参数噪声的振荡模式将变为过阻尼。

6. 发明授权

US07187069B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07187069B2
公开(公告)日：2007-03-06
申请号：US10981676
申请日：2004-11-05
申请人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Yukitoshi Hirose
发明人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Yukitoshi Hirose
IPC分类号： H01L23/02 , H01L23/34
CPC分类号： H01L23/642 , H01L23/5223 , H01L23/5228 , H01L23/5286 , H01L23/647 , H01L25/105 , H01L2224/73204 , H01L2924/19105 , H01L2924/3011
摘要： The present invention provides a technique which, without causing two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.
摘要翻译：本发明提供一种技术，其不会引起两个问题，即（1）增加电源/接地引脚的数量和（2）增加的馈电线电感，防止在控制电路中引起问题的噪声变为布线并引入输出缓冲区。更具体地，可以通过以下两种方法之一来实现上述：（A）为控制电路提供片上旁路电容器，并将控制电路的馈电路径与AC类似的输出缓冲器的馈电路径隔离方式或（B）设计电参数（插入电阻），使得引入馈电路径的任何电参数噪声的振荡模式将变为过阻尼。

7. 发明授权

US07986037B2 Low noise semiconductor device 有权
标题翻译：低噪声半导体器件
公开(公告)号：US07986037B2
公开(公告)日：2011-07-26
申请号：US12068606
申请日：2008-02-08
申请人： Yutaka Uematsu , Tatsuya Saito , Hideki Osaka , Yoji Nishio , Shunichi Saito
发明人： Yutaka Uematsu , Tatsuya Saito , Hideki Osaka , Yoji Nishio , Shunichi Saito
IPC分类号： H01L23/52
CPC分类号： H05K1/0231 , H01L23/50 , H01L23/5385 , H01L23/66 , H01L2224/16225 , H01L2924/12044 , H01L2924/3011 , H05K1/09 , H05K1/111 , H05K1/167 , H05K2201/0352 , H05K2201/0391 , H05K2201/09236 , H05K2201/09309 , H05K2201/09481 , H05K2201/09781 , H05K2201/10636 , H05K2201/10674 , Y02P70/611 , H01L2924/00
摘要： As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.
摘要翻译：作为半导体芯片中的馈电路径，可以实现降低数十MHz频率范围内的反谐振阻抗的馈电路径，从而抑制半导体器件的功率噪声。通过插入将中频带中的电阻提升到电阻本身较高的部分的结构，例如半导体封装中的功率布线和电容器互连电极部件，可以有效地减少中频带中的反谐振阻抗，同时保持阻抗低在低频。

8. 发明申请

US20080290495A1 Low noise semiconductor device 有权
标题翻译：低噪声半导体器件
公开(公告)号：US20080290495A1
公开(公告)日：2008-11-27
申请号：US12068606
申请日：2008-02-08
申请人： Yutaka Uematsu , Tatsuya Saito , Hideki Osaka , Yoji Nishio , Shunichi Saito
发明人： Yutaka Uematsu , Tatsuya Saito , Hideki Osaka , Yoji Nishio , Shunichi Saito
IPC分类号： H01L23/528
CPC分类号： H05K1/0231 , H01L23/50 , H01L23/5385 , H01L23/66 , H01L2224/16225 , H01L2924/12044 , H01L2924/3011 , H05K1/09 , H05K1/111 , H05K1/167 , H05K2201/0352 , H05K2201/0391 , H05K2201/09236 , H05K2201/09309 , H05K2201/09481 , H05K2201/09781 , H05K2201/10636 , H05K2201/10674 , Y02P70/611 , H01L2924/00
摘要： As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.
摘要翻译：作为半导体芯片中的馈电路径，可以实现降低数十MHz频率范围内的反谐振阻抗的馈电路径，从而抑制半导体器件的功率噪声。通过插入将中频带中的电阻提升到电阻本身较高的部分的结构，例如半导体封装中的功率布线和电容器互连电极部件，可以有效地减少中频带中的反谐振阻抗，同时保持阻抗低在低频。

9. 发明授权

US07689944B2 Method for designing semiconductor apparatus, system for aiding to design semiconductor apparatus, computer program product therefor and semiconductor package 失效
标题翻译：半导体装置的设计方法，辅助设计半导体装置的系统，其计算机程序产品和半导体封装
公开(公告)号：US07689944B2
公开(公告)日：2010-03-30
申请号：US11511438
申请日：2006-08-29
申请人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Satoshi Isa , Yoji Nishio , Seiji Funaba , Yukitoshi Hirose
发明人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Satoshi Isa , Yoji Nishio , Seiji Funaba , Yukitoshi Hirose
IPC分类号： G06F17/50
CPC分类号： H05K3/0005 , G06F17/5068 , H01L2224/05553 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H05K1/0231 , H05K2201/10545 , H05K2201/10734 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable is represented in frequency domain, and the adjustment target includes a part of the semiconductor package. The target variable is compared with a predetermined constraint, which is represented in frequency domain, to identify a problematic section, wherein the problematic section corresponds to a frequency region at which the target variable exceeds the predetermined constraint. Design guidelines are decided to solve the identified problematic section.
摘要翻译：公开了一种考虑半导体封装中所包括的半导体芯片的功率完整性来设计包括半导体封装的半导体器件的方法。基于关于调整对象的目标信息来计算用于调整目标的目标变量，其中目标变量在频域中被表示，并且调整目标包括半导体封装的一部分。将目标变量与在频域中表示的预定约束进行比较，以识别有问题的部分，其中有问题的部分对应于目标变量超过预定约束的频率区域。决定设计指南来解决确定的问题部分。

10. 发明申请

US20070057380A1 Method for designing semiconductor apparatus, system for aiding to design semiconductor apparatus, computer program product therefor and semiconductor package 失效
标题翻译：半导体装置的设计方法，辅助设计半导体装置的系统，其计算机程序产品和半导体封装
公开(公告)号：US20070057380A1
公开(公告)日：2007-03-15
申请号：US11511438
申请日：2006-08-29
申请人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Satoshi Isa , Yoji Nishio , Seiji Funaba , Yukitoshi Hirose
发明人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Satoshi Isa , Yoji Nishio , Seiji Funaba , Yukitoshi Hirose
IPC分类号： H01L23/48
CPC分类号： H05K3/0005 , G06F17/5068 , H01L2224/05553 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H05K1/0231 , H05K2201/10545 , H05K2201/10734 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable is represented in frequency domain, and the adjustment target includes a part of the semiconductor package. The target variable is compared with a predetermined constraint, which is represented in frequency domain, to identify a problematic section, wherein the problematic section corresponds to a frequency region at which the target variable exceeds the predetermined constraint. Design guidelines are decided to solve the identified problematic section.
摘要翻译：公开了一种考虑半导体封装中所包括的半导体芯片的功率完整性来设计包括半导体封装的半导体器件的方法。基于关于调整对象的目标信息来计算用于调整目标的目标变量，其中目标变量在频域中被表示，并且调整目标包括半导体封装的一部分。将目标变量与在频域中表示的预定约束进行比较，以识别有问题的部分，其中有问题的部分对应于目标变量超过预定约束的频率区域。决定设计指南来解决确定的问题部分。

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