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1. 发明授权

US07689944B2 Method for designing semiconductor apparatus, system for aiding to design semiconductor apparatus, computer program product therefor and semiconductor package 失效
标题翻译：半导体装置的设计方法，辅助设计半导体装置的系统，其计算机程序产品和半导体封装
公开(公告)号：US07689944B2
公开(公告)日：2010-03-30
申请号：US11511438
申请日：2006-08-29
申请人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Satoshi Isa , Yoji Nishio , Seiji Funaba , Yukitoshi Hirose
发明人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Satoshi Isa , Yoji Nishio , Seiji Funaba , Yukitoshi Hirose
IPC分类号： G06F17/50
CPC分类号： H05K3/0005 , G06F17/5068 , H01L2224/05553 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H05K1/0231 , H05K2201/10545 , H05K2201/10734 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable is represented in frequency domain, and the adjustment target includes a part of the semiconductor package. The target variable is compared with a predetermined constraint, which is represented in frequency domain, to identify a problematic section, wherein the problematic section corresponds to a frequency region at which the target variable exceeds the predetermined constraint. Design guidelines are decided to solve the identified problematic section.
摘要翻译：公开了一种考虑半导体封装中所包括的半导体芯片的功率完整性来设计包括半导体封装的半导体器件的方法。基于关于调整对象的目标信息来计算用于调整目标的目标变量，其中目标变量在频域中被表示，并且调整目标包括半导体封装的一部分。将目标变量与在频域中表示的预定约束进行比较，以识别有问题的部分，其中有问题的部分对应于目标变量超过预定约束的频率区域。决定设计指南来解决确定的问题部分。

2. 发明申请

US20070057380A1 Method for designing semiconductor apparatus, system for aiding to design semiconductor apparatus, computer program product therefor and semiconductor package 失效
标题翻译：半导体装置的设计方法，辅助设计半导体装置的系统，其计算机程序产品和半导体封装
公开(公告)号：US20070057380A1
公开(公告)日：2007-03-15
申请号：US11511438
申请日：2006-08-29
申请人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Satoshi Isa , Yoji Nishio , Seiji Funaba , Yukitoshi Hirose
发明人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Satoshi Isa , Yoji Nishio , Seiji Funaba , Yukitoshi Hirose
IPC分类号： H01L23/48
CPC分类号： H05K3/0005 , G06F17/5068 , H01L2224/05553 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H05K1/0231 , H05K2201/10545 , H05K2201/10734 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable is represented in frequency domain, and the adjustment target includes a part of the semiconductor package. The target variable is compared with a predetermined constraint, which is represented in frequency domain, to identify a problematic section, wherein the problematic section corresponds to a frequency region at which the target variable exceeds the predetermined constraint. Design guidelines are decided to solve the identified problematic section.
摘要翻译：公开了一种考虑半导体封装中所包括的半导体芯片的功率完整性来设计包括半导体封装的半导体器件的方法。基于关于调整对象的目标信息来计算用于调整目标的目标变量，其中目标变量在频域中被表示，并且调整目标包括半导体封装的一部分。将目标变量与在频域中表示的预定约束进行比较，以识别有问题的部分，其中有问题的部分对应于目标变量超过预定约束的频率区域。决定设计指南来解决确定的问题部分。

3. 发明授权

US07411806B2 Memory module and memory system 有权
标题翻译：内存模块和内存系统
公开(公告)号：US07411806B2
公开(公告)日：2008-08-12
申请号：US11634405
申请日：2006-12-06
申请人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
发明人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
IPC分类号： G11C5/06 , G11C5/02
CPC分类号： G11C5/04 , G11C5/063 , G11C7/1048 , G11C11/4093 , G11C2207/105 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311 , H01L2924/19107
摘要： A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.
摘要翻译：存储器模块具有在板的前表面和后表面上共享总线的多个DRAM（115）。总线通过通孔（113）从端子（111）连接到带状线（112）的一端，并且带状线的另一端通过通孔（113）连接到另一层中的带状线孔（119）用于使线路循环。设置在终端电压端子（VTT）附近的终端电阻器（120）通过通孔连接到另一层中的环形带状线。 DRAM端子通过通孔连接到带状线。该存储器模块通过连接器安装在其上提供存储器控制器的母板上。母线的有效特性阻抗与母板线路特性阻抗匹配。

4. 发明申请

US20060006516A1 Stacked semiconductor device and semiconductor memory module 有权
标题翻译：堆叠半导体器件和半导体存储器模块
公开(公告)号：US20060006516A1
公开(公告)日：2006-01-12
申请号：US11176292
申请日：2005-07-08
申请人： Seiji Funaba , Yoji Nishio
发明人： Seiji Funaba , Yoji Nishio
IPC分类号： H01L23/02
CPC分类号： H01L23/66 , G11C5/04 , G11C5/063 , H01L24/06 , H01L24/49 , H01L25/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/06136 , H01L2224/49171 , H01L2225/06527 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/19105 , H01L2924/19106 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device module includes a wiring substrate, a plurality of stacked semiconductor devices and a damping impedance circuit. The plurality of stacked semiconductor devices are provided on the wiring substrate and connected with a signal in a stubless manner, and each of the plurality of stacked semiconductor devices comprises a plurality of semiconductor chips which are stacked. The damping impedance circuit is provided for a transmission path of the signal for an uppermost semiconductor chip as the furthest one, from the wiring substrate, of the plurality of semiconductor chips of a first stacked semiconductor device as one of the plurality of stacked semiconductor devices which is first supplied with the signal.
摘要翻译：半导体器件模块包括布线基板，多个堆叠半导体器件和阻尼阻抗电路。多个堆叠的半导体器件设置在布线基板上，并且以简单的方式与信号连接，并且多个堆叠的半导体器件中的每一个包括堆叠的多个半导体芯片。阻尼阻抗电路被设置为用于作为多个半导体器件中的一个堆叠半导体器件的第一堆叠半导体器件的多个半导体芯片中的最上半个半导体芯片的信号的距离布线基板的最远的信号的传输路径，首先提供信号。

5. 发明申请

US20050139977A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20050139977A1
公开(公告)日：2005-06-30
申请号：US11019553
申请日：2004-12-23
申请人： Yoji Nishio , Seiji Funaba
发明人： Yoji Nishio , Seiji Funaba
IPC分类号： H01L23/14 , G06F1/18 , G06F13/00 , G11C5/02 , G11C7/00 , G11C11/407 , H01L21/68 , H01L23/02 , H01L23/498 , H01L23/50 , H01L23/66 , H01L25/065 , H01L25/07 , H01L27/108 , H05K1/14
CPC分类号： H01L23/66 , G06F1/184 , G06F1/185 , G06F1/186 , G11C5/025 , H01L21/6835 , H01L23/49822 , H01L23/49833 , H01L23/50 , H01L2221/6834 , H01L2221/68368 , H01L2224/16 , H01L2924/01004 , H01L2924/0102 , H01L2924/01068 , H01L2924/13091 , H01L2924/15311 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H05K1/141 , H01L2924/00
摘要： A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided.
摘要翻译：包括多个堆叠的DRAM芯片的COC DRAM通过使用插入件安装在母板上。插入器包括Si单元和PCB。 Si单元包括Si基板和布置布线的绝缘层单元。 PCB包括用于Si单元中布线的参考平面。芯片组和COC DRAM之间的布线结构对于每个信号是相同的。因此，提供了能够进行高速运转，低功耗，大容量的存储器系统。

6. 发明授权

US06628538B2 Memory module including module data wirings available as a memory access data bus 有权
标题翻译：存储器模块包括可用作存储器访问数据总线的模块数据配线
公开(公告)号：US06628538B2
公开(公告)日：2003-09-30
申请号：US10105249
申请日：2002-03-26
申请人： Seiji Funaba , Yoshinobu Nakagome , Masashi Horiguchi , Yoji Nishio
发明人： Seiji Funaba , Yoshinobu Nakagome , Masashi Horiguchi , Yoji Nishio
IPC分类号： G11C506
CPC分类号： G11C5/06 , G11C5/04 , G11C5/063 , H01L23/5387 , H01L25/065 , H01L25/0655 , H01L25/0657 , H01L2224/16 , H01L2225/06517 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06579 , H01L2924/01055 , H01L2924/15312 , H01L2924/1532 , H01L2924/3011
摘要： A module substrate has a plurality of module data terminal pairs individually provided in association with respective chip data terminals in a plurality of memory chips, and a plurality of module data wirings which respectively connect between the plurality of module data terminal pairs. The plurality of module data wirings are connected to their corresponding chip data terminals and are configured so as to be available as a memory access data bus. In a memory system in which a plurality of memory modules are arranged in parallel, module data wirings of each individual memory modules are connected in serial form, and each individual module data wirings do not constitute branch wirings with respect to a data bus on a motherboard of the memory system. In the memory modules, parallel access for the number of bits corresponding to the width of the memory access data bus is assured.
摘要翻译：模块基板具有与多个存储器芯片中的各个芯片数据端子相关联地分别设置的多个模块数据端子对以及分别连接在多个模块数据端子对之间的多个模块数据布线。多个模块数据布线连接到它们对应的芯片数据终端，并被配置为可用作存储器访问数据总线。在并行布置多个存储器模块的存储器系统中，各个存储器模块的模块数据布线以串行形式连接，并且每个单独的模块数据布线不构成相对于主板上的数据总线的分支布线的内存系统。在存储器模块中，确保与存储器访问数据总线的宽度相对应的位数的并行访问。

7. 发明授权

US08064222B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US08064222B2
公开(公告)日：2011-11-22
申请号：US12113414
申请日：2008-05-01
申请人： Yoji Nishio , Seiji Funaba
发明人： Yoji Nishio , Seiji Funaba
IPC分类号： H05K1/11 , H05K1/14
CPC分类号： H01L23/66 , G06F1/184 , G06F1/185 , G06F1/186 , G11C5/025 , H01L21/6835 , H01L23/49822 , H01L23/49833 , H01L23/50 , H01L2221/6834 , H01L2221/68368 , H01L2224/16 , H01L2924/01004 , H01L2924/0102 , H01L2924/01068 , H01L2924/13091 , H01L2924/15311 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H05K1/141 , H01L2924/00
摘要： A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided.
摘要翻译：包括多个堆叠的DRAM芯片的COC DRAM通过使用插入件安装在母板上。插入器包括Si单元和PCB。 Si单元包括Si基板和布置布线的绝缘层单元。 PCB包括用于Si单元中布线的参考平面。芯片组和COC DRAM之间的布线结构对于每个信号是相同的。因此，提供了能够进行高速运转，低功耗，大容量的存储器系统。

8. 发明授权

US07768867B2 Stacked semiconductor device 有权
标题翻译：堆叠半导体器件
公开(公告)号：US07768867B2
公开(公告)日：2010-08-03
申请号：US11761470
申请日：2007-06-12
申请人： Yoji Nishio , Yutaka Uematsu , Seiji Funaba , Hideki Osaka , Tsutomu Hara , Koichiro Aoki
发明人： Yoji Nishio , Yutaka Uematsu , Seiji Funaba , Hideki Osaka , Tsutomu Hara , Koichiro Aoki
IPC分类号： G11C8/00
CPC分类号： G11C7/02 , G11C5/02 , G11C5/04 , H01L25/105 , H01L2924/0002 , H01L2924/15311 , H01L2924/15331 , H01L2924/00
摘要： Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.
摘要翻译：叠层半导体器件包括多个存储器芯片，堆叠在一起，其中高速传输中的波形失真被去除。堆叠半导体器件1包括堆叠在一起的多个存储器芯片11,12。作为用于每周期两次输入/输出数据的控制信号的数据选通信号（DQS）和反相数据选通信号（/ DQS）被用作两个单端数据选通信号。数据选通信号和反相数据选通信号相互配合。用于数据选通信号L4的数据选通信号线连接到第一存储芯片11的数据选通信号（DQS）焊盘。用于/ DQS信号L5的反相数据选通信号线连接到第二存储芯片11的反相数据选通信号（/ DQS）焊盘存储芯片12。

9. 发明申请

US20090245424A1 SEMICONDUCTOR DEVICE, MEMORY DEVICE AND MEMORY MODULE HAVING DIGITAL INTERFACE 有权
标题翻译：半导体器件，存储器件和具有数字接口的存储器模块
公开(公告)号：US20090245424A1
公开(公告)日：2009-10-01
申请号：US12481798
申请日：2009-06-10
申请人： Hideki Osaka , Yoji Nishio , Seiji Funaba , Kazuyoshi Shoji
发明人： Hideki Osaka , Yoji Nishio , Seiji Funaba , Kazuyoshi Shoji
IPC分类号： H03K9/00
CPC分类号： H03K5/082 , H03K5/135
摘要： An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.
摘要翻译：本发明的一个目的是通过接口接收机减少取决于数据模式的抖动。本发明的另一个目的是提供一种LSI能够自动调整抖动减少的延迟时间，以便能够控制每个设备的设置。由于根据数据模式的抖动可以根据先前状态如何被预期，所以保持由接收机接收到的数据的状态，并根据保持的状态和输入来调整提取输入数据的定时数据。作为位于接收机中的控制机构，为了确定取决于安装形式的延迟时间，驱动器以一个周期的间隔发送和接收设置的脉冲数据，并以两个周期的间隔设置脉冲数据作为测试模式。接收机具有自动控制机构，用于根据脉冲宽度不同的脉冲的上升时间与其下降时间之间的差来确定对系统最佳的延迟时间。

10. 发明授权

US07558336B2 Semiconductor device, memory device and memory module having digital interface 失效
标题翻译：半导体器件，存储器件和具有数字接口的存储器模块
公开(公告)号：US07558336B2
公开(公告)日：2009-07-07
申请号：US10982946
申请日：2004-11-08
申请人： Hideki Osaka , Yoji Nishio , Seiji Funaba , Kazuyoshi Shoji
发明人： Hideki Osaka , Yoji Nishio , Seiji Funaba , Kazuyoshi Shoji
IPC分类号： H03K9/00 , H04B3/46 , G06K5/04 , H03M13/00 , G06F13/42
CPC分类号： H03K5/082 , H03K5/135
摘要： An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.
摘要翻译：本发明的一个目的是通过接口接收机减少取决于数据模式的抖动。本发明的另一个目的是提供一种LSI能够自动调整抖动减少的延迟时间，以便能够控制每个设备的设置。由于根据数据模式的抖动可以根据先前状态如何被预期，所以保持由接收器接收到的数据的状态，并且根据保持的状态和输入来调整提取输入数据的定时数据。作为位于接收机中的控制机构，为了确定取决于安装形式的延迟时间，驱动器以一个周期的间隔发送和接收设置的脉冲数据，并以两个周期的间隔设置脉冲数据作为测试模式。接收机具有自动控制机构，用于根据脉冲宽度不同的脉冲的上升时间与其下降时间之间的差来确定对系统最佳的延迟时间。

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