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1. 发明授权

US5475395A Reflecting mirror-equipped GPS receiving antenna apparatus 失效
标题翻译：反射镜配备的GPS接收天线装置
公开(公告)号：US5475395A
公开(公告)日：1995-12-12
申请号：US306733
申请日：1994-09-15
申请人： Yutaka Nakamura , Kazunori Miyahara
发明人： Yutaka Nakamura , Kazunori Miyahara
IPC分类号： G01C15/00 , H01Q1/32 , H01Q3/16 , H01Q1/22
CPC分类号： H01Q3/16 , G01C15/00 , H01Q1/32
摘要： A reflecting mirror-equipped GPS receiving antenna apparatus comprises a reflecting mirror and a microstrip type of antenna for receiving radio waves transmitted from GPS satellites. The reflecting mirror is supported by a base member so as to be swingable about a horizontal axis as well as rotatable about a first vertical axis. The antenna is supported above the reflecting mirror so as to be rotatable about a second vertical axis which is coaxial with the first vertical axis.
摘要翻译：具有反射镜的GPS接收天线装置包括反射镜和微带型天线，用于接收从GPS卫星发射的无线电波。反射镜由基部构件支撑，以便围绕水平轴线摆动并且可围绕第一垂直轴线旋转。天线被支撑在反射镜的上方，以便能够围绕与第一垂直轴同轴的第二垂直轴线旋转。

2. 发明授权

US08497717B2 Reference frequency generating device 有权
标题翻译：参考频率发生装置
公开(公告)号：US08497717B2
公开(公告)日：2013-07-30
申请号：US13257845
申请日：2010-04-15
申请人： Kazunori Miyahara
发明人： Kazunori Miyahara
IPC分类号： H03L7/06
CPC分类号： H03L7/14 , H03L7/0996 , H03L2207/50
摘要： The disclosed is a reference frequency generating device (11), which includes a GPS receiver (21), a PLL circuit (31), a detector (28), a memory unit (29), and a controller (22). The PLL circuit (31) controls the digitally controlled oscillator (26) based on a synchronizing control signal acquired based on a reference signal from the GPS receiver (21). The memory unit (29) stores a correspondence relation between a control value of the synchronizing control signal, and a voltage value and a temperature at that time. When the reference signal is not acquired, the controller 22 determines a holdover control signal based on the correspondence relation, and the voltage and temperature detected by the detector 28, and controls the digitally controlled oscillator (26).
摘要翻译：所公开的是一种参考频率发生装置（11），其包括GPS接收器（21），PLL电路（31），检测器（28），存储单元（29）和控制器（22）。 PLL电路（31）基于基于来自GPS接收器（21）的参考信号获取的同步控制信号来控制数控振荡器（26）。存储单元（29）存储同步控制信号的控制值与电压值和当时的温度之间的对应关系。当不获取参考信号时，控制器22基于对应关系以及由检测器28检测到的电压和温度来确定保持控制信号，并控制数控振荡器（26）。

3. 发明授权

US5942765A High-temperature superconducting random access memory 失效
标题翻译：高温超导随机存取存储器
公开(公告)号：US5942765A
公开(公告)日：1999-08-24
申请号：US975108
申请日：1997-11-20
申请人： Kazunori Miyahara , Yoichi Enomoto , Shoji Tanaka
发明人： Kazunori Miyahara , Yoichi Enomoto , Shoji Tanaka
IPC分类号： G11C11/44 , H01L39/22 , H01L29/06
CPC分类号： H01L39/225 , G11C11/44
摘要： In the random access memory utilizing an oxide high-temperature superconductor, a first high-temperature superconductor layer 1, a non-superconductor layer 2, a second high-temperature superconductor layer 3 and a non-superconductor layer 4 are formed on an insulated substrate. The first high-temperature superconductor layer 1 is formed in a first loop, forming a memory storage superconductor quantum interference device by two Josephson junctions and a control current line I.sub.WX (6) and a bias current line I.sub.WY (8) in order to store the flux quantum. The second high-temperature superconductor layer 3 is formed in a second loop, forming a reading superconducting quantum interference device by two Josephson junctions and a control current line I.sub.RX (5) and a bias current line I.sub.RY (7). By use of the characteristic where the output is occurred according to the polarity of the flux quantum held by the first loop, the writing and reading of the memory is done by a binary logic of "0" and "1", and functions as a random access memory.
摘要翻译：在利用氧化物高温超导体的随机存取存储器中，在绝缘基板上形成第一高温超导体层1，非超导体层2，第二高温超导体层3和非超导体层4 。第一高温超导体层1形成在第一环中，通过两个约瑟夫逊结和控制电流线IWX（6）和偏置电流线IWY（8）形成存储器超导体量子干涉装置，以便存储通量量子。第二高温超导体层3形成在第二环路中，通过两个约瑟夫逊结和控制电流线IRX（5）和偏置电流线IRY（7）形成读取超导量子干涉装置。通过使用根据由第一环保持的通量量子的极性发生输出的特性，存储器的写入和读取由“0”和“1”的二进制逻辑完成，并且用作随机存取存储器。

4. 发明申请

US20210153917A1 BONE NAIL 有权
公开(公告)号：US20210153917A1
公开(公告)日：2021-05-27
申请号：US17167899
申请日：2021-02-04
申请人： Kazunori Miyahara , Kenneth J. Koval , Joshua R. Langford
发明人： Kazunori Miyahara , Kenneth J. Koval , Joshua R. Langford
IPC分类号： A61B17/72 , A61B17/74 , A61B17/17
摘要： A bone nail for stabilizing a fracture. The bone nail having a head portion and a stem portion. The stem portion offset from the longitudinal axis of the head portion. The nail including a continuous passageway extending from a rear edge of the nail to a front edge of the nail. The continuous passageway including a bore extending longitudinally through the head portion and both a groove and a bore in the stem portion.

5. 发明申请

US20110301895A1 PHASE MEASURING DEVICE AND FREQUENCY MEASURING DEVICE 有权
标题翻译：相位测量装置和频率测量装置
公开(公告)号：US20110301895A1
公开(公告)日：2011-12-08
申请号：US13201648
申请日：2010-02-26
申请人： Kazunori Miyahara
发明人： Kazunori Miyahara
IPC分类号： G06F19/00
CPC分类号： G01R25/00 , G01R23/02 , G01R23/15 , G04F10/005
摘要： This disclosure provides a phase measuring device that can measure phase differences with high precision using the digital circuits. A phase measuring device includes a buffer delay measuring circuit and a phase difference measuring circuit which use a TDC, respectively, and a phase difference calculator. The buffer delay measuring circuit generates delay measurement data indicating a delay amount τB between the buffers of the TDCs based on a highly precise clock signal and a sampling reference signal. The phase difference measuring circuit generates a number data row indicating a phase difference between measuring signals SS(A) and SS(B), and first and second phase difference measuring data Ds(A) and Ds(B), using the clock signal. The phase difference calculator calculates the phase difference using numbers of state data NB(A) and NB(B) based on the first and second phase difference measuring data Ds(A) and Ds(B), the number data row, and the highly precise delay amount τB obtained from the delay measurement data.
摘要翻译：本公开提供了一种可以使用数字电路以高精度测量相位差的相位测量装置。相位测量装置包括分别使用TDC的缓冲延迟测量电路和相位差测量电路以及相位差计算器。缓冲延迟测量电路基于高度精确的时钟信号和采样参考信号产生指示TDC的缓冲器之间的延迟量τB的延迟测量数据。相位差测量电路使用时钟信号产生指示测量信号SS（A）和SS（B）之间的相位差的数字数据行以及第一和第二相位差测量数据Ds（A）和Ds（B）。相位差计算器基于第一和第二相位差测量数据Ds（A）和Ds（B），数字数据行和高度数据来计算使用状态数据NB（A）和NB（B）的数量的相位差从延迟测量数据获得的精确延迟量τB。

6. 发明授权

US07760625B2 Exchange node and exchange node control method 失效
标题翻译：交换节点和交换节点控制方法
公开(公告)号：US07760625B2
公开(公告)日：2010-07-20
申请号：US11577215
申请日：2005-09-16
申请人： Noriharu Miyaho , Kazunori Miyahara
发明人： Noriharu Miyaho , Kazunori Miyahara
IPC分类号： H04L12/26 , H04L12/28 , H04J3/00
CPC分类号： H04L47/10 , H04L12/5601 , H04L43/0882 , H04L47/12 , H04L47/2408 , H04L47/283 , H04L49/602
摘要： The present invention reduces the delay time to extremely short by monitoring the output/distribution unit of the exchange node to specify the unused time slot as write destination of the data and performing priority control by the priority control signal contained in the data. The traffic congestion is resolved by performing write output to the specified time slot regardless of the communication speed of the transmission path of the data. Furthermore, the present invention aims to provide the exchange node and the exchange node control method that ensures communication quality by using the connection type as the communication method since the delay time in communication can be reduced.The exchange node 100 according to the present invention includes an input buffer unit 2, an identification unit 7, a distribution unit 5, a multiplexing circuit 9, a time slot allocation circuit 12, and an output/distribution unit 10. More preferably, a frame compression circuit 16, a frame decompression circuit 18 and a priority determination circuit 20 are arranged.
摘要翻译：本发明通过监视交换节点的输出/分配单元来将延迟时间缩短到非常短，以将未使用的时隙指定为数据的写入目的地，并通过数据中包含的优先级控制信号执行优先级控制。通过执行到指定时隙的写入输出来解决交通拥堵，而不管数据的传输路径的通信速度如何。此外，本发明的目的是提供一种交换节点和交换节点控制方法，其通过使用连接类型作为通信方法来确保通信质量，因为可以减少通信中的延迟时间。根据本发明的交换节点100包括输入缓冲单元2，识别单元7，分发单元5，复用电路9，时隙分配电路12和输出/分配单元10.更优选地，帧压缩电路16，帧解压缩电路18和优先级确定电路20。

7. 发明申请

US20120007642A1 REFERENCE FREQUENCY GENERATING DEVICE 有权
标题翻译：参考频率发生装置
公开(公告)号：US20120007642A1
公开(公告)日：2012-01-12
申请号：US13257845
申请日：2010-04-15
申请人： Kazunori Miyahara
发明人： Kazunori Miyahara
IPC分类号： H03L7/00
CPC分类号： H03L7/14 , H03L7/0996 , H03L2207/50
摘要： The disclosed is a reference frequency generating device (11), which includes a GPS receiver (21), a PLL circuit (31), a detector (28), a memory unit (29), and a controller (22). The PLL circuit (31) controls the digitally controlled oscillator (26) based on a synchronizing control signal acquired based on a reference signal from the GPS receiver (21). The memory unit (29) stores a correspondence relation between a control value of the synchronizing control signal, and a voltage value and a temperature at that time. When the reference signal is not acquired, the controller 22 determines a holdover control signal based on the correspondence relation, and the voltage and temperature detected by the detector 28, and controls the digitally controlled oscillator (26).
摘要翻译：所公开的是一种参考频率发生装置（11），其包括GPS接收器（21），PLL电路（31），检测器（28），存储单元（29）和控制器（22）。 PLL电路（31）基于基于来自GPS接收器（21）的参考信号获取的同步控制信号来控制数控振荡器（26）。存储单元（29）存储同步控制信号的控制值与电压值和当时的温度之间的对应关系。当不获取参考信号时，控制器22基于对应关系以及由检测器28检测到的电压和温度来确定保持控制信号，并控制数控振荡器（26）。

8. 发明申请

US20080084898A1 EXCHANGE NODE AND EXCHANGE NODE CONTROL METHOD 失效
标题翻译：交换节点和交换节点控制方法
公开(公告)号：US20080084898A1
公开(公告)日：2008-04-10
申请号：US11577215
申请日：2005-09-16
申请人： Noriharu Miyaho , Kazunori Miyahara
发明人： Noriharu Miyaho , Kazunori Miyahara
IPC分类号： H04J3/00
CPC分类号： H04L47/10 , H04L12/5601 , H04L43/0882 , H04L47/12 , H04L47/2408 , H04L47/283 , H04L49/602
摘要： The present invention reduces the delay time to extremely short by monitoring the output/distribution unit of the exchange node to specify the unused time slot as write destination of the data and performing priority control by the priority control signal contained in the data. The traffic congestion is resolved by performing write output to the specified time slot regardless of the communication speed of the transmission path of the data. Furthermore, the present invention aims to provide the exchange node and the exchange node control method that ensures communication quality by using the connection type as the communication method since the delay time in communication can be reduced.The exchange node 100 according to the present invention includes an input buffer unit 2, an identification unit 7, a distribution unit 5, a multiplexing circuit 9, a time slot allocation circuit 12, and an output/distribution unit 10. More preferably, a frame compression circuit 16, a frame decompression circuit 18 and a priority determination circuit 20 are arranged.
摘要翻译：本发明通过监视交换节点的输出/分配单元来将延迟时间缩短到非常短，以将未使用的时隙指定为数据的写入目的地，并通过数据中包含的优先级控制信号执行优先级控制。通过执行到指定时隙的写入输出来解决交通拥堵，而不管数据的传输路径的通信速度如何。此外，本发明的目的是提供一种交换节点和交换节点控制方法，其通过使用连接类型作为通信方法来确保通信质量，因为可以减少通信中的延迟时间。根据本发明的交换节点100包括输入缓冲单元2，识别单元7，分发单元5，多路复用电路9，时隙分配电路12和输出/分配单元10。更优选地，布置了帧压缩电路16，帧解压缩电路18和优先级确定电路20。

9. 发明授权

US09001865B2 System and device for generating reference signal, and timing signal supply device 有权
标题翻译：用于产生参考信号的系统和装置，以及定时信号供给装置
公开(公告)号：US09001865B2
公开(公告)日：2015-04-07
申请号：US13203093
申请日：2010-04-07
申请人： Kazunori Miyahara
发明人： Kazunori Miyahara
IPC分类号： H04B1/00 , G01S19/14 , H04B1/707
CPC分类号： G01S19/14 , H04B2001/70706 , H04B2201/70715
摘要： Provided is a timing signal supply device that can frequently perform a phase comparison on a side of receiving a supply of a timing signal and flexibly achieve various operation modes. A GPS receiver 11 includes a baseband processing module 16 and a PN code output terminal 26. The baseband processing module 16 performs a positioning calculation based on positioning signals received from GPS satellites. The PN code output terminal 26 is configured so as to be able to output, based on the result of the positioning calculation by the baseband processing module 16, a PN code that is repeated every second in synchronization with the coordinated universal time.
摘要翻译：提供一种定时信号供给装置，其可以在接收定时信号的供给的一方频繁地执行相位比较，并且灵活地实现各种操作模式。 GPS接收机11包括基带处理模块16和PN码输出端子26.基带处理模块16基于从GPS卫星接收到的定位信号进行定位计算。 PN码输出端子26被配置为能够基于基带处理模块16的定位计算的结果输出与协调的世界时间同步地每秒重复的PN码。

10. 发明授权

US06724216B2 Rapid single-flux-quantum logic circuit and rapid single-flux-quantum output conversion circuit 失效
标题翻译：快速单通量 - 量子逻辑电路和快速单通量 - 量子输出转换电路
公开(公告)号：US06724216B2
公开(公告)日：2004-04-20
申请号：US10142932
申请日：2002-05-13
申请人： Hideo Suzuki , Shuichi Nagasawa , Kazunori Miyahara , Youichi Enomoto
发明人： Hideo Suzuki , Shuichi Nagasawa , Kazunori Miyahara , Youichi Enomoto
IPC分类号： H03K19195
CPC分类号： H03K19/1954
摘要： A rapid single-flux-quantum RSFQ logic circuit includes a first circuit portion having a first end grounded and having in-series connected first and second Josephson junctions. A second circuit portion has a first end grounded and has in-series connected third and fourth Josephson junctions. A first inductance element connects a second end of the first circuit portion to a second end of the second circuit portion. A tap is provided in the first inductance element, an input current signal being supplied to the tap. A bias current source is connected to a first connection node between the first and second Josephson junctions. A second inductance element connects the first connection node to a second connection node between the third and fourth Josephson junctions. A superconducting quantum interference device has fifth and sixth Josephson junctions and is coupled to the second inductance element through a magnetic field.
摘要翻译：快速单通量量子RSFQ逻辑电路包括第一电路部分，其具有接地的第一端并具有串联连接的第一和第二约瑟夫逊结。第二电路部分具有第一端接地并具有串联连接的第三和第四约瑟夫逊结。第一电感元件将第一电路部分的第二端连接到第二电路部分的第二端。在第一电感元件中提供抽头，输入电流信号被提供给抽头。偏置电流源连接到第一和第二约瑟夫逊结之间的第一连接节点。第二电感元件将第一连接节点连接到第三和第四约瑟夫森结之间的第二连接节点。超导量子干涉装置具有第五和第六约瑟夫逊结，并且通过磁场耦合到第二电感元件。

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