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1. 发明授权

US06605868B2 Insulating substrate including multilevel insulative ceramic layers joined with an intermediate layer 有权
标题翻译：绝缘基板包括与中间层连接的多层绝缘陶瓷层
公开(公告)号：US06605868B2
公开(公告)日：2003-08-12
申请号：US09457335
申请日：1999-12-09
申请人： Yutaka Ishiwata , Kosoku Nagata , Toshio Shimizu , Hiroyuki Hiramoto , Yasuhiko Taniguchi , Kouji Araki , Hiroshi Fukuyoshi , Hiroshi Komorita
发明人： Yutaka Ishiwata , Kosoku Nagata , Toshio Shimizu , Hiroyuki Hiramoto , Yasuhiko Taniguchi , Kouji Araki , Hiroshi Fukuyoshi , Hiroshi Komorita
IPC分类号： H05K346
CPC分类号： H05K1/0256 , H01L23/34 , H01L23/49822 , H01L23/562 , H01L24/48 , H01L2224/05599 , H01L2224/48137 , H01L2224/85399 , H01L2924/00014 , H01L2924/01019 , H01L2924/01057 , H01L2924/01079 , H01L2924/01322 , H01L2924/16152 , H01L2924/181 , H05K1/0306 , H05K2201/09145 , Y10S428/901 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49165 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.
摘要翻译：绝缘基板（1）具有彼此层叠的绝缘陶瓷层（2,3），由与陶瓷层的材料不同并且布置在相邻的陶瓷层之间的材料制成的中间层（4）将相邻的陶瓷层彼此接合，接合到顶部陶瓷层的顶表面的第一导电层（5）和接合到陶瓷的底部陶瓷层的底表面的第二导电层（6）层。即使陶瓷层中的任何一个具有低于设计强度的强度并且由于例如热应力而引起断裂，剩余的陶瓷层声音可以确保绝缘基板的规定的击穿电压。

2. 发明授权

US07263766B2 Insulating substrate, manufacturing method thereof, and module semiconductor device with insulating substrate 有权
标题翻译：绝缘基板，其制造方法以及具有绝缘基板的模块半导体器件
公开(公告)号：US07263766B2
公开(公告)日：2007-09-04
申请号：US10351312
申请日：2003-01-27
申请人： Yutaka Ishiwata , Kosoku Nagata , Toshio Shimizu , Hiroyuki Hiramoto , Yasuhiko Taniguchi , Kouji Araki , Hiroshi Fukuyoshi , Hiroshi Komorita
发明人： Yutaka Ishiwata , Kosoku Nagata , Toshio Shimizu , Hiroyuki Hiramoto , Yasuhiko Taniguchi , Kouji Araki , Hiroshi Fukuyoshi , Hiroshi Komorita
IPC分类号： H05K3/00 , H05K1/00 , H05K1/18 , H05K7/00
CPC分类号： H05K1/0256 , H01L23/34 , H01L23/49822 , H01L23/562 , H01L24/48 , H01L2224/05599 , H01L2224/48137 , H01L2224/85399 , H01L2924/00014 , H01L2924/01019 , H01L2924/01057 , H01L2924/01079 , H01L2924/01322 , H01L2924/16152 , H01L2924/181 , H05K1/0306 , H05K2201/09145 , Y10S428/901 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49165 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.
摘要翻译：绝缘基板（1）具有彼此层叠的绝缘陶瓷层（2,3），由与陶瓷层的材料不同并且布置在相邻的陶瓷层之间的材料制成的中间层（4）将相邻的陶瓷层彼此接合，接合到顶部陶瓷层的顶表面的第一导电层（5）和接合到陶瓷的底部陶瓷层的底表面的第二导电层（6）层。即使陶瓷层中的任何一个具有低于设计强度的强度并且由于例如热应力而引起断裂，剩余的陶瓷层声音可以确保绝缘基板的规定的击穿电压。

3. 发明授权

US08587105B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08587105B2
公开(公告)日：2013-11-19
申请号：US13424345
申请日：2012-03-19
申请人： Junichi Nakao , Hiroshi Fukuyoshi
发明人： Junichi Nakao , Hiroshi Fukuyoshi
IPC分类号： H01L23/22
CPC分类号： H01L23/049 , H01L23/10 , H01L23/24 , H01L23/3735 , H01L23/49811 , H01L23/49844 , H01L24/33 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/072 , H01L25/18 , H01L2224/32145 , H01L2224/32225 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40095 , H01L2224/40225 , H01L2224/40491 , H01L2224/40991 , H01L2224/45124 , H01L2224/45147 , H01L2224/48227 , H01L2224/4846 , H01L2224/48472 , H01L2224/49111 , H01L2224/49175 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/84801 , H01L2924/01047 , H01L2924/1203 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/15787 , H01L2924/30107 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor device includes a first semiconductor chip, a buffer body, and a terminal lead. The first semiconductor chip includes a first electrode and a second electrode provided on a side opposite to the first electrode. The first semiconductor chip is configured to allow a current to flow between the first electrode and the second electrode. The buffer body includes a lower metal foil, a ceramic piece, and an upper metal foil. The lower metal foil is electrically connected to the second electrode. The ceramic piece is provided on the second electrode with the lower metal foil interposed. The upper metal foil is provided on a side of the ceramic piece opposite to the lower metal foil to be electrically connected to the lower metal foil. The terminal lead has one end provided on the upper metal foil and electrically connected to the upper metal foil.
摘要翻译：半导体器件包括第一半导体芯片，缓冲体和端子引线。第一半导体芯片包括第一电极和设置在与第一电极相对的一侧的第二电极。第一半导体芯片被配置为允许电流在第一电极和第二电极之间流动。缓冲体包括下金属箔，陶瓷片和上金属箔。下部金属箔电连接到第二电极。陶瓷片设置在第二电极上，下部金属箔插入。上部金属箔设置在与下部金属箔相对的陶瓷片的一侧，以电连接到下部金属箔。端子引线的一端设置在上金属箔上并与上金属箔电连接。

4. 发明授权

US08519265B2 Power module 有权
标题翻译：电源模块
公开(公告)号：US08519265B2
公开(公告)日：2013-08-27
申请号：US12885393
申请日：2010-09-17
申请人： Junichi Nakao , Hiroshi Fukuyoshi
发明人： Junichi Nakao , Hiroshi Fukuyoshi
IPC分类号： H01R13/46
CPC分类号： H01L25/072 , H01L23/24 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L2924/01079 , H01L2924/01322 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： According to one embodiment, a power module includes a metal base, a ceramic substrate, a semiconductor chip, a nut holder housing a nut, an electrode terminal and a casing. The ceramic substrate is connected to an upper surface of the metal base via a lower electrode. The semiconductor chip is located on a first major surface of the ceramic substrate. The electrode terminal includes a bent portion surrounding a nut holder. The electrode terminal includes a first connecting portion extending perpendicularly to the bent portion from one end of the bent portion, and being located on the first major surface via an upper electrode, and electrically connected to the semiconductor chip. A casing is bonded to the metal base to enclose the semiconductor chip and the electrode terminal. An upper end portion of the bent portion of the electrode terminal is exposed to outside of the casing through the opening.
摘要翻译：根据一个实施例，功率模块包括金属基座，陶瓷基板，半导体芯片，容纳螺母的螺母保持器，电极端子和壳体。陶瓷基板经由下部电极与金属基体的上表面连接。半导体芯片位于陶瓷基板的第一主表面上。电极端子包括围绕螺母保持器的弯曲部分。电极端子包括从弯曲部分的一端垂直于弯曲部分延伸并且经由上电极位于第一主表面上并电连接到半导体芯片的第一连接部分。壳体接合到金属基底以包围半导体芯片和电极端子。电极端子的弯曲部分的上端部分通过开口暴露于外壳外部。

5. 发明申请

US20110069458A1 POWER MODULE 有权
标题翻译：电源模块
公开(公告)号：US20110069458A1
公开(公告)日：2011-03-24
申请号：US12885393
申请日：2010-09-17
申请人： Junichi Nakao , Hiroshi Fukuyoshi
发明人： Junichi Nakao , Hiroshi Fukuyoshi
IPC分类号： H05K7/00
CPC分类号： H01L25/072 , H01L23/24 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L2924/01079 , H01L2924/01322 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： According to one embodiment, a power module includes a metal base, a ceramic substrate, a semiconductor chip, a nut holder housing a nut, an electrode terminal and a casing. The ceramic substrate is connected to an upper surface of the metal base via a lower electrode. The semiconductor chip is located on a first major surface of the ceramic substrate. The electrode terminal includes a bent portion surrounding a nut holder. The electrode terminal includes a first connecting portion extending perpendicularly to the bent portion from one end of the bent portion, and being located on the first major surface via an upper electrode, and electrically connected to the semiconductor chip. A casing is bonded to the metal base to enclose the semiconductor chip and the electrode terminal. An upper end portion of the bent portion of the electrode terminal is exposed to outside of the casing through the opening.
摘要翻译：根据一个实施例，功率模块包括金属基座，陶瓷基板，半导体芯片，容纳螺母的螺母保持器，电极端子和壳体。陶瓷基板经由下部电极与金属基体的上表面连接。半导体芯片位于陶瓷基板的第一主表面上。电极端子包括围绕螺母保持器的弯曲部分。电极端子包括从弯曲部分的一端垂直于弯曲部分延伸并且经由上电极位于第一主表面上并电连接到半导体芯片的第一连接部分。壳体接合到金属基底以包围半导体芯片和电极端子。电极端子的弯曲部分的上端部分通过开口暴露于外壳外部。

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