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1. 发明授权

US08324090B2 Method to improve dielectric quality in high-k metal gate technology 有权
标题翻译：提高高k金属栅极技术介质质量的方法
公开(公告)号：US08324090B2
公开(公告)日：2012-12-04
申请号：US12338787
申请日：2008-12-18
申请人： Yuri Masuoka , Peng-Fu Hsu , Huan-Tsung Huang , Kuo-Tai Huang , Yong-Tian Hou , Carlos H. Diaz
发明人： Yuri Masuoka , Peng-Fu Hsu , Huan-Tsung Huang , Kuo-Tai Huang , Yong-Tian Hou , Carlos H. Diaz
IPC分类号： H01L21/4763 , H01L25/11 , H01L29/78
CPC分类号： H01L29/4925 , H01L21/28061 , H01L21/28185 , H01L21/28194 , H01L21/823842 , H01L29/513 , H01L29/517
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region. The first gate stack includes the high-k dielectric layer, the first capping layer, the layer containing Si, and the metal layer and the second gate stack includes the high-k dielectric layer, the second capping layer, the layer containing Si, and the metal layer.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括提供具有第一有源区和第二有源区的半导体衬底，提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，形成第一覆盖层和第二覆盖层覆盖在高k电介质层上，覆盖第一区域的第一覆盖层和覆盖第二区域的第二封盖层，在第一和第二覆盖层上形成含有硅（Si）的层，形成金属层所述层包含Si，并且在所述第一区域上形成第一栅极堆叠，并且在所述第二有源区域上形成第二栅极堆叠。第一栅极堆叠包括高k电介质层，第一覆盖层，含有Si的层，金属层和第二栅极堆叠包括高k电介质层，第二覆盖层，含有Si的层和金属层。

2. 发明申请

US20100052063A1 METHOD TO IMPROVE DIELECTRIC QUALITY IN HIGH-K METAL GATE TECHNOLOGY 有权
标题翻译：在高K金属门技术中提高介电质量的方法
公开(公告)号：US20100052063A1
公开(公告)日：2010-03-04
申请号：US12338787
申请日：2008-12-18
申请人： Yuri Masuoka , Peng-Fu Hsu , Huan-Tsung Huang , Kuo-Tai Huang , Carlos H. Diaz , Yong-Tian Hou
发明人： Yuri Masuoka , Peng-Fu Hsu , Huan-Tsung Huang , Kuo-Tai Huang , Carlos H. Diaz , Yong-Tian Hou
IPC分类号： H01L25/11 , H01L21/4763 , H01L29/78
CPC分类号： H01L29/4925 , H01L21/28061 , H01L21/28185 , H01L21/28194 , H01L21/823842 , H01L29/513 , H01L29/517
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region. The first gate stack includes the high-k dielectric layer, the first capping layer, the layer containing Si, and the metal layer and the second gate stack includes the high-k dielectric layer, the second capping layer, the layer containing Si, and the metal layer.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括提供具有第一有源区和第二有源区的半导体衬底，提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，形成第一覆盖层和第二覆盖层覆盖在高k电介质层上，覆盖第一区域的第一覆盖层和覆盖第二区域的第二封盖层，在第一和第二覆盖层上形成含有硅（Si）的层，形成金属层所述层包含Si，并且在所述第一区域上形成第一栅极堆叠，并且在所述第二有源区域上形成第二栅极堆叠。第一栅极堆叠包括高k电介质层，第一覆盖层，含有Si的层，金属层和第二栅极堆叠包括高k电介质层，第二覆盖层，含有Si的层和金属层。

3. 发明授权

US08415749B2 Semiconductor structure with dielectric-sealed doped region 有权
公开(公告)号：US08415749B2
公开(公告)日：2013-04-09
申请号：US11788226
申请日：2007-04-19
申请人： Huan-Tsung Huang , Kou-Cheng Wu , Carlos H. Diaz
发明人： Huan-Tsung Huang , Kou-Cheng Wu , Carlos H. Diaz
IPC分类号： H01L29/51
CPC分类号： H01L21/76232 , H01L29/0653 , H01L29/66636 , H01L29/66651
摘要： Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired.

4. 发明申请

US20080237750A1 Silicided metal gate for multi-threshold voltage configuration 有权
标题翻译：硅化金属栅极，用于多阈值电压配置
公开(公告)号：US20080237750A1
公开(公告)日：2008-10-02
申请号：US11728809
申请日：2007-03-27
申请人： Ching-Wei Tsai , Chih-Hao Wang , Wei-Jung Lin , Huan-Tsung Huang , Carlos H. Diaz
发明人： Ching-Wei Tsai , Chih-Hao Wang , Wei-Jung Lin , Huan-Tsung Huang , Carlos H. Diaz
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L27/088 , H01L21/28097 , H01L21/82345 , H01L29/4975 , H01L29/66545 , H01L29/7833
摘要： A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not.
摘要翻译：具有改进的功函数和良好的DIBL（漏极诱发的势垒降低）和SCE（短沟道效应）特性的低电压阈值MOSFET（MOS场效应晶体管）的PMOS（p沟道金属氧化物半导体）器件，以及一种方法用于制造这样的装置。 PMOS器件包括设置在衬底上并包括硅化栅电极的栅极结构。硅化物优选为富镍，并且包括在栅电极和将栅电极与衬底分离的电介质层之间的界面处或附近的峰值铂浓度。通过多步快速热退火或类似方法制备铂峰区域。 PMOS器件还可以包括两个这样的MOSFET，其中一个是硼掺杂的，其中一个不是。

5. 发明授权

US07768072B2 Silicided metal gate for multi-threshold voltage configuration 有权
标题翻译：硅化金属栅极，用于多阈值电压配置
公开(公告)号：US07768072B2
公开(公告)日：2010-08-03
申请号：US11728809
申请日：2007-03-27
申请人： Ching-Wei Tsai , Chih-Hao Wang , Wei-Jung Lin , Huan-Tsung Huang , Carlos H. Diaz
发明人： Ching-Wei Tsai , Chih-Hao Wang , Wei-Jung Lin , Huan-Tsung Huang , Carlos H. Diaz
IPC分类号： H01L29/94
CPC分类号： H01L27/088 , H01L21/28097 , H01L21/82345 , H01L29/4975 , H01L29/66545 , H01L29/7833
摘要： A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not.
摘要翻译：具有改进的功函数和良好的DIBL（漏极诱发的势垒降低）和SCE（短沟道效应）特性的低电压阈值MOSFET（MOS场效应晶体管）的PMOS（p沟道金属氧化物半导体）器件，以及一种方法用于制造这样的装置。 PMOS器件包括设置在衬底上并包括硅化栅电极的栅极结构。硅化物优选为富镍，并且包括在栅电极和将栅电极与衬底分离的电介质层之间的界面处或附近的峰值铂浓度。通过多步快速热退火或类似方法制备铂峰区域。 PMOS器件还可以包括两个这样的MOSFET，其中一个是硼掺杂的，其中一个不是。

6. 发明申请

US20080258185A1 Semiconductor structure with dielectric-sealed doped region 有权
标题翻译：具有绝缘密封掺杂区域的半导体结构
公开(公告)号：US20080258185A1
公开(公告)日：2008-10-23
申请号：US11788226
申请日：2007-04-19
申请人： Huan-Tsung Huang , Kuo-Cheng Wu , Carlos H. Diaz
发明人： Huan-Tsung Huang , Kuo-Cheng Wu , Carlos H. Diaz
IPC分类号： H01L29/772 , H01L29/78
CPC分类号： H01L21/76232 , H01L29/0653 , H01L29/66636 , H01L29/66651
摘要： Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired.
摘要翻译：泄漏电流可以通过形成密封电介质来代替源极/漏极区域和衬底材料之间的常规结点而大大减小。在用半导体材料填充沟槽之前，在衬底中形成沟槽，并且用密封电介质衬里。优选地，沟槽被过度填充，并且CMP工艺使过填充材料平坦化。如果需要，可以在平坦化之后在沟槽顶上生长外延层。

7. 发明授权

US08679926B2 Local charge and work function engineering on MOSFET 有权
标题翻译： MOSFET的局部充电和工作功能工程
公开(公告)号：US08679926B2
公开(公告)日：2014-03-25
申请号：US13232154
申请日：2011-09-14
申请人： Huan-Tsung Huang , Shyh-Horng Yang , Yuri Masuoka , Ken-Ichi Goto
发明人： Huan-Tsung Huang , Shyh-Horng Yang , Yuri Masuoka , Ken-Ichi Goto
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L21/28088 , H01L29/42376 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/6659
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.
摘要翻译：本发明提供一种半导体器件。半导体器件包括具有源极区和漏极区的半导体衬底，限定从源极到漏极的第一维度; 以及设置在所述半导体衬底上并部分插入在所述源极区域和所述漏极区域之间的栅极堆叠。栅极堆叠包括设置在半导体衬底上的高k电介质层; 第一金属特征设置在高k电介质层上，第一金属栅极特征具有第一功函数并限定与第一维平行的第二维度; 以及具有不同于所述第一功函数的第二功函数并且限定与所述第一尺寸平行的第三尺寸的第二金属特征，所述第三尺寸小于所述第二尺寸。

8. 发明申请

US20120003804A1 Local Charge and Work Function Engineering on MOSFET 有权
标题翻译： MOSFET的局部充电和工作功能工程
公开(公告)号：US20120003804A1
公开(公告)日：2012-01-05
申请号：US13232154
申请日：2011-09-14
申请人： Huan-Tsung Huang , Shyh-Horng Yang , Yuri Masuoka , Ken-Ichi Goto
发明人： Huan-Tsung Huang , Shyh-Horng Yang , Yuri Masuoka , Ken-Ichi Goto
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/7833 , H01L21/28088 , H01L29/42376 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/6659
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.
摘要翻译：本发明提供一种半导体器件。半导体器件包括具有源极区和漏极区的半导体衬底，限定从源极到漏极的第一维度; 以及设置在所述半导体衬底上并部分插入在所述源极区域和所述漏极区域之间的栅极堆叠。栅极堆叠包括设置在半导体衬底上的高k电介质层; 第一金属特征设置在高k电介质层上，第一金属栅极特征具有第一功函数并限定与第一维平行的第二维度; 以及具有不同于所述第一功函数的第二功函数并且限定与所述第一尺寸平行的第三尺寸的第二金属特征，所述第三尺寸小于所述第二尺寸。

9. 发明授权

US08030718B2 Local charge and work function engineering on MOSFET 有权
标题翻译： MOSFET的局部充电和工作功能工程
公开(公告)号：US08030718B2
公开(公告)日：2011-10-04
申请号：US12424170
申请日：2009-04-15
申请人： Huan-Tsung Huang , Shyh-Horng Yang , Yuri Masuoka , Ken-Ichi Goto
发明人： Huan-Tsung Huang , Shyh-Horng Yang , Yuri Masuoka , Ken-Ichi Goto
IPC分类号： H01L29/76
CPC分类号： H01L29/7833 , H01L21/28088 , H01L29/42376 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/6659
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.
摘要翻译：本发明提供一种半导体器件。半导体器件包括具有源极区和漏极区的半导体衬底，限定从源极到漏极的第一维度; 以及设置在所述半导体衬底上并部分插入在所述源极区域和所述漏极区域之间的栅极堆叠。栅极堆叠包括设置在半导体衬底上的高k电介质层; 第一金属特征设置在高k电介质层上，第一金属栅极特征具有第一功函数并限定与第一维平行的第二维度; 以及具有不同于所述第一功函数的第二功函数并且限定与所述第一尺寸平行的第三尺寸的第二金属特征，所述第三尺寸小于所述第二尺寸。

10. 发明授权

US08357581B2 Transistor performance improving method with metal gate 有权
标题翻译：晶体管性能改进方法与金属门
公开(公告)号：US08357581B2
公开(公告)日：2013-01-22
申请号：US13217442
申请日：2011-08-25
申请人： Yuri Masuoka , Huan-Tsung Huang
发明人： Yuri Masuoka , Huan-Tsung Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/28088 , H01L21/823807 , H01L21/823835 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/7833 , H01L29/7845
摘要： The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.
摘要翻译：本公开提供了制造具有金属栅极叠层的半导体器件的方法。该方法包括在半导体衬底上形成高k电介质材料层; 在所述高k电介质材料层上形成第一金属层; 在所述第一金属层上形成硅层; 图案化硅层，第一金属层和高k电介质材料层以形成栅叠层; 并进行硅化处理以完全将硅层改变为硅化物电极。

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