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1. 发明授权

US08288280B2 Conductor removal process 有权
标题翻译：导体去除过程
公开(公告)号：US08288280B2
公开(公告)日：2012-10-16
申请号：US11780024
申请日：2007-07-19
申请人： Yung-Tai Hung , Chin-Tsan Yeh , Chin-Ta Su , Ling-Wu Yang , Tung-Han Chuang
发明人： Yung-Tai Hung , Chin-Tsan Yeh , Chin-Ta Su , Ling-Wu Yang , Tung-Han Chuang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/3212 , H01L21/32105
摘要： A conductor removal process is described, which is applied to a substrate that has thereon a plurality of patterns and a blanket conductor layer covering the patterns. An upper portion of the blanket conductor layer entirely over the patterns is oxidized to form a dielectric layer. A CMP step is performed to remove the dielectric layer and a portion of the remaining conductor layer in turn and thereby expose the patterns.
摘要翻译：描述了导体去除工艺，其应用于其上具有多个图案的基板和覆盖图案的覆盖层导体层。橡皮布导体层的整个图案上方的上部被氧化以形成电介质层。执行CMP步骤以依次去除电介质层和剩余导体层的一部分，从而暴露图案。

2. 发明申请

US20090023289A1 CONDUCTOR REMOVAL PROCESS 有权
标题翻译：导线器拆卸过程
公开(公告)号：US20090023289A1
公开(公告)日：2009-01-22
申请号：US11780024
申请日：2007-07-19
申请人： Yung-Tai Hung , Chin-Tsan Yeh , Chin-Ta Su , Ling-Wu Yang , Tung-Han Chuang
发明人： Yung-Tai Hung , Chin-Tsan Yeh , Chin-Ta Su , Ling-Wu Yang , Tung-Han Chuang
IPC分类号： H01L21/461
CPC分类号： H01L21/3212 , H01L21/32105
摘要： A conductor removal process is described, which is applied to a substrate that has thereon a plurality of patterns and a blanket conductor layer covering the patterns. An upper portion of the blanket conductor layer entirely over the patterns is oxidized to form a dielectric layer. A CMP step is performed to remove the dielectric layer and a portion of the remaining conductor layer in turn and thereby expose the patterns.
摘要翻译：描述了导体去除工艺，其应用于其上具有多个图案的基板和覆盖图案的覆盖层导体层。橡皮布导体层的整个图案上方的上部被氧化以形成电介质层。执行CMP步骤以依次去除电介质层和剩余导体层的一部分，从而暴露图案。

3. 发明申请

US20130241075A1 CONTACT OR VIA CRITICAL DIMENSION CONTROL WITH NOVEL CLOSED LOOP CONTROL SYSTEM IN CHEMICAL MECHANICAL PLANARIZATION PROCESS 审中-公开
标题翻译：联系或通过化学机械平面化过程中的新型闭环控制系统的关键尺寸控制
公开(公告)号：US20130241075A1
公开(公告)日：2013-09-19
申请号：US13418920
申请日：2012-03-13
申请人： Chin-Tsan Yeh , Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su
发明人： Chin-Tsan Yeh , Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su
IPC分类号： H01L21/306 , H01L29/30 , B24B49/00
CPC分类号： B24B37/013 , H01L21/3212 , H01L21/7684 , H01L22/12 , H01L22/20
摘要： Closed loop control may be used to improve uniformity of contact or via critical dimension using chemical mechanical planarization. For example, real-time closed loop control may be used to adjust oxide buffing or over-polishing time in a chemical mechanical planarization process to more uniformly and consistently achieve a target critical dimension of a semiconductor wafer.
摘要翻译：闭环控制可用于通过化学机械平面化改善接触的均匀性或通过临界尺寸。例如，实时闭环控制可用于在化学机械平面化工艺中调节氧化物抛光或过抛光时间，以更均匀且一致地实现半导体晶片的目标临界尺寸。

4. 发明授权

US08445982B2 Method of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US08445982B2
公开(公告)日：2013-05-21
申请号：US13156933
申请日：2011-06-09
申请人： Chin-Tsan Yeh , Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su
发明人： Chin-Tsan Yeh , Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A polysilicon structure and method of forming the polysilicon structure are disclosed, where the method includes a two-step deposition and planarization process. The disclosed process reduces the likelihood of defects such as voids, particularly where polysilicon is deposited in a trench having a high aspect ratio. A first polysilicon structure is deposited that includes a trench liner portion and a first upper portion. The trench liner portion only partially fills the trench, while the first upper portion extends over the adjacent field isolation structures. Next, at least a portion of the first upper portion of the first polysilicon structure is removed. A second polysilicon structure is then deposited that includes a trench plug portion and a second upper portion. The trench is filled by the plug portion, while the second upper portion extends over the adjacent field isolation structures. The second upper portion is then removed.
摘要翻译：公开了多晶硅结构和形成多晶硅结构的方法，其中该方法包括两步沉积和平坦化处理。所公开的方法降低诸如空隙的缺陷的可能性，特别是在具有高纵横比的沟槽中沉积多晶硅时。沉积包括沟槽衬垫部分和第一上部部分的第一多晶硅结构。沟槽衬垫部分仅部分地填充沟槽，而第一上部部分在相邻的隔离结构上延伸。接下来，去除第一多晶硅结构的第一上部的至少一部分。然后沉积包括沟槽塞部分和第二上部部分的第二多晶硅结构。沟槽由插头部分填充，而第二上部部分延伸在相邻的隔离结构上。然后移除第二个上部。

5. 发明申请

US20120313214A1 POLYSILICON STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：多晶硅结构及其制造方法
公开(公告)号：US20120313214A1
公开(公告)日：2012-12-13
申请号：US13156933
申请日：2011-06-09
申请人： Chin-Tsan Yeh , Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su
发明人： Chin-Tsan Yeh , Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76232
摘要： A polysilicon structure and method of forming the polysilicon structure are disclosed, where the method includes a two-step deposition and planarization process. The disclosed process reduces the likelihood of defects such as voids, particularly where polysilicon is deposited in a trench having a high aspect ratio. A first polysilicon structure is deposited that includes a trench liner portion and a first upper portion. The trench liner portion only partially fills the trench, while the first upper portion extends over the adjacent field isolation structures. Next, at least a portion of the first upper portion of the first polysilicon structure is removed. A second polysilicon structure is then deposited that includes a trench plug portion and a second upper portion. The trench is filled by the plug portion, while the second upper portion extends over the adjacent field isolation structures. The second upper portion is then removed.
摘要翻译：公开了多晶硅结构和形成多晶硅结构的方法，其中该方法包括两步沉积和平坦化处理。所公开的方法降低诸如空隙的缺陷的可能性，特别是在具有高纵横比的沟槽中沉积多晶硅时。沉积包括沟槽衬垫部分和第一上部部分的第一多晶硅结构。沟槽衬垫部分仅部分地填充沟槽，而第一上部部分在相邻的隔离结构上延伸。接下来，去除第一多晶硅结构的第一上部的至少一部分。然后沉积包括沟槽塞部分和第二上部部分的第二多晶硅结构。沟槽由插塞部分填充，而第二上部部分延伸在相邻的隔离结构上。然后移除第二个上部。

6. 发明授权

US08047899B2 Pad and method for chemical mechanical polishing 有权
标题翻译：化学机械抛光垫和方法
公开(公告)号：US08047899B2
公开(公告)日：2011-11-01
申请号：US11878654
申请日：2007-07-26
申请人： Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su , Kuang-Chao Chen
发明人： Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su , Kuang-Chao Chen
IPC分类号： B24B7/22 , B24D3/34
CPC分类号： B24B37/24 , B24D3/346
摘要： A method for chemical-mechanical polishing two adjacent structures of a semiconductor device is provided. The method for mechanical polishing comprising: (a) providing a semiconductor device comprising a recess formed in a surface thereof, a first layer formed over the surface, and a second layer filled with the recess and formed on the first layer; and (b) substantially polishing the first and second layer with a pad and a substantially inhibitor-free slurry, wherein the pad comprising a corrosion inhibitor of the second layer.
摘要翻译：提供了半导体器件的两个相邻结构的化学机械抛光方法。一种用于机械抛光的方法，包括：（a）提供半导体器件，其包括在其表面形成的凹部，形成在所述表面上的第一层，以及填充有所述凹部并形成在所述第一层上的第二层; 和（b）用垫和基本上无抑制剂的浆料基本上抛光第一层和第二层，其中该垫包括第二层的腐蚀抑制剂。

7. 发明申请

US20080315420A1 Metal pad formation method and metal pad structure using the same 有权
标题翻译：金属垫形成方法和金属垫结构使用相同
公开(公告)号：US20080315420A1
公开(公告)日：2008-12-25
申请号：US11819011
申请日：2007-06-25
申请人： Yung-Tai Hung , Jen-Chuan Pan , Chin-Ta Su , Ta-Hung Yang
发明人： Yung-Tai Hung , Jen-Chuan Pan , Chin-Ta Su , Ta-Hung Yang
IPC分类号： H01L23/485 , H01L21/441
CPC分类号： H01L24/02 , H01L22/32 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01016 , H01L2924/01018 , H01L2924/01033 , H01L2924/01074 , H01L2924/01327
摘要： A metal pad formation method and metal pad structure using the same are provided. A wider first pad metal is formed together with a first metal. A dielectric layer is then deposited thereon. A first opening and a second opening are formed in the dielectric layer to respectively expose the first metal and the first pad metal. Then, the first opening is filled by W metal to generate a first via. Finally, a second metal and a second pad metal are formed to respectively cover the first via and the first pad metal to generate the metal pad.
摘要翻译：提供了一种使用其的金属焊盘形成方法和金属焊盘结构。与第一金属一起形成较宽的第一焊盘金属。然后在其上沉积介电层。在电介质层中形成第一开口和第二开口以分别暴露第一金属和第一焊盘金属。然后，第一开口由W金属填充以产生第一通孔。最后，形成第二金属和第二焊盘金属，以分别覆盖第一通孔和第一焊盘金属以产生金属焊盘。

8. 发明申请

US20130113031A1 KINK POLY STRUCTURE FOR IMPROVING RANDOM SINGLE BIT FAILURE 有权
标题翻译：用于改善随机单位故障的消除聚合结构
公开(公告)号：US20130113031A1
公开(公告)日：2013-05-09
申请号：US13288275
申请日：2011-11-03
申请人： Shing Ann Luo , Yung-Tai Hung , Chin-Ta Su , Tahone Yagn
发明人： Shing Ann Luo , Yung-Tai Hung , Chin-Ta Su , Tahone Yagn
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L21/28114 , H01L21/28273 , H01L27/10802 , H01L27/11521 , H01L27/11558 , H01L27/1156 , H01L29/42324 , H01L29/42328 , H01L29/7841
摘要： A memory cell having a kinked polysilicon layer structure, or a polysilicon layer structure with a top portion being narrower than a bottom portion, may greatly reduce random single bit (RSB) failures and may improve high density plasma (HDP) oxide layer fill-in by reducing defects caused by various impurities and/or a polysilicon layer short path. A kinked polysilicon layer structure may also be applied to floating gate memory cells either at the floating gate structure or the control gate structure.
摘要翻译：具有扭结多晶硅层结构的存储单元或具有比底部部分更窄的顶部的多晶硅层结构可以大大减少随机单位（RSB）故障，并且可以改善高密度等离子体（HDP）氧化物层填充通过减少由各种杂质和/或多晶硅层短路导致的缺陷。扭转多晶硅层结构也可以在浮动栅极结构或控制栅极结构处施加到浮动栅极存储器单元。

9. 发明申请

US20120040532A1 PAD AND METHOD FOR CHEMICAL MECHANICAL POLISHING 审中-公开
标题翻译： PAD和化学机械抛光方法
公开(公告)号：US20120040532A1
公开(公告)日：2012-02-16
申请号：US13281162
申请日：2011-10-25
申请人： Chun-Fu CHEN , Yung-Tai Hung , Chin-Ta Su , Kuang-Chao Chen
发明人： Chun-Fu CHEN , Yung-Tai Hung , Chin-Ta Su , Kuang-Chao Chen
IPC分类号： H01L21/306
CPC分类号： B24B37/24 , B24D3/346
摘要： A method for chemical-mechanical polishing two adjacent structures of a semiconductor device is provided. The method for mechanical polishing comprising: (a) providing a semiconductor device comprising a recess formed in a surface thereof, a first layer formed over the surface, and a second layer filled with the recess and formed on the first layer; and (b) substantially polishing the first and second layer with a pad and a substantially inhibitor-free slurry, wherein the pad comprising a corrosion inhibitor of the second layer.
摘要翻译：提供了半导体器件的两个相邻结构的化学机械抛光方法。一种用于机械抛光的方法，包括：（a）提供半导体器件，其包括在其表面形成的凹部，形成在所述表面上的第一层，以及填充有所述凹部并形成在所述第一层上的第二层; 和（b）用垫和基本上无抑制剂的浆料基本上抛光第一层和第二层，其中该垫包括第二层的腐蚀抑制剂。

10. 发明申请

US20100244180A1 METHOD FOR FABRICATING DEVICE ISOLATION STRUCTURE 审中-公开
标题翻译：制造器件隔离结构的方法
公开(公告)号：US20100244180A1
公开(公告)日：2010-09-30
申请号：US12411189
申请日：2009-03-25
申请人： Yung-Tai Hung , Chin-Ta Su , Ta-Hung Yang
发明人： Yung-Tai Hung , Chin-Ta Su , Ta-Hung Yang
IPC分类号： H01L29/06 , H01L21/762 , H01L21/311
CPC分类号： H01L21/31111 , H01L21/02164 , H01L21/02274 , H01L21/31053 , H01L21/31116 , H01L21/31612 , H01L21/76229 , H01L21/76232
摘要： A method of a fabricating a semiconductor device includes providing a substrate having a first region and a second region. A pad layer is formed overlying the substrate in both the first region and the second region. A mask layer is then formed overlying the pad layer. Thereafter, the mask layer, the pad layer and the substrate are patterned to form a plurality of first trenches in the first region and a plurality of second trenches in the second region. A trimming process is then performed on the mask layer to remove a portion of the mask layer. An insulation layer is formed over the substrate and fills the plurality of the first trenches and the plurality of the second trenches. Ultimately, a planarization process is performed on the insulation layer.
摘要翻译：制造半导体器件的方法包括提供具有第一区域和第二区域的衬底。在第一区域和第二区域中形成覆盖衬底的衬垫层。然后形成覆盖衬垫层的掩模层。此后，对掩模层，焊盘层和衬底进行构图以在第一区域中形成多个第一沟槽和在第二区域中形成多个第二沟槽。然后在掩模层上进行修整处理以去除掩模层的一部分。绝缘层形成在衬底上并填充多个第一沟槽和多个第二沟槽。最终，在绝缘层上进行平坦化处理。

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