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1. 发明授权

US08076708B2 Structures for and method of silicide formation on memory array and peripheral logic devices 有权
标题翻译：存储器阵列和外围逻辑器件上硅化物形成的结构和方法
公开(公告)号：US08076708B2
公开(公告)日：2011-12-13
申请号：US12403602
申请日：2009-03-13
申请人： Yi-Hung Li , Jen-Chuan Pan , Jongoh Kim
发明人： Yi-Hung Li , Jen-Chuan Pan , Jongoh Kim
IPC分类号： H01L29/76
CPC分类号： H01L29/66833 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A memory device and peripheral circuitry on a substrate are described, made by a process that includes forming a charge trapping structure having a first thickness over a first area. A first gate dielectric layer having a second thickness is formed for low-voltage transistors. A second gate dielectric layer having a third thickness, greater than the second thickness, is formed for high-voltage transistors. Polysilicon is deposited and patterned to define word lines and transistor gates. The thickness of the second gate dielectric layer in regions adjacent the gates, and over a source and drain regions, is reduced to a thickness that is close to that of the second thickness.
摘要翻译：通过包括在第一区域上形成具有第一厚度的电荷捕获结构的方法来描述衬底上的存储器件和外围电路。为低压晶体管形成具有第二厚度的第一栅介质层。形成具有大于第二厚度的第三厚度的第二栅极介电层，用于高压晶体管。沉积并图案化多晶硅以限定字线和晶体管栅极。第二栅极电介质层的厚度在与栅极相邻的区域以及源极和漏极区域上的厚度减小到接近第二厚度的厚度。

2. 发明授权

US07786023B2 Metal pad formation method and metal pad structure using the same 有权
标题翻译：金属垫形成方法和金属垫结构使用相同
公开(公告)号：US07786023B2
公开(公告)日：2010-08-31
申请号：US11819011
申请日：2007-06-25
申请人： Yung-Tai Hung , Jen-Chuan Pan , Chin-Ta Su , Ta-Hung Yang
发明人： Yung-Tai Hung , Jen-Chuan Pan , Chin-Ta Su , Ta-Hung Yang
IPC分类号： H01L21/31
CPC分类号： H01L24/02 , H01L22/32 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01016 , H01L2924/01018 , H01L2924/01033 , H01L2924/01074 , H01L2924/01327
摘要： A metal pad formation method and metal pad structure using the same are provided. A wider first pad metal is formed together with a first metal. A dielectric layer is then deposited thereon. A first opening and a second opening are formed in the dielectric layer to respectively expose the first metal and the first pad metal. Then, the first opening is filled by W metal to generate a first via. Finally, a second metal and a second pad metal are formed to respectively cover the first via and the first pad metal to generate the metal pad.
摘要翻译：提供了一种使用其的金属焊盘形成方法和金属焊盘结构。与第一金属一起形成较宽的第一焊盘金属。然后在其上沉积介电层。在电介质层中形成第一开口和第二开口以分别暴露第一金属和第一焊盘金属。然后，第一开口由W金属填充以产生第一通孔。最后，形成第二金属和第二焊盘金属，以分别覆盖第一通孔和第一焊盘金属以产生金属焊盘。

3. 发明授权

US07517737B2 Structures for and method of silicide formation on memory array and peripheral logic devices 有权
标题翻译：存储器阵列和外围逻辑器件上硅化物形成的结构和方法
公开(公告)号：US07517737B2
公开(公告)日：2009-04-14
申请号：US11672150
申请日：2007-02-07
申请人： Yi Hung Li , Jen Chuan Pan , Jongoh Kim
发明人： Yi Hung Li , Jen Chuan Pan , Jongoh Kim
IPC分类号： H01L21/335
CPC分类号： H01L29/66833 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A memory device and peripheral circuitry on a substrate are described, made by a process that includes forming a charge trapping structure having a first thickness over a first area. A first gate dielectric layer having a second thickness is formed for low-voltage transistors. A second gate dielectric layer having a third thickness, greater than the second thickness, is formed for high-voltage transistors. Polysilicon is deposited and patterned to define word lines and transistor gates. The thickness of the second gate dielectric layer in regions adjacent the gates, and over a source and drain regions, is reduced to a thickness that is close to that of the second thickness. Dopants are implanted for formation of source and drain regions in the second and third areas. A silicon nitride spacer material is deposited over the word lines and gates, and etched to form sidewall spacers on the gates. Dopants are implanted aligned with the sidewall spacers in the second and third areas. The gate dielectric layers are selectively etched to expose the substrate adjacent the sidewall spacers, and to expose word lines and gates without exposing the substrate in the bit line contract regions. A self-aligned silicide formation is then applied. A portion of the charge trapping structure in the bit line contact regions acts as a mask to prevent silicide formation. An interlayer dielectric and bit line contacts are formed in the bit line contact regions. Patterned conductor layers are formed over the interlayer dielectric.
摘要翻译：通过包括在第一区域上形成具有第一厚度的电荷捕获结构的方法来描述衬底上的存储器件和外围电路。为低压晶体管形成具有第二厚度的第一栅介质层。形成具有大于第二厚度的第三厚度的第二栅极介电层，用于高压晶体管。沉积并图案化多晶硅以限定字线和晶体管栅极。第二栅极电介质层的厚度在与栅极相邻的区域以及源极和漏极区域上的厚度减小到接近第二厚度的厚度。植入掺杂剂以在第二和第三区域中形成源区和漏区。氮化硅间隔物材料沉积在字线和栅极上，并被蚀刻以在栅极上形成侧壁间隔物。在第二和第三区域中注入与侧壁间隔物对准的掺杂剂。选择性地蚀刻栅极电介质层以暴露邻近侧壁间隔物的衬底，并暴露字线和栅极，而不会在位线收缩区域中暴露衬底。然后施加自对准的硅化物形成。位线接触区域中的电荷俘获结构的一部分用作掩模以防止形成硅化物。在位线接触区域中形成层间电介质和位线接触。图案化的导体层形成在层间电介质上。

4. 发明申请

US20080315420A1 Metal pad formation method and metal pad structure using the same 有权
标题翻译：金属垫形成方法和金属垫结构使用相同
公开(公告)号：US20080315420A1
公开(公告)日：2008-12-25
申请号：US11819011
申请日：2007-06-25
申请人： Yung-Tai Hung , Jen-Chuan Pan , Chin-Ta Su , Ta-Hung Yang
发明人： Yung-Tai Hung , Jen-Chuan Pan , Chin-Ta Su , Ta-Hung Yang
IPC分类号： H01L23/485 , H01L21/441
CPC分类号： H01L24/02 , H01L22/32 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01016 , H01L2924/01018 , H01L2924/01033 , H01L2924/01074 , H01L2924/01327
摘要： A metal pad formation method and metal pad structure using the same are provided. A wider first pad metal is formed together with a first metal. A dielectric layer is then deposited thereon. A first opening and a second opening are formed in the dielectric layer to respectively expose the first metal and the first pad metal. Then, the first opening is filled by W metal to generate a first via. Finally, a second metal and a second pad metal are formed to respectively cover the first via and the first pad metal to generate the metal pad.
摘要翻译：提供了一种使用其的金属焊盘形成方法和金属焊盘结构。与第一金属一起形成较宽的第一焊盘金属。然后在其上沉积介电层。在电介质层中形成第一开口和第二开口以分别暴露第一金属和第一焊盘金属。然后，第一开口由W金属填充以产生第一通孔。最后，形成第二金属和第二焊盘金属，以分别覆盖第一通孔和第一焊盘金属以产生金属焊盘。

5. 发明授权

US06699761B2 Method for fabricating y-direction, self-alignment mask ROM device 有权
标题翻译：用于制造y方向，自对准掩模ROM器件的方法
公开(公告)号：US06699761B2
公开(公告)日：2004-03-02
申请号：US10064396
申请日：2002-07-10
申请人： Jen-Chuan Pan
发明人： Jen-Chuan Pan
IPC分类号： H01L21336
CPC分类号： H01L27/11266 , H01L21/823892 , H01L27/105 , H01L27/11293
摘要： A method for fabricating a y-direction, self-alignment mask ROM device is described. The method includes forming a buried drain region in a substrate and forming a gate oxide layer on the substrate. Perpendicular to the direction of the buried drain region, a bar-shaped silicon nitride layer is formed on the gate oxide layer. A photoresist layer is then formed on the gate oxide layer and the bar-shaped silicon nitride layer. Performing a code implantation to form a plurality of coded memory cells using the photoresist layer as a mask. The photoresist layer is then removed. A polysilicon layer is further formed on the gate oxide layer and the bar-shaped silicon nitride layer. The polysilicon layer is back-etched until the bar-shaped silicon nitride layer is exposed. The silicon nitride layer is subsequently removed.
摘要翻译：描述了用于制造y方向自对准掩模ROM器件的方法。该方法包括在衬底中形成埋漏区，并在衬底上形成栅极氧化层。垂直于掩埋漏极区域的方向，在栅极氧化物层上形成棒状氮化硅层。然后在栅极氧化物层和棒状氮化硅层上形成光致抗蚀剂层。使用光致抗蚀剂层作为掩模来执行代码注入以形成多个编码存储单元。然后除去光致抗蚀剂层。在栅极氧化物层和棒状氮化硅层上还形成多晶硅层。多晶硅层被反蚀刻直到棒状氮化硅层露出。随后去除氮化硅层。

6. 发明授权

US06559013B1 Method for fabricating mask ROM device 有权
标题翻译：掩模ROM器件的制造方法
公开(公告)号：US06559013B1
公开(公告)日：2003-05-06
申请号：US10064397
申请日：2002-07-10
申请人： Jen-Chuan Pan
发明人： Jen-Chuan Pan
IPC分类号： H01L218234
CPC分类号： H01L27/1126 , H01L27/112
摘要： A method for fabricating a mask ROM device is described. The method includes forming a buried drain region in a substrate and forming a thick oxide layer on the substrate. Perpendicular to the direction of the buried drain region, a bar-shaped silicon nitride layer is formed on the thick oxide layer. A portion of the thick oxide layer is then removed to expose the substrate, followed by forming a gate oxide layer on the exposed substrate surface for forming a plurality of coded memory cells, wherein the coded memory cells with a gate oxide layer corresponds to a logic state “1” while the code memory cells with a thick silicon oxide layer corresponds to a logic state “0”. A polysilicon layer is then formed on the substrate, followed by back-etching the polysilicon layer to expose the bar-shaped silicon nitride layer. After this, the bar-shaped silicon nitride layer is removed.
摘要翻译：描述了一种制造掩模ROM器件的方法。该方法包括在衬底中形成掩埋漏极区域，并在衬底上形成厚的氧化物层。垂直于埋漏区的方向，在厚氧化物层上形成棒状氮化硅层。然后去除厚氧化物层的一部分以暴露衬底，随后在暴露的衬底表面上形成栅极氧化物层，以形成多个编码存储器单元，其中具有栅极氧化物层的编码存储器单元对应于逻辑状态“1”，而具有厚氧化硅层的代码存储单元对应于逻辑状态“0”。然后在衬底上形成多晶硅层，然后反向蚀刻多晶硅层以暴露棒状氮化硅层。之后，去除棒状氮化硅层。

7. 发明授权

US07442610B2 Low thermal budget fabrication method for a mask read only memory device 有权
标题翻译：用于掩模只读存储器件的低热预算制造方法
公开(公告)号：US07442610B2
公开(公告)日：2008-10-28
申请号：US10156323
申请日：2002-05-24
申请人： Shui-Chin Huang , Jen-Chuan Pan
发明人： Shui-Chin Huang , Jen-Chuan Pan
IPC分类号： H01L21/8234
CPC分类号： H01L27/1126 , H01L27/112
摘要： A low thermal budget fabrication method for a mask ROM is described. The method includes providing a substrate having a gate oxide layer thereon. A first conductive layer is formed on the gate oxide layer. A plurality of bit lines is formed in the substrate. A second conductive layer is then formed on the first conductive layer, followed by forming a plurality of ROM codes in the substrate.
摘要翻译：描述了用于掩模ROM的低热预算制造方法。该方法包括提供其上具有栅氧化层的衬底。在栅极氧化物层上形成第一导电层。在基板中形成多个位线。然后在第一导电层上形成第二导电层，随后在衬底中形成多个ROM代码。

8. 发明申请

US20090173990A1 STRUCTURES FOR AND METHOD OF SILICIDE FORMATION ON MEMORY ARRAY AND PERIPHERAL LOGIC DEVICES 有权
标题翻译：存储器阵列和外围逻辑器件中硅化物形成的结构和方法
公开(公告)号：US20090173990A1
公开(公告)日：2009-07-09
申请号：US12403602
申请日：2009-03-13
申请人： Yi-Hung Li , Jen-Chuan Pan , Jongoh Kim
发明人： Yi-Hung Li , Jen-Chuan Pan , Jongoh Kim
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A memory device and peripheral circuitry on a substrate are described, made by a process that includes forming a charge trapping structure having a first thickness over a first area. A first gate dielectric layer having a second thickness is formed for low-voltage transistors. A second gate dielectric layer having a third thickness, greater than the second thickness, is formed for high-voltage transistors. Polysilicon is deposited and patterned to define word lines and transistor gates. The thickness of the second gate dielectric layer in regions adjacent the gates, and over a source and drain regions, is reduced to a thickness that is close to that of the second thickness.
摘要翻译：通过包括在第一区域上形成具有第一厚度的电荷捕获结构的方法来描述衬底上的存储器件和外围电路。为低压晶体管形成具有第二厚度的第一栅介质层。形成具有大于第二厚度的第三厚度的第二栅极介电层，用于高压晶体管。沉积并图案化多晶硅以限定字线和晶体管栅极。第二栅极电介质层的厚度在与栅极相邻的区域以及源极和漏极区域上的厚度减小到接近第二厚度的厚度。

9. 发明申请

US20080185634A1 STRUCTURES FOR AND METHOD OF SILICIDE FORMATION ON MEMORY ARRAY AND PERIPHERAL LOGIC DEVICES 有权
标题翻译：存储器阵列和外围逻辑器件中硅化物形成的结构和方法
公开(公告)号：US20080185634A1
公开(公告)日：2008-08-07
申请号：US11672150
申请日：2007-02-07
申请人： YI HUNG LI , JEN CHUAN PAN , JONGOH KIM
发明人： YI HUNG LI , JEN CHUAN PAN , JONGOH KIM
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/66833 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A memory device and peripheral circuitry on a substrate are described, made by a process that includes forming a charge trapping structure having a first thickness over a first area. A first gate dielectric layer having a second thickness is formed for low-voltage transistors. A second gate dielectric layer having a third thickness, greater than the second thickness, is formed for high-voltage transistors. Polysilicon is deposited and patterned to define word lines and transistor gates. The thickness of the second gate dielectric layer in regions adjacent the gates, and over a source and drain regions, is reduced to a thickness that is close to that of the second thickness. Dopants are implanted for formation of source and drain regions in the second and third areas. A silicon nitride spacer material is deposited over the word lines and gates, and etched to form sidewall spacers on the gates. Dopants are implanted aligned with the sidewall spacers in the second and third areas. The gate dielectric layers are selectively etched to expose the substrate adjacent the sidewall spacers, and to expose word lines and gates without exposing the substrate in the bit line contract regions. A self-aligned silicide formation is then applied. A portion of the charge trapping structure in the bit line contact regions acts as a mask to prevent silicide formation. An interlayer dielectric and bit line contacts are formed in the bit line contact regions. Patterned conductor layers are formed over the interlayer dielectric.
摘要翻译：通过包括在第一区域上形成具有第一厚度的电荷捕获结构的方法来描述衬底上的存储器件和外围电路。为低压晶体管形成具有第二厚度的第一栅介质层。形成具有大于第二厚度的第三厚度的第二栅极介电层，用于高压晶体管。沉积并图案化多晶硅以限定字线和晶体管栅极。第二栅极电介质层的厚度在与栅极相邻的区域以及源极和漏极区域上的厚度减小到接近第二厚度的厚度。植入掺杂剂以在第二和第三区域中形成源区和漏区。氮化硅间隔物材料沉积在字线和栅极上，并被蚀刻以在栅极上形成侧壁间隔物。在第二和第三区域中注入与侧壁间隔物对准的掺杂剂。选择性地蚀刻栅极电介质层以暴露邻近侧壁间隔物的衬底，并暴露字线和栅极，而不会在位线收缩区域中暴露衬底。然后施加自对准的硅化物形成。位线接触区域中的电荷俘获结构的一部分用作掩模以防止形成硅化物。在位线接触区域中形成层间电介质和位线接触。图案化的导体层形成在层间电介质上。

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