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1. 发明申请

US20050156252A1 Method for forming a polycide gate and structure of the same 审中-公开
标题翻译：形成多晶硅栅极的方法及其结构
公开(公告)号：US20050156252A1
公开(公告)日：2005-07-21
申请号：US11011598
申请日：2004-12-15
申请人： Yung-Chang Lin , Le-Tien Jung , Wen-Jeng Lin
发明人： Yung-Chang Lin , Le-Tien Jung , Wen-Jeng Lin
IPC分类号： H01L21/28 , H01L21/3115 , H01L29/49 , H01L29/76 , H01L21/336
CPC分类号： H01L21/31155 , H01L21/28061 , H01L29/4916
摘要： The method of forming a polycide gate includes forming a pad oxide layer on a substrate. A first conductive layer is formed on the pad oxide layer. Subsequently, a first ion implantation into the first conductive layer is next performed to form deep implantation region of polysilicon. Successively, a second ion implantation into the first conductive layer is performed to form shallow implantation region of polysilicon, wherein the second ion type is the same as the first ion type. A second conductive layer formed on the first conductive layer. A further patterned photoresist layer is formed on the second conductive layer. Next, a dry etching process one time by way of using the patterned photoresist layer as an etching mask is performed to etch through in turn the second conductive layer, the first conductive layer and the pad oxide layer until forming a gate with double polysilicon implantation, thereby forming a polycide gate. Finally, the photoresist layer is then removed.
摘要翻译：形成多晶硅栅极的方法包括在衬底上形成衬垫氧化物层。在衬垫氧化物层上形成第一导电层。随后，进行第一离子注入到第一导电层中以形成多晶硅的深注入区。接着，进行到第一导电层的第二离子注入以形成多晶硅的浅注入区，其中第二离子类型与第一离子类型相同。形成在第一导电层上的第二导电层。在第二导电层上形成另外的图案化光致抗蚀剂层。接下来，进行通过使用图案化光致抗蚀剂层作为蚀刻掩模一次的干蚀刻处理，以依次蚀刻第二导电层，第一导电层和衬垫氧化物层，直到形成具有双多晶硅注入的栅极，从而形成多晶硅栅极。最后，去除光致抗蚀剂层。

2. 发明授权

US06221767B1 Method of fabricating a silicide landing pad 有权
标题翻译：制造硅化物着陆垫的方法
公开(公告)号：US06221767B1
公开(公告)日：2001-04-24
申请号：US09428735
申请日：1999-10-28
申请人： Kirk Hsu , Yung-Chang Lin , Wen-Jeng Lin
发明人： Kirk Hsu , Yung-Chang Lin , Wen-Jeng Lin
IPC分类号： H01L2144
CPC分类号： H01L21/28518
摘要： A method for fabricating a landing pad is described in which a transistor is formed on the substrate, wherein the transistor comprises a gate and source/drain regions at both sides of the gate in the substrate. A cap layer and a spacer are formed on the gate and at the sidewall of the gate respectively. A protective layer is formed to cover the substrate. The protective layer is then defined to form an opening to expose the source/drain region. A polysilicon landing pad is then formed in the opening and on the protective layer at the periphery of the opening. Silicidation is then conducted on the polysilicon landing pad to form a metal silicide landing pad and to destroy any native oxide at the source/drain region.
摘要翻译：描述了一种用于制造着陆焊盘的方法，其中在衬底上形成晶体管，其中晶体管包括在衬底中的栅极两侧的栅极和源极/漏极区域。在栅极和门的侧壁分别形成覆盖层和间隔物。形成保护层以覆盖基板。然后限定保护层以形成开口以暴露源极/漏极区域。然后在开口处和开口周边处的保护层上形成多晶硅着陆垫。然后在多晶硅着陆焊盘上进行硅化，以形成金属硅化物着陆焊盘并破坏源极/漏极区域处的任何自然氧化物。

3. 发明授权

US06238958B1 Method for forming a transistor with reduced source/drain series resistance 失效
标题翻译：用于形成具有降低的源极/漏极串联电阻的晶体管的方法
公开(公告)号：US06238958B1
公开(公告)日：2001-05-29
申请号：US09477109
申请日：1999-12-31
申请人： Kirk Hsu , Yung-Chang Lin , Wen-Jeng Lin
发明人： Kirk Hsu , Yung-Chang Lin , Wen-Jeng Lin
IPC分类号： H01L2184
CPC分类号： H01L29/665 , H01L29/41775 , H01L29/41783
摘要： A method for forming a transistor in integrated circuits is disclosed. The method includes the following steps. A substrate is first provided. An insulating layer is then formed on the substrate. A conductor layer is formed on the insulating layer. Subsequently, a patterned photoresist layer is formed on the conductor layer. Next, an etch process is used to etch the conductor layer which has a sidewall. The patterned photoresist layer is then removed. After forming a liner layer on the sidewall of the conductor layer, a lightly doped drain is formed on and in the substrate. Then, a spacer is formed on the liner layer. Thereafter, a proper process is used to introduce ions into the lightly doped drain, and then a source/drain region is completed. The steps with follow include annealing the source/drain region and removing the spacer. Subsequently, an epi-silicon layer is formed on the lightly doped drain region, the source/drain region and the top surface of the conductor layer. Finally, the epi-silicon layer is treated with a salicidation process to form a salicide layer.
摘要翻译：公开了一种在集成电路中形成晶体管的方法。该方法包括以下步骤。首先提供基板。然后在衬底上形成绝缘层。在绝缘层上形成导体层。随后，在导体层上形成图案化的光致抗蚀剂层。接下来，使用蚀刻工艺来蚀刻具有侧壁的导体层。然后去除图案化的光致抗蚀剂层。在导体层的侧壁上形成衬垫层之后，在衬底上和衬底中形成轻掺杂漏极。然后，在衬垫层上形成间隔物。此后，使用适当的方法将离子引入轻掺杂的漏极中，然后完成源极/漏极区域。随后的步骤包括对源极/漏极区进行退火并去除间隔物。随后，在轻掺杂漏区，导体层的源/漏区和顶表面上形成外延硅层。最后，用硅化物处理外延硅层以形成自对准硅层。

4. 发明申请

US20070298567A1 SRAM CELL STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译： SRAM单元结构及其制造方法
公开(公告)号：US20070298567A1
公开(公告)日：2007-12-27
申请号：US11852185
申请日：2007-09-07
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rem-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rem-Hurng Larn
IPC分类号： H01L21/8244
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.
摘要翻译：至少包括衬底，晶体管，上电极和电容器电介质层的静态随机存取存储器（SRAM）单元结构。在衬底中设置器件隔离结构以限定有源区。活动区域有一个开口。晶体管设置在衬底的有源区上。晶体管的源极区域靠近开口。将上电极设置在开口上方，使得开口完全充满。电容器介电层设置在上电极和衬底之间。

5. 发明授权

US07157763B2 SRAM cell structure and manufacturing method thereof 有权
公开(公告)号：US07157763B2
公开(公告)日：2007-01-02
申请号：US10983140
申请日：2004-11-04
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
IPC分类号： H01L27/108
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

6. 发明申请

US20060192241A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20060192241A1
公开(公告)日：2006-08-31
申请号：US11066994
申请日：2005-02-25
申请人： Tzung-Han Lee , Wen-Jeng Lin , Kuang-Pi Lee , Blue Larn
发明人： Tzung-Han Lee , Wen-Jeng Lin , Kuang-Pi Lee , Blue Larn
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L29/6653
摘要： A non-volatile memory comprising a substrate, a stacked gate structure, a conductive spacer, an oxide/nitride/oxide layer, buried doping regions, a control gate and an insulating layer. The stacked gate structure is disposed on the substrate. The stacked gate structure comprises a gate dielectric layer, a select gate and a cap layer. The conductive spacer is disposed on the sidewalls of the stacked gate structure. The oxide/nitride/oxide layer is disposed between the conductive spacer and the stacked gate structure and between the conductive spacer and the substrate. The buried doping regions are disposed in the substrate outside the conductive spacer on each side of the stacked gate structure. The control gate is disposed over the stacked gate structure and electrically connected to the conductive spacer. The insulating layer is disposed between the buried doping layer and the control gate.
摘要翻译：包括衬底，堆叠栅极结构，导电间隔物，氧化物/氮化物/氧化物层，掩埋掺杂区域，控制栅极和绝缘层的非易失性存储器。层叠的栅极结构设置在基板上。堆叠栅极结构包括栅极介电层，选择栅极和盖层。导电间隔物设置在堆叠栅结构的侧壁上。氧化物/氮化物/氧化物层设置在导电间隔物和层叠栅极结构之间以及导电间隔物和衬底之间。掩埋掺杂区域设置在层叠栅极结构的每一侧上的导电间隔物外部的衬底中。控制栅极设置在堆叠的栅极结构上并电连接到导电间隔物。绝缘层设置在掩埋掺杂层和控制栅极之间。

7. 发明授权

US06177297B1 Method of forming metallic fuse demanding lower laser power for circuit repair 有权
标题翻译：形成金属保险丝的方法，要求较低的激光功率进行电路修复
公开(公告)号：US06177297B1
公开(公告)日：2001-01-23
申请号：US09227953
申请日：1999-01-11
申请人： Jacob Chen , Wen-Jeng Lin
发明人： Jacob Chen , Wen-Jeng Lin
IPC分类号： H01L2182
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： An improved formation method produces a metallic fuse capable of lowering the laser power needed for carrying out circuit repair. The method includes forming a metallic fuse when the penultimate metallic layer is formed. Since the metallic fuse is not too far away from the top surface, the power of the laser beam necessary for repairing the circuit can be moderate. Furthermore, the laser beam is more focused because it travels a shorter distance to reach the fuse, thereby avoiding unnecessary dispersion through intermediate material. Moreover, since the metallic fuse itself is not too thick, only a low-power laser beam is needed to melt the metallic fuse.
摘要翻译：改进的形成方法产生能够降低执行电路修复所需的激光功率的金属保险丝。该方法包括在倒数第二个金属层形成时形成金属熔丝。由于金属保险丝距离顶表面不是太远，修理电路所需的激光束的功率可以适中。此外，激光束由于其行进较短的距离而到达保险丝而被聚焦，从而避免了通过中间材料的不必要的分散。此外，由于金属熔断器本身不太厚，所以仅需要低功率激光束来熔化金属熔断器。

8. 发明申请

US20060202248A1 SRAM cell structure and manufacturing method thereof 有权
公开(公告)号：US20060202248A1
公开(公告)日：2006-09-14
申请号：US11416926
申请日：2006-05-02
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
IPC分类号： H01L29/94
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

9. 发明申请

US20050098905A1 SRAM cell structure and manufacturing method thereof 有权
标题翻译： SRAM单元结构及其制造方法
公开(公告)号：US20050098905A1
公开(公告)日：2005-05-12
申请号：US10983140
申请日：2004-11-04
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
IPC分类号： H01L21/336 , H01L21/8242 , H01L21/8244 , H01L27/11
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.
摘要翻译：至少包括衬底，晶体管，上电极和电容器电介质层的静态随机存取存储器（SRAM）单元结构。在衬底中设置器件隔离结构以限定有源区。活动区域有一个开口。晶体管设置在衬底的有源区上。晶体管的源极区域靠近开口。将上电极设置在开口上方，使得开口完全充满。电容器介电层设置在上电极和衬底之间。

10. 发明授权

US06218239B1 Manufacturing method of a bottom plate 失效
标题翻译：底板的制造方法
公开(公告)号：US06218239B1
公开(公告)日：2001-04-17
申请号：US09195168
申请日：1998-11-17
申请人： Keh-Ching Huang , Wen-Jeng Lin , Tz-Guei Jung , Jacob Chen
发明人： Keh-Ching Huang , Wen-Jeng Lin , Tz-Guei Jung , Jacob Chen
IPC分类号： H01L218242
CPC分类号： H01L28/87 , H01L27/10855 , H01L28/91
摘要： The invention provides a manufacturing method of forming a bottom plate for a capacitor on a substrate, wherein the substrate comprises a MOS transistor having a gate and a pair of source/drain regions. A crown-liked conductive plate is formed over an insulation oxide layer and a contact plug. The crown-liked conductive plate penetrates the insulation layer and the stop layer, wherein the bottom of the crown-like conductive plate is electrically connected to the contact plug. The crown-like conductive plate, served as the bottom plate for a DRAM capacitor, is composed of tungsten silicide or a combination of a tungsten nitride layer and a tungsten layer.
摘要翻译：本发明提供一种在基板上形成用于电容器的底板的制造方法，其中所述基板包括具有栅极和一对源极/漏极区域的MOS晶体管。冠状导电板形成在绝缘氧化物层和接触插塞上。冠状导电板穿透绝缘层和阻挡层，其中冠状导电板的底部电连接到接触插塞。用作DRAM电容器的底板的冠状导电板由硅化钨或氮化钨层和钨层的组合构成。

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