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1. 发明授权

US08659321B2 Semiconductor device having sense amplifier 有权
标题翻译：具有读出放大器的半导体器件
公开(公告)号：US08659321B2
公开(公告)日：2014-02-25
申请号：US13306560
申请日：2011-11-29
申请人： Yuko Watanabe , Yoshiro Riho , Hiromasa Noda , Yoji Idei , Kosuke Goto
发明人： Yuko Watanabe , Yoshiro Riho , Hiromasa Noda , Yoji Idei , Kosuke Goto
IPC分类号： G01R19/00 , G11C7/00 , H03F3/45
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/08 , G11C7/222 , G11C11/4074 , G11C11/4076
摘要： A semiconductor device includes a first driver circuit for supplying a first potential to a first power supply node of the sense amplifier, second and third driver circuits for supplying a second potential and a third potential to a second power supply node of the sense amplifier, and a timing control circuit for controlling operations of the first to third driver circuits. The timing control circuit includes a delay circuit for deciding an ON period of the third driver circuit. The delay circuit includes a first delay circuit having a delay amount that depends on an external power supply potential and a second delay circuit having a delay amount that does not depend on the external power supply potential, and the ON period of the third driver circuit is decided based on a sum of the delay amounts of the first and second delay circuits.
摘要翻译：半导体器件包括用于向读出放大器的第一电源节点提供第一电位的第一驱动器电路，用于向读出放大器的第二电源节点提供第二电位和第三电位的第二和第三驱动器电路，以及用于控制第一至第三驱动器电路的操作的定时控制电路。定时控制电路包括用于决定第三驱动电路的接通时间的延迟电路。延迟电路包括具有取决于外部电源电位的延迟量的第一延迟电路和具有不依赖于外部电源电位的延迟量的第二延迟电路，并且第三驱动电路的导通周期为基于第一和第二延迟电路的延迟量的总和来决定。

2. 发明申请

US20140140155A1 SEMICONDUCTOR DEVICE AND METHOD INCLUDING REDUNDANT BIT LINE PROVIDED TO REPLACE DEFECTIVE BIT LINE 有权
标题翻译：半导体器件和方法，包括提供更换缺陷位线的冗余位线
公开(公告)号：US20140140155A1
公开(公告)日：2014-05-22
申请号：US14163368
申请日：2014-01-24
申请人： Yoshiro Riho , Yoshio Mizukane , Hiromasa Noda
发明人： Yoshiro Riho , Yoshio Mizukane , Hiromasa Noda
IPC分类号： G11C29/00
CPC分类号： G11C29/785 , G11C11/406 , G11C29/783 , G11C29/808 , G11C29/83
摘要： A method includes selecting a word line included in one of a plurality of memory mats based on a row address, where each of the plurality of memory mats includes a plurality of word lines, a plurality of bit lines, and a redundant bit line, selecting one of the bit lines included in the selected memory mat based on a column address, selecting, by a column relief circuit, the redundant bit line in place of the one of the bit lines to be selected based on the column address, in response to the column address indicating a defective address, activating the column relief circuit when the row address is supplied in response to a first command, and inactivating the column relief circuit when the row address is supplied in response to a second command.
摘要翻译：一种方法包括：基于行地址选择包括在多个存储器阵列之一中的字线，其中多个存储器阵列中的每一个包括多个字线，多个位线和冗余位线，选择基于列地址包括在所选择的存储器存储器中的位线之一，响应于列地址，由列浮动电路选择冗余位线来代替要选择的位线中的一个位置所述列地址指示缺陷地址，当响应于第一命令提供所述行地址时激活所述列浮动电路，以及当响应于第二命令提供所述行地址时，使所述列浮动电路失活。

3. 发明申请

US20120213021A1 SEMICONDUCTOR DEVICE HAVING REDUNDANT BIT LINE PROVIDED TO REPLACE DEFECTIVE BIT LINE 失效
标题翻译：具有冗余位线的半导体器件提供更换有缺陷的位线
公开(公告)号：US20120213021A1
公开(公告)日：2012-08-23
申请号：US13396985
申请日：2012-02-15
申请人： Yoshiro Riho , Yoshio Mizukane , Hiromasa Noda
发明人： Yoshiro Riho , Yoshio Mizukane , Hiromasa Noda
IPC分类号： G11C29/04
CPC分类号： G11C29/785 , G11C11/406 , G11C29/783 , G11C29/808 , G11C29/83
摘要： Disclosed herein is a device that responds to mat selection information, which is used to select one of memory mats, and selects at least one defective address from a plurality of defective addresses which are stored, for example, in a fuse circuit. When the access address information is coincident with a selected defective address, a redundant memory cell is accessed for reading or writing data in place of a normal memory cell. In a refresh operation, on the other hand, a column addressing, including the above replacement of a normal memory cell with a redundant memory cell, is deactivated.
摘要翻译：本文公开了一种响应于垫选择信息的装置，其用于选择存储器垫之一，并且从例如存储在熔丝电路中的多个缺陷地址中选择至少一个缺陷地址。当访问地址信息与选择的缺陷地址一致时，访问冗余存储单元来代替正常存储单元读取或写入数据。另一方面，在刷新操作中，包括上述用冗余存储单元替换正常存储单元的列寻址被去激活。

4. 发明授权

US07940583B2 Semiconductor memory device, control method therefor, and method for determining repair possibility of defective address 有权
标题翻译：半导体存储器件及其控制方法以及用于确定缺陷地址修复可能性的方法
公开(公告)号：US07940583B2
公开(公告)日：2011-05-10
申请号：US12320892
申请日：2009-02-06
申请人： Yoshiro Riho , Jun Suzuki , Yasuhiro Matsumoto , Shuichi Kubouchi , Hiromasa Noda , Yasuji Koshikawa
发明人： Yoshiro Riho , Jun Suzuki , Yasuhiro Matsumoto , Shuichi Kubouchi , Hiromasa Noda , Yasuji Koshikawa
IPC分类号： G11C29/00
CPC分类号： G11C8/08 , G11C8/10 , G11C29/84
摘要： There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit.
摘要翻译：提供有多个存储器垫，子字驱动器，其访问正常存储器单元，而不管请求访问的行地址是否是缺陷地址;子字驱动器，访问属于当行地址是缺陷地址时，由行地址指示的正常存储单元不同的存储器垫。根据本发明，正常存储单元和冗余存储单元属于彼此不同的存储器单元，从而可以在确定修复确定电路的操作的同时访问正常存储单元。

5. 发明授权

US08638625B2 Semiconductor device having redundant bit line provided to replace defective bit line 失效
标题翻译：具有提供冗余位线以替代有缺陷位线的半导体器件
公开(公告)号：US08638625B2
公开(公告)日：2014-01-28
申请号：US13396985
申请日：2012-02-15
申请人： Yoshiro Riho , Yoshio Mizukane , Hiromasa Noda
发明人： Yoshiro Riho , Yoshio Mizukane , Hiromasa Noda
IPC分类号： G11C7/00
CPC分类号： G11C29/785 , G11C11/406 , G11C29/783 , G11C29/808 , G11C29/83
摘要： Disclosed herein is a device that responds to mat selection information, which is used to select one of memory mats, and selects at least one defective address from a plurality of defective addresses which are stored, for example, in a fuse circuit. When the access address information is coincident with a selected defective address, a redundant memory cell is accessed for reading or writing data in place of a normal memory cell. In a refresh operation, on the other hand, a column addressing, including the above replacement of a normal memory cell with a redundant memory cell, is deactivated.
摘要翻译：本文公开了一种响应于垫选择信息的装置，其用于选择存储器垫之一，并且从例如存储在熔丝电路中的多个缺陷地址中选择至少一个缺陷地址。当访问地址信息与选择的缺陷地址一致时，访问冗余存储单元来代替正常存储单元读取或写入数据。另一方面，在刷新操作中，包括上述用冗余存储单元替换正常存储单元的列寻址被去激活。

6. 发明授权

US08837242B2 Semiconductor device and method including redundant bit line provided to replace defective bit line 有权
标题翻译：半导体装置和方法包括提供冗余位线来替代有缺陷的位线
公开(公告)号：US08837242B2
公开(公告)日：2014-09-16
申请号：US14163368
申请日：2014-01-24
申请人： Yoshiro Riho , Yoshio Mizukane , Hiromasa Noda
发明人： Yoshiro Riho , Yoshio Mizukane , Hiromasa Noda
IPC分类号： G11C7/00
CPC分类号： G11C29/785 , G11C11/406 , G11C29/783 , G11C29/808 , G11C29/83
摘要： A method includes selecting a word line included in one of a plurality of memory mats based on a row address, where each of the plurality of memory mats includes a plurality of word lines, a plurality of bit lines, and a redundant bit line, selecting one of the bit lines included in the selected memory mat based on a column address, selecting, by a column relief circuit, the redundant bit line in place of the one of the bit lines to be selected based on the column address, in response to the column address indicating a defective address, activating the column relief circuit when the row address is supplied in response to a first command, and inactivating the column relief circuit when the row address is supplied in response to a second command.
摘要翻译：一种方法包括：基于行地址选择包括在多个存储器阵列之一中的字线，其中多个存储器阵列中的每一个包括多个字线，多个位线和冗余位线，选择基于列地址包括在所选择的存储器存储器中的位线之一，响应于列地址，由列浮动电路选择冗余位线来代替要选择的位线中的一个位置所述列地址指示缺陷地址，当响应于第一命令提供所述行地址时激活所述列浮动电路，以及当响应于第二命令提供所述行地址时，使所述列浮动电路失活。

7. 发明申请

US20140211582A1 Semiconductor Device Performing Stress Test 有权
标题翻译：半导体器件进行应力测试
公开(公告)号：US20140211582A1
公开(公告)日：2014-07-31
申请号：US14243183
申请日：2014-04-02
申请人： Yoshiro Riho , Hiromasa Noda , Kazuki Sakuma
发明人： Yoshiro Riho , Hiromasa Noda , Kazuki Sakuma
IPC分类号： G11C29/00
CPC分类号： G11C29/00 , G11C29/02 , G11C29/06 , G11C29/12005 , G11C29/28 , G11C29/50 , G11C2029/1202 , G11C2029/2602
摘要： A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays, and each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at a time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent to each other in the plurality of memory cell mats. According to the present invention, the memory cell mats with the plurality of activated word lines are distributed. Therefore, as compared with many word lines activated in one memory cell mat, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced. As a result, more word lines can be activated at the same time.
摘要翻译：半导体器件包括存储单元阵列，其通过多个读出放大器阵列被分成多个存储单元阵列，并且多个存储单元阵列中的每一个包括多个字线和用于执行测试控制的测试电路一次激活在多个存储单元垫中彼此不邻近设置的多个所选存储单元垫中的每一个中包括的多个字线。根据本发明，分配具有多个激活字线的存储单元垫。因此，与在一个存储单元垫中激活的许多字线相比，施加到用于驱动字线的驱动电路的负载和施加到用于向驱动器电路提供工作电压的电源电路的负载减小。因此，可以同时激活更多的字线。

8. 发明授权

US08737149B2 Semiconductor device performing stress test 有权
标题翻译：半导体器件进行压力测试
公开(公告)号：US08737149B2
公开(公告)日：2014-05-27
申请号：US13302772
申请日：2011-11-22
申请人： Yoshiro Riho , Hiromasa Noda , Kazuki Sakuma
发明人： Yoshiro Riho , Hiromasa Noda , Kazuki Sakuma
IPC分类号： G11C7/00 , G11C29/50 , G11C29/02 , G11C29/06 , G11C29/12 , G11C29/28
CPC分类号： G11C29/00 , G11C29/02 , G11C29/06 , G11C29/12005 , G11C29/28 , G11C29/50 , G11C2029/1202 , G11C2029/2602
摘要： A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays. Each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at one time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent each other in the plurality of memory cell mats. The memory cell mats with the plurality of activated word lines are distributed. Therefore, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced.
摘要翻译：半导体器件包括由多个读出放大器阵列分成多个存储单元阵列的存储单元阵列。多个存储单元垫中的每一个包括多个字线和用于执行测试控制的测试电路，以一次激活多个选定的未设置的存储单元垫中的每一个字线在多个存储单元垫中彼此相邻。分配具有多个激活字线的存储单元垫。因此，施加到用于驱动字线的驱动电路的负载和施加到用于向驱动器电路提供工作电压的电源电路的负载减小。

9. 发明申请

US20090201753A1 Semiconductor memory device, control method therefor, and method for determining repair possibility of defective address 有权
标题翻译：半导体存储器件及其控制方法以及用于确定缺陷地址修复可能性的方法
公开(公告)号：US20090201753A1
公开(公告)日：2009-08-13
申请号：US12320892
申请日：2009-02-06
申请人： Yoshiro Riho , Jun Suzuki , Yasuhiro Matsumoto , Shuichi Kubouchi , Hiromasa Noda , Yasuji Koshikawa
发明人： Yoshiro Riho , Jun Suzuki , Yasuhiro Matsumoto , Shuichi Kubouchi , Hiromasa Noda , Yasuji Koshikawa
IPC分类号： G11C29/00 , G11C8/00 , G11C17/16
CPC分类号： G11C8/08 , G11C8/10 , G11C29/84
摘要： There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit.
摘要翻译：提供有多个存储器垫，子字驱动器，其访问正常存储器单元，而不管请求访问的行地址是否是缺陷地址;子字驱动器，访问属于当行地址是缺陷地址时，由行地址指示的正常存储单元不同的存储器垫。根据本发明，正常存储单元和冗余存储单元属于彼此不同的存储器单元，从而可以在确定修复确定电路的操作的同时访问正常存储单元。

10. 发明申请

US20080067551A1 Semiconductor device having pseudo power supply wiring and method of designing the same 审中-公开
标题翻译：具有伪电源布线的半导体装置及其设计方法
公开(公告)号：US20080067551A1
公开(公告)日：2008-03-20
申请号：US11898155
申请日：2007-09-10
申请人： Yoshiro Riho , Ken Ota , Hiromasa Noda , Shinichi Miyatake
发明人： Yoshiro Riho , Ken Ota , Hiromasa Noda , Shinichi Miyatake
IPC分类号： H01L27/105 , G06F17/50
CPC分类号： G06F17/5068 , G06F2217/78 , H01L23/5286 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： Inverters are connected between a pseudo power supply wiring and a main power supply wiring, while inverters are connected between a main power supply wiring VDD and a pseudo power supply wiring. Connected to the sources of transistors are switching areas for switching to the main power supply wiring or the pseudo power supply wiring. Connected to the sources of transistors are switching areas for switching to the main power supply wiring or the pseudo power supply wiring. Even if improper connections are found or logical changes are required, the connection destination of the source is switched easily.
摘要翻译：逆变器连接在伪电源线和主电源配线之间，而逆变器连接在主电源线VDD和伪电源配线之间。连接到晶体管的源极的是用于切换到主电源布线或伪电源布线的开关区域。连接到晶体管的源极的是用于切换到主电源布线或伪电源布线的开关区域。即使发现不正确的连接或需要进行逻辑更改，源的连接目的地也很容易切换。

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