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1. 发明申请

US20120133399A1 SEMICONDUCTOR DEVICE HAVING SENSE AMPLIFIER 有权
标题翻译：具有感应放大器的半导体器件
公开(公告)号：US20120133399A1
公开(公告)日：2012-05-31
申请号：US13306560
申请日：2011-11-29
申请人： Yuko WATANABE , Yoshiro RIHO , Hiromasa NODA , Yoji IDEI , Kosuke GOTO
发明人： Yuko WATANABE , Yoshiro RIHO , Hiromasa NODA , Yoji IDEI , Kosuke GOTO
IPC分类号： H03K3/00
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/08 , G11C7/222 , G11C11/4074 , G11C11/4076
摘要： A semiconductor device includes a first driver circuit for supplying a first potential to a first power supply node of the sense amplifier, second and third driver circuits for supplying a second potential and a third potential to a second power supply node of the sense amplifier, and a timing control circuit for controlling operations of the first to third driver circuits. The timing control circuit includes a delay circuit for deciding an ON period of the third driver circuit. The delay circuit includes a first delay circuit having a delay amount that depends on an external power supply potential and a second delay circuit having a delay amount that does not depend on the external power supply potential, and the ON period of the third driver circuit is decided based on a sum of the delay amounts of the first and second delay circuits.
摘要翻译：半导体器件包括用于向读出放大器的第一电源节点提供第一电位的第一驱动器电路，用于向读出放大器的第二电源节点提供第二电位和第三电位的第二和第三驱动器电路，以及用于控制第一至第三驱动器电路的操作的定时控制电路。定时控制电路包括用于决定第三驱动电路的接通时间的延迟电路。延迟电路包括具有取决于外部电源电位的延迟量的第一延迟电路和具有不依赖于外部电源电位的延迟量的第二延迟电路，并且第三驱动电路的导通周期为基于第一和第二延迟电路的延迟量的总和来决定。

2. 发明申请

US20120127814A1 SEMICONDUCTOR DEVICE PERFORMING STRESS TEST 有权
标题翻译：执行应力测试的半导体器件
公开(公告)号：US20120127814A1
公开(公告)日：2012-05-24
申请号：US13302772
申请日：2011-11-22
申请人： Yoshiro RIHO , Hiromasa NODA , Kazuki SAKUMA
发明人： Yoshiro RIHO , Hiromasa NODA , Kazuki SAKUMA
IPC分类号： G11C29/00
CPC分类号： G11C29/00 , G11C29/02 , G11C29/06 , G11C29/12005 , G11C29/28 , G11C29/50 , G11C2029/1202 , G11C2029/2602
摘要： A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays. Each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at one time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent each other in the plurality of memory cell mats. The memory cell mats with the plurality of activated word lines are distributed. Therefore, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced
摘要翻译：半导体器件包括由多个读出放大器阵列分成多个存储单元阵列的存储单元阵列。多个存储单元垫中的每一个包括多个字线和用于执行测试控制的测试电路，以一次激活多个选定的未设置的存储单元垫中的每一个字线在多个存储单元垫中彼此相邻。分配具有多个激活字线的存储单元垫。因此，施加到用于驱动字线的驱动电路的负载和施加到用于向驱动器电路提供工作电压的电源电路的负载减小

3. 发明申请

US20080212386A1 SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, MEMORY SYSTEM AND REFRESH CONTROL METHOD 审中-公开
标题翻译：半导体存储器件，半导体器件，存储器系统和刷新控制方法
公开(公告)号：US20080212386A1
公开(公告)日：2008-09-04
申请号：US11964303
申请日：2007-12-26
申请人： Yoshiro RIHO
发明人： Yoshiro RIHO
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/406 , G11C5/025 , G11C8/06 , G11C8/12 , G11C11/40618 , G11C11/40622
摘要： A semiconductor memory device comprises: a memory cell array in which memory cells are divided into banks; cache memories each for storing data of a word line selected by a row address; a setting register for setting a data holding capacity so that a holding area where data is held during a self refresh period and a non-holding area where data is not held during the self refresh period are commonly included in each bank; a refresh controller for outputting a row address to be refreshed at predetermined intervals during the self refresh period and for performing a refresh operation for a selected word line corresponding to the row address in an activated bank; and a bank controller for activating all banks when the selected word line is included in the holding area and inactivating all banks when the selected word Line is included in the non-holding area.
摘要翻译：半导体存储器件包括：存储器单元阵列，其中存储器单元被划分为存储体; 高速缓存存储器，用于存储由行地址选择的字线的数据; 一个设置寄存器，用于设置数据保持容量，使得在自刷新周期期间保持数据的保持区域和在自刷新周期期间不保持数据的非保持区域通常包括在每个存储体中; 刷新控制器，用于在自刷新周期期间以预定间隔输出要刷新的行地址，并且用于对与激活的存储体中的行地址相对应的所选字线执行刷新操作; 以及当所选择的字线被包括在保持区域中时激活所有存储体的存储体控制器，并且当所选择的字线被包括在非保持区域中时使所有存储体停用。

4. 发明申请

US20080211572A1 REFERENCE VOLTAGE GENERATING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：参考电压发生电路和半导体集成电路器件
公开(公告)号：US20080211572A1
公开(公告)日：2008-09-04
申请号：US12018375
申请日：2008-01-23
申请人： Yoshiro RIHO
发明人： Yoshiro RIHO
IPC分类号： G05F3/16
CPC分类号： G11C11/4074 , G11C5/147 , G11C7/04 , G11C11/4099
摘要： A reference voltage generating circuit comprises: a monitor circuit, including a low threshold voltage PMOS transistor, a low threshold voltage NMOS transistor, and a resistor having a predetermined resistance which are connected in series, for generating a reference voltage at one end; and an additional circuit for supplying a monitor current to the monitor circuit and for controlling the other end of the monitor circuit to be at a constant voltage, wherein a voltage value of the reference voltage is corrected within a range corresponding to a process fluctuation from a predetermined center value, based on the monitor current changing in response to the process fluctuation.
摘要翻译：参考电压产生电路包括：监测电路，包括低阈值电压PMOS晶体管，低阈值电压NMOS晶体管和串联连接的具有预定电阻的电阻器，用于在一端产生参考电压; 以及附加电路，用于向监视电路提供监视电流，并将监视器电路的另一端控制在恒定电压，其中参考电压的电压值在对应于来自基于监视电流响应于过程波动而改变的预定中心值。

5. 发明申请

US20110026293A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110026293A1
公开(公告)日：2011-02-03
申请号：US12838028
申请日：2010-07-16
申请人： Yoshiro RIHO
发明人： Yoshiro RIHO
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C5/02 , G11C11/4076 , G11C11/4093 , H01L25/0657 , H01L25/18 , H01L27/108 , H01L2225/06541 , H01L2924/0002 , H01L2924/14 , H01L2924/19043 , H01L2924/3011 , H01L2924/00
摘要： In a semiconductor device of a stacked structure type having a control chip and a plurality of controlled chips, wherein the control chip allocates different I/O sets to the respective controlled chips and processes the I/O sets within the same access cycle, the controlled chip close to the control chip and positioned to a lower position in the stacked structure has I/O penetrating through substrate vias connected to penetrating through interconnections. The penetrating through interconnections are extended to an upper one of the controlled chips that not use the penetrating through interconnections and, as a result, all of the penetrating through interconnections have the same lengths as each other.
摘要翻译：在具有控制芯片和多个受控芯片的堆叠结构类型的半导体器件中，其中控制芯片将不同的I / O组分配给相应的受控芯片，并且在相同的访问周期内对该I / O集进行处理，靠近控制芯片的芯片并且位于堆叠结构中的较低位置，具有穿透连接到穿透互连件的衬底通孔的I / O。通过互连的穿透被扩展到不使用穿透互连的受控芯片的上部，并且因此，所有穿透互连件的所有穿透互连件具有彼此相同的长度。

6. 发明申请

US20080133985A1 SEMICONDUCTOR DEVICE AND TESTING METHOD FOR SAME 失效
标题翻译：半导体器件及其测试方法
公开(公告)号：US20080133985A1
公开(公告)日：2008-06-05
申请号：US11968664
申请日：2008-01-03
申请人： Yoshiro RIHO , Yutaka Ito
发明人： Yoshiro RIHO , Yutaka Ito
IPC分类号： G11C29/08 , G06F11/26
CPC分类号： G06F11/1076 , G06F11/1012 , G11C11/406 , G11C29/42 , G11C2211/4062
摘要： A test method for a semiconductor device that is provided with an ECC circuit that uses product code that is composed of a first code and a second code for implementing error correction of a memory, the test method includes steps of: obtaining first pass/fail determination results and second pass/fail determination results that are realized by independent correction operations based on the first code and the second code, respectively; recording the results in a first fail memory and a second fail memory, respectively; executing a prescribed logical operation such as an AND operation relating to the contents of the first fail memory and the contents of the second fail memory; and based on the results of the logical operation, remedying both fail bits and potential fail bits.
摘要翻译：一种半导体器件的测试方法，该半导体器件设置有使用由第一代码组成的产品代码和用于实现存储器的错误校正的第二代码的ECC电路，该测试方法包括以下步骤：获得第一通过/不确定分别通过基于第一代码和第二代码的独立校正操作实现的结果和第二通过/失败确定结果; 将结果分别记录在第一故障存储器和第二故障存储器中; 执行诸如与第一故障存储器的内容和第二故障存储器的内容有关的AND操作的规定的逻辑操作; 并基于逻辑运算的结果，纠正故障位和潜在故障位。

7. 发明申请

US20140232429A1 DEVICE 有权
标题翻译：设备
公开(公告)号：US20140232429A1
公开(公告)日：2014-08-21
申请号：US14266217
申请日：2014-04-30
申请人： Yoshiro RIHO
发明人： Yoshiro RIHO
IPC分类号： H03K19/00
CPC分类号： H03K19/0005 , H03K19/018521 , H04L25/0278
摘要： A semiconductor device has a first controlled chip, including a first replica output circuit having the same configuration as a first output circuit, a first ZQ terminal connected to the first replica output circuit, a first through electrode connected to the first ZQ terminal, and a first control circuit which sets the impedance of the first replica output circuit. A control chip includes a second ZQ terminal connected to the first through electrode, a comparator circuit which compares a voltage of the second ZQ terminal with a reference voltage, and a second control circuit 123 which performs a process based on a comparison by the comparator circuit. The first control circuit and the second control circuit receive a common input signal to operate and sequentially change and set the impedance until the comparison result changes when an external resistance element is connected to the second ZQ terminal
摘要翻译：半导体器件具有第一受控芯片，包括具有与第一输出电路相同的配置的第一复制输出电路，连接到第一复制输出电路的第一ZQ端子，连接到第一ZQ端子的第一通电极和第一控制电路，其设置第一复制输出电路的阻抗。控制芯片包括连接到第一贯通电极的第二ZQ端子，将第二ZQ端子的电压与参考电压进行比较的比较器电路，以及基于比较器电路进行比较的处理的第二控制电路123 。第一控制电路和第二控制电路接收公共输入信号以操作并顺序地改变和设置阻抗，直到当外部电阻元件连接到第二ZQ端子时比较结果改变

8. 发明申请

US20120262198A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120262198A1
公开(公告)日：2012-10-18
申请号：US13531346
申请日：2012-06-22
申请人： Yoshiro RIHO
发明人： Yoshiro RIHO
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： G11C5/063 , G11C5/02 , G11C5/04 , H01L23/60 , H01L27/0296 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06596 , H01L2924/00014 , H01L2924/13091 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method of testing a semiconductor device includes providing a first wafer that includes a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode, providing a second wafer that includes a second electrode penetrating the second wafer, stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer, probing a needle to the pad, and supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.
摘要翻译：一种测试半导体器件的方法包括提供第一晶片，其包括第一表面，分配在第一表面的相对侧的第二表面，从第一表面穿过第一晶片的第一电极到第二表面，以及垫，其形成在第一表面上并与第一电极电连接，提供包括穿透第二晶片的第二电极的第二晶片，将第一晶片堆叠到第二晶片上以将第一电极与第二电极连接，使得第二第一晶片的表面面向第二晶片，探针到焊盘，并且以第一晶片堆叠在第二晶片上的状态提供到第一电极的测试信号，以将测试信号输入到第二晶片晶片经由第一电极和第二电极。

9. 发明申请

US20140247683A1 SEMICONDUCTOR DEVICE HAVING A CONTROL CHIP STACKED WITH A CONTROLLED CHIP 有权
标题翻译：具有控制芯片堆叠的控制芯片的半导体器件
公开(公告)号：US20140247683A1
公开(公告)日：2014-09-04
申请号：US14274267
申请日：2014-05-09
申请人： Yoshiro RIHO
发明人： Yoshiro RIHO
IPC分类号： G11C11/4063
CPC分类号： G11C11/4063 , G11C5/063 , G11C7/1066 , G11C7/1093 , G11C7/222 , G11C11/40 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C29/023 , G11C29/028 , H01L25/0657 , H01L2224/16145 , H01L2924/1305 , H01L2924/13091 , H03L7/0812 , H03L7/097 , H01L2924/00
摘要： A semiconductor device includes a first controlled chip and a control chip stacked therewith. The first controlled chip includes a first circuit outputting a data signal in response to a synchronization signal, an input/output circuit outputting the data signal to a data terminal in synchronization with a delayed synchronization signal, and a replica circuit replicating an output circuit and outputting a replica signal to a first replica terminal in synchronization with the delayed synchronization signal. The control chip includes a first control circuit outputting a synchronization signal and receiving a data signal, a delay adjustment circuit delaying the synchronization signal and outputting the same as a delayed synchronization signal, a phase comparator circuit comparing the phases of the replica signal and the synchronization signal, and a delay control circuit controlling the delay amount of the delay adjustment circuit based on a comparison result of the phase comparator circuit.
摘要翻译：半导体器件包括第一受控芯片和与其堆叠的控制芯片。第一受控芯片包括响应于同步信号输出数据信号的第一电路，与延迟同步信号同步地将数据信号输出到数据端的输入/输出电路，复制输出电路并输出与延迟的同步信号同步的第一副本终端的复制信号。控制芯片包括输出同步信号并接收数据信号的第一控制电路，延迟同步信号并将其作为延迟同步信号输出的延迟调整电路，比较复制信号和同步的相位的相位比较器电路信号，以及延迟控制电路，其基于相位比较器电路的比较结果来控制延迟调整电路的延迟量。

10. 发明申请

US20120146707A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120146707A1
公开(公告)日：2012-06-14
申请号：US13311392
申请日：2011-12-05
申请人： Yoshiro RIHO
发明人： Yoshiro RIHO
IPC分类号： H03K17/56 , H01L23/48
CPC分类号： G11C7/10 , G11C5/02 , G11C7/20 , G11C8/12 , G11C8/18 , G11C29/023 , G11C29/028 , H01L23/481 , H01L24/06 , H01L24/14 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/05082 , H01L2224/05087 , H01L2224/05096 , H01L2224/05548 , H01L2224/05567 , H01L2224/05568 , H01L2224/06181 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13025 , H01L2224/13564 , H01L2224/14181 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01055 , H01L2924/01074 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/1436 , H01L2924/14361 , H01L2924/00 , H01L2224/05552
摘要： Disclosed herein is a device that includes a first terminal operatively supplied with a pulse signal, a second terminal, a set of third terminals operatively supplied with identification information, a storage unit configured to store the identification information in response to the pulse signal, and a control unit configured to electrically disconnect the first terminal from the second terminal until the storage unit stores the identification information and electrically connect the first terminal to the second terminal after the storage unit has stored the identification information. This device may be used as each of semiconductor chips that are stacked with each other.
摘要翻译：本文公开了一种装置，其包括可操作地提供有脉冲信号的第一端子，第二端子，可操作地提供有识别信息的一组第三端子，被配置为响应于脉冲信号存储识别信息的存储单元，以及所述控制单元被配置为从所述第二终端电气断开所述第一终端，直到所述存储单元存储所述识别信息，并且在所述存储单元存储所述识别信息之后将所述第一终端电连接到所述第二终端。该装置可以用作彼此堆叠的每个半导体芯片。

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