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1. 发明专利

JP2009109961A Engine control by remote control 审中-公开
标题翻译：发动机遥控控制
公开(公告)号：JP2009109961A
公开(公告)日：2009-05-21
申请号：JP2007305058
申请日：2007-10-28
申请人： Kazuki Sakuma , 一樹佐久真
发明人： SAKUMA KAZUKI
IPC分类号： G09B9/04 , G09B9/06
摘要： PROBLEM TO BE SOLVED: To provide a device and a system for assisting steering and operation safely and efficiently while preventing an accident from occurring by controlling an engine and a brake or the like manually or automatically or by remote control from a separate position in vehicle drive training and ship steering training (personal watercraft or the like) and operation of machine or the like.
SOLUTION: Control of the brake and an engine ignition signal is performed by remote control while judging circumstances in a remote controller provided in a vehicle, a ship and a machine or the like from a remote control transmitter. Engine control operation is performed to apply a current to a relay through a receiver 1, and applying currents of ignition signals 18 and 21 relayed through the switch relay to a body intermittently or continuously so as to perform control as a kill switch 3. An auxiliary manual switch 2 is used to cut the engine ignition signal through a connected string. When falling down, the engine is stopped by applying an engine ignition current to the body side by an automatic switch 3 attached to a main body perpendicularly and starting energizing when it becomes horizontal.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种装置和系统，用于通过手动或自动地或通过远程控制从单独的位置控制发动机和制动器等来安全而有效地辅助转向和操作，同时防止发生事故在车辆驾驶培训和船舶转向训练（个人船舶等）和机器等的操作中。解决方案：通过远程控制来执行制动器和发动机点火信号的控制，同时判断来自遥控发射器的车辆，船舶和机器等中提供的遥控器中的情况。执行发动机控制操作以通过接收器1向继电器施加电流，并且将间歇或连续地通过开关继电器中继的点火信号18和21的电流施加到主体，以便执行作为停止开关3的控制。辅助手动开关2用于通过连接的串来切断发动机点火信号。当下降时，发动机通过垂直安装在主体上的自动开关3施加发动机点火电流而停止，并且当其变为水平时开始通电。版权所有（C）2009，JPO＆INPIT

2. 发明申请

US20140211582A1 Semiconductor Device Performing Stress Test 有权
标题翻译：半导体器件进行应力测试
公开(公告)号：US20140211582A1
公开(公告)日：2014-07-31
申请号：US14243183
申请日：2014-04-02
申请人： Yoshiro Riho , Hiromasa Noda , Kazuki Sakuma
发明人： Yoshiro Riho , Hiromasa Noda , Kazuki Sakuma
IPC分类号： G11C29/00
CPC分类号： G11C29/00 , G11C29/02 , G11C29/06 , G11C29/12005 , G11C29/28 , G11C29/50 , G11C2029/1202 , G11C2029/2602
摘要： A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays, and each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at a time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent to each other in the plurality of memory cell mats. According to the present invention, the memory cell mats with the plurality of activated word lines are distributed. Therefore, as compared with many word lines activated in one memory cell mat, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced. As a result, more word lines can be activated at the same time.
摘要翻译：半导体器件包括存储单元阵列，其通过多个读出放大器阵列被分成多个存储单元阵列，并且多个存储单元阵列中的每一个包括多个字线和用于执行测试控制的测试电路一次激活在多个存储单元垫中彼此不邻近设置的多个所选存储单元垫中的每一个中包括的多个字线。根据本发明，分配具有多个激活字线的存储单元垫。因此，与在一个存储单元垫中激活的许多字线相比，施加到用于驱动字线的驱动电路的负载和施加到用于向驱动器电路提供工作电压的电源电路的负载减小。因此，可以同时激活更多的字线。

3. 发明授权

US08737149B2 Semiconductor device performing stress test 有权
标题翻译：半导体器件进行压力测试
公开(公告)号：US08737149B2
公开(公告)日：2014-05-27
申请号：US13302772
申请日：2011-11-22
申请人： Yoshiro Riho , Hiromasa Noda , Kazuki Sakuma
发明人： Yoshiro Riho , Hiromasa Noda , Kazuki Sakuma
IPC分类号： G11C7/00 , G11C29/50 , G11C29/02 , G11C29/06 , G11C29/12 , G11C29/28
CPC分类号： G11C29/00 , G11C29/02 , G11C29/06 , G11C29/12005 , G11C29/28 , G11C29/50 , G11C2029/1202 , G11C2029/2602
摘要： A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays. Each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at one time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent each other in the plurality of memory cell mats. The memory cell mats with the plurality of activated word lines are distributed. Therefore, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced.
摘要翻译：半导体器件包括由多个读出放大器阵列分成多个存储单元阵列的存储单元阵列。多个存储单元垫中的每一个包括多个字线和用于执行测试控制的测试电路，以一次激活多个选定的未设置的存储单元垫中的每一个字线在多个存储单元垫中彼此相邻。分配具有多个激活字线的存储单元垫。因此，施加到用于驱动字线的驱动电路的负载和施加到用于向驱动器电路提供工作电压的电源电路的负载减小。

4. 发明授权

US06885092B1 Semiconductor device and a memory system including a plurality of IC chips in a common package 失效
标题翻译：半导体器件和包括公共封装中的多个IC芯片的存储器系统
公开(公告)号：US06885092B1
公开(公告)日：2005-04-26
申请号：US09453171
申请日：1999-12-02
申请人： Kazuki Sakuma , Masayasu Kawamura , Yasushi Takahashi , Masachika Masuda , Tamaki Wada , Michiaki Sugiyama , Hirotaka Nishizawa , Toshio Sugano
发明人： Kazuki Sakuma , Masayasu Kawamura , Yasushi Takahashi , Masachika Masuda , Tamaki Wada , Michiaki Sugiyama , Hirotaka Nishizawa , Toshio Sugano
IPC分类号： G11C8/00 , H01L23/02 , H01L23/495 , H01L23/28 , H01L23/04 , H01L23/48
CPC分类号： H01L24/06 , H01L23/4951 , H01L23/49537 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/73215 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01055 , H01L2924/01058 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.
摘要翻译：半导体器件通过层叠两个半导体芯片与其背面面对面设置而形成。每个半导体芯片设置有用于时钟使能的外部引线，时钟使能信号和芯片选择信号被单独地输入。在访问一个半导体芯片的情况下，通过将时钟使能信号和芯片选择信号设置为非活动状态，将另一个半导体芯片设置为低功耗模式。

5. 发明申请

US20120127814A1 SEMICONDUCTOR DEVICE PERFORMING STRESS TEST 有权
标题翻译：执行应力测试的半导体器件
公开(公告)号：US20120127814A1
公开(公告)日：2012-05-24
申请号：US13302772
申请日：2011-11-22
申请人： Yoshiro RIHO , Hiromasa NODA , Kazuki SAKUMA
发明人： Yoshiro RIHO , Hiromasa NODA , Kazuki SAKUMA
IPC分类号： G11C29/00
CPC分类号： G11C29/00 , G11C29/02 , G11C29/06 , G11C29/12005 , G11C29/28 , G11C29/50 , G11C2029/1202 , G11C2029/2602
摘要： A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays. Each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at one time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent each other in the plurality of memory cell mats. The memory cell mats with the plurality of activated word lines are distributed. Therefore, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced
摘要翻译：半导体器件包括由多个读出放大器阵列分成多个存储单元阵列的存储单元阵列。多个存储单元垫中的每一个包括多个字线和用于执行测试控制的测试电路，以一次激活多个选定的未设置的存储单元垫中的每一个字线在多个存储单元垫中彼此相邻。分配具有多个激活字线的存储单元垫。因此，施加到用于驱动字线的驱动电路的负载和施加到用于向驱动器电路提供工作电压的电源电路的负载减小

6. 发明申请

US20050184380A1 Semiconductor device and a memory system including a plurality of IC chips in a common package 有权
公开(公告)号：US20050184380A1
公开(公告)日：2005-08-25
申请号：US11114175
申请日：2005-04-26
申请人： Kazuki Sakuma , Masayasu Kawamura , Yasushi Takahashi , Masachika Masuda , Tamaki Wada , Michiaki Sugiyama , Hirotaka Nishizawa , Toshio Sugano
发明人： Kazuki Sakuma , Masayasu Kawamura , Yasushi Takahashi , Masachika Masuda , Tamaki Wada , Michiaki Sugiyama , Hirotaka Nishizawa , Toshio Sugano
IPC分类号： G11C8/00 , H01L23/02 , H01L23/495
CPC分类号： H01L24/06 , H01L23/4951 , H01L23/49537 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/73215 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01055 , H01L2924/01058 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.

7. 发明申请

US20080151659A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20080151659A1
公开(公告)日：2008-06-26
申请号：US11959253
申请日：2007-12-18
申请人： Kazuki Sakuma , Jun Suzuki , Chiaki Dono
发明人： Kazuki Sakuma , Jun Suzuki , Chiaki Dono
IPC分类号： G11C7/00 , G11C29/00 , G11C8/00
CPC分类号： G11C29/40 , G11C5/04 , G11C29/802
摘要： A semiconductor memory device includes at least one memory bank. Each memory bank includes: memory units that output data in response to a burst read command; a selector section that sequentially outputs the data output from the memory units in accordance with a select signal; a comparator section that compares the data sequentially output from the selector section with reference data sequentially input, outputs a comparison result indicating normal when the data output from the selector section matches with the reference data, and outputs a comparison result indicating abnormal when the data output from the selector section does not match with the reference data; and a reduction result storage section that stores, as a reduction result of the memory bank, a value indicating normal when comparison results sequentially output from the comparator section all indicate normal, and a value indicating abnormal when any one of the comparison results indicates abnormal.
摘要翻译：半导体存储器件包括至少一个存储体。每个存储体包括：响应突发读命令输出数据的存储器单元; 选择器部分，其根据选择信号依次输出从存储器单元输出的数据; 将从选择器部顺序地输出的数据与依次输入的参考数据进行比较的比较器部，当从选择部输出的数据与参考数据匹配时，输出表示正常的比较结果，并输出指示异常的比较结果从选择器部分与参考数据不匹配; 以及减少结果存储部分，当从比较器部分顺序输出的比较结果全部表示正常时，作为存储体的缩小结果，存储指示正常的值，以及当比较结果指示异常时表示异常的值。

8. 发明授权

US07227251B2 Semiconductor device and a memory system including a plurality of IC chips in a common package 有权
标题翻译：半导体器件和包括公共封装中的多个IC芯片的存储器系统
公开(公告)号：US07227251B2
公开(公告)日：2007-06-05
申请号：US11114175
申请日：2005-04-26
申请人： Kazuki Sakuma , Masayasu Kawamura , Yasushi Takahashi , Masachika Masuda , Tamaki Wada , Michiaki Sugiyama , Hirotaka Nishizawa , Toshio Sugano
发明人： Kazuki Sakuma , Masayasu Kawamura , Yasushi Takahashi , Masachika Masuda , Tamaki Wada , Michiaki Sugiyama , Hirotaka Nishizawa , Toshio Sugano
IPC分类号： H01L23/02 , H01L23/48 , G11C8/00
CPC分类号： H01L24/06 , H01L23/4951 , H01L23/49537 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/73215 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01055 , H01L2924/01058 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.
摘要翻译：半导体器件通过层叠两个半导体芯片与其背面面对面设置而形成。每个半导体芯片设置有用于时钟使能的外部引线，时钟使能信号和芯片选择信号被单独地输入。在访问一个半导体芯片的情况下，通过将时钟使能信号和芯片选择信号设置为非活动状态，将另一个半导体芯片设置为低功耗模式。

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