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1. 发明授权

US06389518B1 Multiprocessor system and methods for transmitting memory access transactions for the same 有权
公开(公告)号：US06389518B1
公开(公告)日：2002-05-14
申请号：US09523737
申请日：2000-03-13
申请人： Yuji Tsushima , Hideya Akashi , Keitaro Uehara , Naoki Hamanaka , Toru Shonai , Tetsuhiko Okada , Masamori Kashiyama
发明人： Yuji Tsushima , Hideya Akashi , Keitaro Uehara , Naoki Hamanaka , Toru Shonai , Tetsuhiko Okada , Masamori Kashiyama
IPC分类号： G06F1200
摘要： In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation. On the other hand, when there is no possibility that the memory to be accessed is cached, this memory access command is transferred only to the target node in yan one-to-one correspondence.

2. 发明授权

US06591325B1 Method and apparatus of out-of-order transaction processing using request side queue pointer and response side queue pointer 失效
标题翻译：使用请求侧队列指针和响应端队列指针进行乱序事务处理的方法和装置
公开(公告)号：US06591325B1
公开(公告)日：2003-07-08
申请号：US09547392
申请日：2000-04-11
申请人： Hideya Akashi , Yuji Tsushima , Keitaro Uehara , Naoki Hamanaka , Toru Shonai , Tetsuhiko Okada , Masamori Kashiyama
发明人： Hideya Akashi , Yuji Tsushima , Keitaro Uehara , Naoki Hamanaka , Toru Shonai , Tetsuhiko Okada , Masamori Kashiyama
IPC分类号： G06F1314
CPC分类号： G06F13/4204
摘要： An information processing system that transfers transactions between a plurality of system modules. A request side interface unit in a request side module has a request ID queue in which issued request transactions are stored in order of issuance. A request side queue pointer points to an entry in this request ID queue corresponding to a response transaction to be accepted next. A response side interface unit in a response side module has a response queue in which accepted request transactions are stored in order of acceptance. A response side queue pointer points to an entry in this response queue corresponding to a response transaction to be issued next. Therefore, a request transaction and the corresponding response transaction are transferred between the request side interface unit and the response side interface unit without transferring transaction IDs. When the response order is changed, the response side interface unit issues a command, which changes the value of the request side queue pointer, to inform the request side interface unit of the change in the order.
摘要翻译：一种在多个系统模块之间传送交易的信息处理系统。请求侧模块中的请求侧接口单元具有请求ID队列，其中发出的请求事务按照发布的顺序存储。请求侧队列指针指向与要接受的响应事务相对应的该请求ID队列中的条目。响应侧模块中的响应侧接口单元具有响应队列，其中接受请求事务按接受顺序存储。响应侧队列指针指向对应于接下来要发出的响应事务的该响应队列中的条目。因此，在请求侧接口单元和响应侧接口单元之间传送请求事务和相应的响应事务，而不转移事务ID。当响应顺序改变时，响应侧接口单元发出改变请求侧队列指针的值的命令，以通知请求侧接口单元的顺序改变。

3. 发明授权

US06516391B1 Multiprocessor system and methods for transmitting memory access transactions for the same 失效
标题翻译：用于传输内存访问事务的多处理器系统和方法相同
公开(公告)号：US06516391B1
公开(公告)日：2003-02-04
申请号：US09523737
申请日：2000-03-13
申请人： Yuji Tsushima , Hideya Akashi , Keitaro Uehara , Naoki Hamanaka , Toru Shonai , Tetsuhiko Okada , Masamori Kashiyama
发明人： Yuji Tsushima , Hideya Akashi , Keitaro Uehara , Naoki Hamanaka , Toru Shonai , Tetsuhiko Okada , Masamori Kashiyama
IPC分类号： G06F1200
CPC分类号： G06F12/0813 , G06F12/0817 , G06F15/177 , G06F2212/2542
摘要： In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation. On the other hand, when there is no possibility that the memory to be accessed is cached, this memory access command is transferred only to the target node in yan one-to-one correspondence.
摘要翻译：在根据其中包含多个处理器单元的多个处理器节点经由网络彼此耦合的NUMA或UMA而布置的多处理器中，结合存储器访问操作执行的高速缓存侦听操作在两个阶段即在节点内执行的本地侦听操作，以及节点之间的全局侦听操作。在执行本地侦听操作之前，向具有存储器的目标节点发出用于指定存储器的RAS的ACTV命令，并且预先激活存储器访问。另外指定存储器的CAS，并且在发出ACTV命令之后重新执行存储器访问，然后发出存储器访问命令。当存在待访问的存储器存在除了源节点之外的处理器节点的可能性时，该存储器访问命令被发布以分发给所有节点，以便执行全局侦听操作。另一方面，当不存在要访问的存储器被缓存时，该存储器访问命令仅以一对一对应的方式传送到目标节点。

4. 发明授权

US06789173B1 Node controller for performing cache coherence control and memory-shared multiprocessor system 失效
标题翻译：用于执行高速缓存一致性控制和内存共享多处理器系统的节点控制器
公开(公告)号：US06789173B1
公开(公告)日：2004-09-07
申请号：US09585390
申请日：2000-06-02
申请人： Tsuyoshi Tanaka , Hideya Akashi , Yuji Tsushima , Keitaro Uehara , Naoki Hamanaka , Toru Shonai
发明人： Tsuyoshi Tanaka , Hideya Akashi , Yuji Tsushima , Keitaro Uehara , Naoki Hamanaka , Toru Shonai
IPC分类号： G06F1200
CPC分类号： G06F12/0813
摘要： In a multiprocessor system of a main memory shared type having a plurality of nodes connected each other through signal lines; each of the plurality of nodes includes CPUs having caches therein, a main memory, and a node controller for performing communication control between the CPUs, main memory and ones of the nodes other than its own node. The node controller has a communication controller for controlling communication interface between the plurality of nodes, a crossbar for determining a processing sequence of memory access issued from at least one of the plurality of nodes to be directed to the main memories of the plurality of nodes, and crossbar controller for making valid or invalid the crossbar.
摘要翻译：在具有通过信号线彼此连接的多个节点的主存储器共享类型的多处理器系统中; 所述多个节点中的每一个包括其中具有高速缓存的CPU，主存储器和节点控制器，用于执行CPU，主存储器以及除了其自身节点之外的节点之间的通信控制。节点控制器具有用于控制多个节点之间的通信接口的通信控制器，用于确定从多个节点中的至少一个节点发出的指向多个节点的主存储器的存储器访问的处理顺序的交叉开关，和横杆控制器使横梁有效或无效。

5. 发明授权

US06636926B2 Shared memory multiprocessor performing cache coherence control and node controller therefor 失效
标题翻译：共享内存多处理器执行高速缓存一致性控制和节点控制器
公开(公告)号：US06636926B2
公开(公告)日：2003-10-21
申请号：US09740816
申请日：2000-12-21
申请人： Yoshiko Yasuda , Naoki Hamanaka , Toru Shonai , Hideya Akashi , Yuji Tsushima , Keitaro Uehara
发明人： Yoshiko Yasuda , Naoki Hamanaka , Toru Shonai , Hideya Akashi , Yuji Tsushima , Keitaro Uehara
IPC分类号： G06F1300
CPC分类号： G06F12/0813 , G06F12/0833 , G06F2212/1016
摘要： Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit interconnecting the nodes but directly to the unit designated by the unit information.
摘要翻译：每个节点包括用于解码由处理器或I / O设备发出的访问请求的控制信息和地址信息的节点控制器，基于解码结果生成指示高速缓存一致性控制的高速缓存一致性控制信息是否需要节点信息和传输目的地的单位信息，并将这些信息添加到访问请求。用于连接节点控制器中的单元的节点内连接电路保持高速缓存一致性控制信息，节点信息和添加到访问请求的单元信息。当高速缓存一致性控制信息指示不需要高速缓存一致性控制并且节点信息指示本地节点时，节点内连接电路不是将互连节点的节点间连接电路的访问请求传送到节点间连接电路，而是直接连接到单位由单位信息指定。

6. 发明授权

US06874053B2 Shared memory multiprocessor performing cache coherence control and node controller therefor 失效
标题翻译：共享内存多处理器执行高速缓存一致性控制和节点控制器
公开(公告)号：US06874053B2
公开(公告)日：2005-03-29
申请号：US10654983
申请日：2003-09-05
申请人： Yoshiko Yasuda , Naoki Hamanaka , Toru Shonai , Hideya Akashi , Yuji Tsushima , Keitaro Uehara
发明人： Yoshiko Yasuda , Naoki Hamanaka , Toru Shonai , Hideya Akashi , Yuji Tsushima , Keitaro Uehara
IPC分类号： G06F12/08 , G06F15/173 , G06F13/00 , G06F15/167
CPC分类号： G06F12/0813 , G06F12/0833 , G06F2212/1016
摘要： Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit inter-connecting the node but directly to the unit designated by the unit information.
摘要翻译：每个节点包括用于解码由处理器或I / O设备发出的访问请求的控制信息和地址信息的节点控制器，基于解码结果生成指示高速缓存一致性控制的高速缓存一致性控制信息是否需要节点信息和传输目的地的单位信息，并将这些信息添加到访问请求。用于连接节点控制器中的单元的节点内连接电路保持高速缓存一致性控制信息，节点信息和添加到访问请求的单元信息。当高速缓存一致性控制信息指示不需要高速缓存一致性控制并且节点信息指示本地节点时，节点间连接电路将访问请求传送到不是直接连接节点的节点间连接电路到由单位信息指定的单位。

7. 发明授权

US07313637B2 Fabric and method for sharing an I/O device among virtual machines formed in a computer system 失效
标题翻译：用于在计算机系统中形成的虚拟机之间共享I / O设备的结构和方法
公开(公告)号：US07313637B2
公开(公告)日：2007-12-25
申请号：US10727602
申请日：2003-12-05
申请人： Tsuyoshi Tanaka , Keitaro Uehara , Yuji Tsushima , Naoki Hamanaka , Daisuke Yoshida , Yoshinori Wakai
发明人： Tsuyoshi Tanaka , Keitaro Uehara , Yuji Tsushima , Naoki Hamanaka , Daisuke Yoshida , Yoshinori Wakai
IPC分类号： G06F3/00
CPC分类号： G06F9/5077 , G06F11/1484 , G06F11/2033
摘要： Disclosed herein is a computer system provided with a mechanism for connecting a single port disk to an active server and the disk to a standby server when in a fail-over processing. An “add_pci” command issued from a clustering program is used to let a control program change the allocation of a PCI slot while an interruption signal issued to a standby server permits an ACPI processing routine to hot-add a PCI card that includes the disk unit on the subject guest OS.
摘要翻译：这里公开了一种计算机系统，其具有用于在故障转移处理中将单个端口盘连接到活动服务器并且将该盘连接到备用服务器的机构。使用从聚类程序发出的“add_pci”命令使得控制程序改变PCI插槽的分配，同时发出到备用服务器的中断信号允许ACPI处理程序热插入包括盘单元的PCI卡在主题客户操作系统上。

8. 发明授权

US08819675B2 Virtual machine monitor and multiprocessor system 有权
标题翻译：虚拟机监控和多处理器系统
公开(公告)号：US08819675B2
公开(公告)日：2014-08-26
申请号：US12222227
申请日：2008-08-05
申请人： Keitaro Uehara , Yuji Tsushima
发明人： Keitaro Uehara , Yuji Tsushima
IPC分类号： G06F9/455 , G06F9/46 , G06F9/50
CPC分类号： G06F9/5077
摘要： In order to provide an interface of acquiring physical position information of an I/O device on a virtual machine monitor having an exclusive allocation function of the I/O device and optimize allocation of a resource to a virtual server by using the acquired physical position information, a virtual machine monitor includes an interface of allocating a resource in accordance with a given policy (a parameter of determining to which a priority is given in distributing resources) for an I/O device, a CPU NO., and a memory amount request to guest OS. Further, the virtual machine monitor includes an interface of pertinently converting physical position information of the resource allocated by the virtual machine monitor to notice to guest OS.
摘要翻译：为了提供在具有I / O设备的排他分配功能的虚拟机监视器上获取I / O设备的物理位置信息的接口，并且通过使用所获取的物理位置信息来优化资源到虚拟服务器的分配，虚拟机监视器包括根据给定策略（在分配资源中确定给予哪个优先级的参数）为I / O设备分配资源的接口，CPU号和存储量请求到客户操作系统。此外，虚拟机监视器包括适当地转换由虚拟机监视器分配的资源的物理位置信息以通知客户OS的接口。

9. 发明授权

US08046520B2 Compound computer system and method for sharing PCI devices thereof 有权
标题翻译：用于共享其PCI设备的复合计算机系统和方法
公开(公告)号：US08046520B2
公开(公告)日：2011-10-25
申请号：US12635755
申请日：2009-12-11
申请人： Takashige Baba , Keitaro Uehara , Yuji Tsushima
发明人： Takashige Baba , Keitaro Uehara , Yuji Tsushima
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： A resource management module of a management server for controlling a multi-root I/O manager connected to a PCI switch for connecting a plurality of I/O devices and a plurality of computers with each other includes: failure handling content information indicating, for each computer sharing a multi-root I/O device, a content of a failure handling at an occurrence of a failure in the multi-root I/O device; and failure handling availability status information indicating whether a hardware reset of the multi-root I/O device is possible and updates, upon reception of a notification of the occurrence of the failure in the multi-root I/O device, the failure handling availability status information, and instructs, based on the failure handling availability status information, the multi-root I/O manager to restrain or cancel the hardware reset of the multi-root I/O device.
摘要翻译：用于控制连接到用于连接多个I / O设备和多个计算机的PCI交换机的多根I / O管理器的管理服务器的资源管理模块包括：故障处理内容信息，指示每个计算机共享多根I / O设备，在多根I / O设备发生故障时进行故障处理的内容; 以及指示多根I / O设备的硬件复位是否可能的故障处理可用性状态信息，并且在接收到多根I / O设备中发生故障的通知时更新故障处理可用性状态信息，并指示基于故障处理可用性状态信息，多根I / O管理器来限制或取消多根I / O设备的硬件复位。

10. 发明授权

US08533381B2 Computer system, method of managing PCI switch, and management server 失效
标题翻译：计算机系统，PCI交换机管理方法和管理服务器
公开(公告)号：US08533381B2
公开(公告)日：2013-09-10
申请号：US12709405
申请日：2010-02-19
申请人： Keitaro Uehara , Takashige Baba , Yuji Tsushima
发明人： Keitaro Uehara , Takashige Baba , Yuji Tsushima
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F9/4411
摘要： It is provided a computer system including computers, PCI switches each having first and second ports, a switch management module and a power control module. The switch management module includes an identifying module for identifying a first port coupled to the computer to be booted up, and notifying the PCI switch of the first port, an instruction module for instructing the power control module to boot up the computer, and an allocation management module for managing allocation of one of the I/O device to the computer and notifying the one of the PCI switches of the allocation after the computer is booted up. The PCI switches includes a preventing control module for preventing the computer from detecting a configuration of the first port, and a virtual switch generating module for generating a virtual switch that couples the first port and the second port based on the notification.
摘要翻译：提供了一种计算机系统，包括计算机，每个具有第一和第二端口的PCI开关，开关管理模块和电源控制模块。交换机管理模块包括识别模块，用于识别耦合到要启动的计算机的第一端口，并通知第一端口的PCI交换机，用于指示电源控制模块引导计算机的指令模块以及分配管理模块，用于管理其中一个I / O设备到计算机的分配，并在计算机启动后通知PCI交换机中的一个分配。 PCI交换机包括用于防止计算机检测第一端口的配置的防止控制模块，以及用于基于通知生成耦合第一端口和第二端口的虚拟交换机的虚拟交换机生成模块。

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