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1. 发明授权

US06636926B2 Shared memory multiprocessor performing cache coherence control and node controller therefor 失效
标题翻译：共享内存多处理器执行高速缓存一致性控制和节点控制器
公开(公告)号：US06636926B2
公开(公告)日：2003-10-21
申请号：US09740816
申请日：2000-12-21
申请人： Yoshiko Yasuda , Naoki Hamanaka , Toru Shonai , Hideya Akashi , Yuji Tsushima , Keitaro Uehara
发明人： Yoshiko Yasuda , Naoki Hamanaka , Toru Shonai , Hideya Akashi , Yuji Tsushima , Keitaro Uehara
IPC分类号： G06F1300
CPC分类号： G06F12/0813 , G06F12/0833 , G06F2212/1016
摘要： Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit interconnecting the nodes but directly to the unit designated by the unit information.
摘要翻译：每个节点包括用于解码由处理器或I / O设备发出的访问请求的控制信息和地址信息的节点控制器，基于解码结果生成指示高速缓存一致性控制的高速缓存一致性控制信息是否需要节点信息和传输目的地的单位信息，并将这些信息添加到访问请求。用于连接节点控制器中的单元的节点内连接电路保持高速缓存一致性控制信息，节点信息和添加到访问请求的单元信息。当高速缓存一致性控制信息指示不需要高速缓存一致性控制并且节点信息指示本地节点时，节点内连接电路不是将互连节点的节点间连接电路的访问请求传送到节点间连接电路，而是直接连接到单位由单位信息指定。

2. 发明授权

US06874053B2 Shared memory multiprocessor performing cache coherence control and node controller therefor 失效
标题翻译：共享内存多处理器执行高速缓存一致性控制和节点控制器
公开(公告)号：US06874053B2
公开(公告)日：2005-03-29
申请号：US10654983
申请日：2003-09-05
申请人： Yoshiko Yasuda , Naoki Hamanaka , Toru Shonai , Hideya Akashi , Yuji Tsushima , Keitaro Uehara
发明人： Yoshiko Yasuda , Naoki Hamanaka , Toru Shonai , Hideya Akashi , Yuji Tsushima , Keitaro Uehara
IPC分类号： G06F12/08 , G06F15/173 , G06F13/00 , G06F15/167
CPC分类号： G06F12/0813 , G06F12/0833 , G06F2212/1016
摘要： Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit inter-connecting the node but directly to the unit designated by the unit information.
摘要翻译：每个节点包括用于解码由处理器或I / O设备发出的访问请求的控制信息和地址信息的节点控制器，基于解码结果生成指示高速缓存一致性控制的高速缓存一致性控制信息是否需要节点信息和传输目的地的单位信息，并将这些信息添加到访问请求。用于连接节点控制器中的单元的节点内连接电路保持高速缓存一致性控制信息，节点信息和添加到访问请求的单元信息。当高速缓存一致性控制信息指示不需要高速缓存一致性控制并且节点信息指示本地节点时，节点间连接电路将访问请求传送到不是直接连接节点的节点间连接电路到由单位信息指定的单位。

3. 发明授权

US06789173B1 Node controller for performing cache coherence control and memory-shared multiprocessor system 失效
标题翻译：用于执行高速缓存一致性控制和内存共享多处理器系统的节点控制器
公开(公告)号：US06789173B1
公开(公告)日：2004-09-07
申请号：US09585390
申请日：2000-06-02
申请人： Tsuyoshi Tanaka , Hideya Akashi , Yuji Tsushima , Keitaro Uehara , Naoki Hamanaka , Toru Shonai
发明人： Tsuyoshi Tanaka , Hideya Akashi , Yuji Tsushima , Keitaro Uehara , Naoki Hamanaka , Toru Shonai
IPC分类号： G06F1200
CPC分类号： G06F12/0813
摘要： In a multiprocessor system of a main memory shared type having a plurality of nodes connected each other through signal lines; each of the plurality of nodes includes CPUs having caches therein, a main memory, and a node controller for performing communication control between the CPUs, main memory and ones of the nodes other than its own node. The node controller has a communication controller for controlling communication interface between the plurality of nodes, a crossbar for determining a processing sequence of memory access issued from at least one of the plurality of nodes to be directed to the main memories of the plurality of nodes, and crossbar controller for making valid or invalid the crossbar.
摘要翻译：在具有通过信号线彼此连接的多个节点的主存储器共享类型的多处理器系统中; 所述多个节点中的每一个包括其中具有高速缓存的CPU，主存储器和节点控制器，用于执行CPU，主存储器以及除了其自身节点之外的节点之间的通信控制。节点控制器具有用于控制多个节点之间的通信接口的通信控制器，用于确定从多个节点中的至少一个节点发出的指向多个节点的主存储器的存储器访问的处理顺序的交叉开关，和横杆控制器使横梁有效或无效。

4. 发明授权

US06516391B1 Multiprocessor system and methods for transmitting memory access transactions for the same 失效
标题翻译：用于传输内存访问事务的多处理器系统和方法相同
公开(公告)号：US06516391B1
公开(公告)日：2003-02-04
申请号：US09523737
申请日：2000-03-13
申请人： Yuji Tsushima , Hideya Akashi , Keitaro Uehara , Naoki Hamanaka , Toru Shonai , Tetsuhiko Okada , Masamori Kashiyama
发明人： Yuji Tsushima , Hideya Akashi , Keitaro Uehara , Naoki Hamanaka , Toru Shonai , Tetsuhiko Okada , Masamori Kashiyama
IPC分类号： G06F1200
CPC分类号： G06F12/0813 , G06F12/0817 , G06F15/177 , G06F2212/2542
摘要： In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation. On the other hand, when there is no possibility that the memory to be accessed is cached, this memory access command is transferred only to the target node in yan one-to-one correspondence.
摘要翻译：在根据其中包含多个处理器单元的多个处理器节点经由网络彼此耦合的NUMA或UMA而布置的多处理器中，结合存储器访问操作执行的高速缓存侦听操作在两个阶段即在节点内执行的本地侦听操作，以及节点之间的全局侦听操作。在执行本地侦听操作之前，向具有存储器的目标节点发出用于指定存储器的RAS的ACTV命令，并且预先激活存储器访问。另外指定存储器的CAS，并且在发出ACTV命令之后重新执行存储器访问，然后发出存储器访问命令。当存在待访问的存储器存在除了源节点之外的处理器节点的可能性时，该存储器访问命令被发布以分发给所有节点，以便执行全局侦听操作。另一方面，当不存在要访问的存储器被缓存时，该存储器访问命令仅以一对一对应的方式传送到目标节点。

5. 发明授权

US06591325B1 Method and apparatus of out-of-order transaction processing using request side queue pointer and response side queue pointer 失效
标题翻译：使用请求侧队列指针和响应端队列指针进行乱序事务处理的方法和装置
公开(公告)号：US06591325B1
公开(公告)日：2003-07-08
申请号：US09547392
申请日：2000-04-11
申请人： Hideya Akashi , Yuji Tsushima , Keitaro Uehara , Naoki Hamanaka , Toru Shonai , Tetsuhiko Okada , Masamori Kashiyama
发明人： Hideya Akashi , Yuji Tsushima , Keitaro Uehara , Naoki Hamanaka , Toru Shonai , Tetsuhiko Okada , Masamori Kashiyama
IPC分类号： G06F1314
CPC分类号： G06F13/4204
摘要： An information processing system that transfers transactions between a plurality of system modules. A request side interface unit in a request side module has a request ID queue in which issued request transactions are stored in order of issuance. A request side queue pointer points to an entry in this request ID queue corresponding to a response transaction to be accepted next. A response side interface unit in a response side module has a response queue in which accepted request transactions are stored in order of acceptance. A response side queue pointer points to an entry in this response queue corresponding to a response transaction to be issued next. Therefore, a request transaction and the corresponding response transaction are transferred between the request side interface unit and the response side interface unit without transferring transaction IDs. When the response order is changed, the response side interface unit issues a command, which changes the value of the request side queue pointer, to inform the request side interface unit of the change in the order.
摘要翻译：一种在多个系统模块之间传送交易的信息处理系统。请求侧模块中的请求侧接口单元具有请求ID队列，其中发出的请求事务按照发布的顺序存储。请求侧队列指针指向与要接受的响应事务相对应的该请求ID队列中的条目。响应侧模块中的响应侧接口单元具有响应队列，其中接受请求事务按接受顺序存储。响应侧队列指针指向对应于接下来要发出的响应事务的该响应队列中的条目。因此，在请求侧接口单元和响应侧接口单元之间传送请求事务和相应的响应事务，而不转移事务ID。当响应顺序改变时，响应侧接口单元发出改变请求侧队列指针的值的命令，以通知请求侧接口单元的顺序改变。

6. 发明授权

US06389518B1 Multiprocessor system and methods for transmitting memory access transactions for the same 有权
公开(公告)号：US06389518B1
公开(公告)日：2002-05-14
申请号：US09523737
申请日：2000-03-13
申请人： Yuji Tsushima , Hideya Akashi , Keitaro Uehara , Naoki Hamanaka , Toru Shonai , Tetsuhiko Okada , Masamori Kashiyama
发明人： Yuji Tsushima , Hideya Akashi , Keitaro Uehara , Naoki Hamanaka , Toru Shonai , Tetsuhiko Okada , Masamori Kashiyama
IPC分类号： G06F1200
摘要： In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation. On the other hand, when there is no possibility that the memory to be accessed is cached, this memory access command is transferred only to the target node in yan one-to-one correspondence.

7. 发明授权

US07890669B2 Computer system for sharing I/O device 有权
标题翻译：用于共享I / O设备的计算机系统
公开(公告)号：US07890669B2
公开(公告)日：2011-02-15
申请号：US11561557
申请日：2006-11-20
申请人： Keitaro Uehara , Yuji Tsushima , Toshiomi Moriki , Yoshiko Yasuda
发明人： Keitaro Uehara , Yuji Tsushima , Toshiomi Moriki , Yoshiko Yasuda
IPC分类号： G06F13/28
CPC分类号： G06F13/385
摘要： Provided is a computer system in which an I/O card is shared among physical servers and logical servers. Servers are set in advance such that one I/O card is used exclusively by one physical or logical server, or shared among a plurality of servers. An I/O hub allocates a virtual MM I/O address unique to each physical or logical server to a physical MM I/O address associated with each I/O card. The I/O hub keeps allocation information indicating the relation between the allocated virtual MM I/O address, the physical MM I/O address, and a server identifier unique to each physical or logical server. When a request to access an I/O card is sent from a physical or logical server, the allocation information is referred to and a server identifier is extracted from the access request. The extracted server identifier is used to identify the physical or logical server that has made the access request.
摘要翻译：提供了在物理服务器和逻辑服务器之间共享I / O卡的计算机系统。服务器预先设置，使得一个I / O卡由一个物理或逻辑服务器专门使用，或者在多个服务器之间共享。 I / O集线器将每个物理或逻辑服务器唯一的虚拟MM I / O地址分配给与每个I / O卡相关联的物理MM I / O地址。 I / O集线器保持指示分配的虚拟MM I / O地址，物理MM I / O地址与每个物理或逻辑服务器唯一的服务器标识之间的关系的分配信息。当从物理或逻辑服务器发送访问I / O卡的请求时，参考分配信息并从访问请求中提取服务器标识符。提取的服务器标识符用于标识已进行访问请求的物理或逻辑服务器。

8. 发明授权

US07313637B2 Fabric and method for sharing an I/O device among virtual machines formed in a computer system 失效
标题翻译：用于在计算机系统中形成的虚拟机之间共享I / O设备的结构和方法
公开(公告)号：US07313637B2
公开(公告)日：2007-12-25
申请号：US10727602
申请日：2003-12-05
申请人： Tsuyoshi Tanaka , Keitaro Uehara , Yuji Tsushima , Naoki Hamanaka , Daisuke Yoshida , Yoshinori Wakai
发明人： Tsuyoshi Tanaka , Keitaro Uehara , Yuji Tsushima , Naoki Hamanaka , Daisuke Yoshida , Yoshinori Wakai
IPC分类号： G06F3/00
CPC分类号： G06F9/5077 , G06F11/1484 , G06F11/2033
摘要： Disclosed herein is a computer system provided with a mechanism for connecting a single port disk to an active server and the disk to a standby server when in a fail-over processing. An “add_pci” command issued from a clustering program is used to let a control program change the allocation of a PCI slot while an interruption signal issued to a standby server permits an ACPI processing routine to hot-add a PCI card that includes the disk unit on the subject guest OS.
摘要翻译：这里公开了一种计算机系统，其具有用于在故障转移处理中将单个端口盘连接到活动服务器并且将该盘连接到备用服务器的机构。使用从聚类程序发出的“add_pci”命令使得控制程序改变PCI插槽的分配，同时发出到备用服务器的中断信号允许ACPI处理程序热插入包括盘单元的PCI卡在主题客户操作系统上。

9. 发明授权

US08078764B2 Method for switching I/O path in a computer system having an I/O switch 有权
标题翻译：用于在具有I / O开关的计算机系统中切换I / O路径的方法
公开(公告)号：US08078764B2
公开(公告)日：2011-12-13
申请号：US12222959
申请日：2008-08-20
申请人： Jun Okitsu , Yoshiko Yasuda , Takashige Baba , Keitaro Uehara , Yuji Tsushima
发明人： Jun Okitsu , Yoshiko Yasuda , Takashige Baba , Keitaro Uehara , Yuji Tsushima
IPC分类号： G06F3/00
CPC分类号： G06F9/45558 , G06F9/5088 , G06F2009/4557 , G06F2009/45579
摘要： The physical server includes a hypervisor for managing an association between the virtual server and the I/O device allocated to the virtual server. The I/O switch includes: a setting register for retaining a request to inhibit a transaction from being issued from the I/O device to the virtual server; a Tx inhibition control module for performing an inhibition of the transaction from the I/O device to the virtual server, and guaranteeing a completion of a transaction from the I/O device issued before the inhibition; a virtualization assist module for converting an address of the virtual server into an address within a memory of the physical server; and a switch management module for managing a configuration of the I/O switch.
摘要翻译：物理服务器包括用于管理虚拟服务器和分配给虚拟服务器的I / O设备之间的关联的管理程序。 I / O开关包括：设置寄存器，用于保留阻止从I / O设备发送到虚拟服务器的事务的请求; Tx禁止控制模块，用于执行从I / O设备到虚拟服务器的交易的禁止，并且保证在禁止之前发出的I / O设备完成交易; 虚拟化辅助模块，用于将虚拟服务器的地址转换成物理服务器的存储器内的地址; 以及用于管理I / O交换机的配置的交换机管理模块。

10. 发明申请

US20090198862A1 Method for switching I/O path in a computer system having an I/O switch 有权
标题翻译：用于在具有I / O开关的计算机系统中切换I / O路径的方法
公开(公告)号：US20090198862A1
公开(公告)日：2009-08-06
申请号：US12222959
申请日：2008-08-20
申请人： Jun Okitsu , Yoshiko Yasuda , Takashige Baba , Keitaro Uehara , Yuji Tsushima
发明人： Jun Okitsu , Yoshiko Yasuda , Takashige Baba , Keitaro Uehara , Yuji Tsushima
IPC分类号： G06F13/00
CPC分类号： G06F9/45558 , G06F9/5088 , G06F2009/4557 , G06F2009/45579
摘要： The physical server includes a hypervisor for managing an association between the virtual server and the I/O device allocated to the virtual server. The I/O switch includes: a setting register for retaining a request to inhibit a transaction from being issued from the I/O device to the virtual server; a Tx inhibition control module for performing an inhibition of the transaction from the I/O device to the virtual server, and guaranteeing a completion of a transaction from the I/O device issued before the inhibition; a virtualization assist module for converting an address of the virtual server into an address within a memory of the physical server; and a switch management module for managing a configuration of the I/O switch.
摘要翻译：物理服务器包括用于管理虚拟服务器和分配给虚拟服务器的I / O设备之间的关联的管理程序。 I / O开关包括：设置寄存器，用于保留阻止从I / O设备发送到虚拟服务器的事务的请求; Tx禁止控制模块，用于执行从I / O设备到虚拟服务器的交易的禁止，并且保证在禁止之前发出的I / O设备完成交易; 虚拟化辅助模块，用于将虚拟服务器的地址转换成物理服务器的存储器内的地址; 以及用于管理I / O交换机的配置的交换机管理模块。

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