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1. 发明申请

US20080098198A1 INFORMATION PROCESSING DEVICE, DATA TRANSFER METHOD, AND INFORMATION STORAGE MEDIUM 有权
标题翻译：信息处理设备，数据传输方法和信息存储介质
公开(公告)号：US20080098198A1
公开(公告)日：2008-04-24
申请号：US11834074
申请日：2007-08-06
申请人： Yuji Kawamura , Takeshi Yamazaki
发明人： Yuji Kawamura , Takeshi Yamazaki
IPC分类号： G06F12/00
CPC分类号： G06F12/1081 , G06F12/1072
摘要： The present invention has been conceived in view of the above described situation, and an object of the invention is to provide an information processing device, data transfer method and information storage medium that can commence data transfer to an I/O device immediately, and can stably exhibit data transfer performance. In an information processing device provided with hardware for sharing an address translation table, for translating logical addresses of a memory to physical addresses, between a main processor and a sub-processor, one of the sub-processors is caused to function as means for receiving a transfer request designating a logical address of the memory, means for translating the logical address that has been designated in the transfer request to a physical address using the shared address translation table, and means for executing transfer processing for data stored in the memory 14 according to the translated physical address.
摘要翻译：鉴于上述情况，本发明是考虑到的，其目的在于提供一种信息处理装置，数据传送方法和信息存储介质，可以立即开始数据传送到I / O装置，并且可以稳定展现数据传输性能。在具有用于共享地址转换表的硬件的信息处理装置中，为了将存储器的逻辑地址转换为物理地址，在主处理器和子处理器之间，使得一个子处理器用作接收装置指定存储器的逻辑地址的传送请求，用于使用共享地址转换表将已经在传送请求中指定的逻辑地址转换为物理地址的装置，以及用于对存储在存储器14中的数据执行传送处理的装置，到翻译的物理地址。

2. 发明申请

US20100058024A1 Data Transfer Apparatus, Data Transfer Method And Processor 有权
标题翻译：数据传输设备，数据传输方法和处理器
公开(公告)号：US20100058024A1
公开(公告)日：2010-03-04
申请号：US12550936
申请日：2009-08-31
申请人： Yuji Kawamura , Takeshi Yamazaki
发明人： Yuji Kawamura , Takeshi Yamazaki
IPC分类号： G06F12/02
CPC分类号： G06F12/084 , G06F9/3824 , G06F9/3885
摘要： A processor includes a CPU core which executes a user program, and a data transfer apparatus. The CPU core stores a transfer request from a user program in a specific area of a main memory, in which the transfer request specifies the virtual addresses of a transfer source and a transfer destination in a memory space allocated to the user program. The data transfer apparatus refers to the specific area of the main memory and acquires a transfer request asynchronously to processing performed by the CPU core. The data transfer apparatus then identifies physical addresses corresponding to virtual addresses specified in the transfer request. After that, the data transfer apparatus transcribes original data stored in a storage area indicated by the physical address of the transfer source, to a storage area in a cache memory related to the virtual address or physical address of the transfer destination.
摘要翻译：处理器包括执行用户程序的CPU核心和数据传送装置。 CPU核存储来自主存储器的特定区域中的用户程序的传送请求，其中传送请求在分配给用户程序的存储空间中指定传送源和传送目的地的虚拟地址。数据传送装置是指主存储器的特定区域，并且与CPU核心执行的处理异步地获取传送请求。然后，数据传送装置识别与传送请求中指定的虚拟地址对应的物理地址。之后，数据传送装置将存储在由传送源的物理地址指定的存储区域中的原始数据转录到与传送目的地的虚拟地址或物理地址相关的高速缓冲存储器中的存储区域。

3. 发明授权

US08719542B2 Data transfer apparatus, data transfer method and processor 有权
标题翻译：数据传输装置，数据传输方式和处理器
公开(公告)号：US08719542B2
公开(公告)日：2014-05-06
申请号：US12550936
申请日：2009-08-31
申请人： Yuji Kawamura , Takeshi Yamazaki
发明人： Yuji Kawamura , Takeshi Yamazaki
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F9/3824 , G06F9/3885
摘要： A processor includes a CPU core which executes a user program, and a data transfer apparatus. The CPU core stores a transfer request from a user program in a specific area of a main memory, in which the transfer request specifies the virtual addresses of a transfer source and a transfer destination in a memory space allocated to the user program. The data transfer apparatus refers to the specific area of the main memory and acquires a transfer request asynchronously to processing performed by the CPU core. The data transfer apparatus then identifies physical addresses corresponding to virtual addresses specified in the transfer request. After that, the data transfer apparatus transcribes original data stored in a storage area indicated by the physical address of the transfer source, to a storage area in a cache memory related to the virtual address or physical address of the transfer destination.
摘要翻译：处理器包括执行用户程序的CPU核心和数据传送装置。 CPU核存储来自主存储器的特定区域中的用户程序的传送请求，其中传送请求在分配给用户程序的存储空间中指定传送源和传送目的地的虚拟地址。数据传送装置是指主存储器的特定区域，并且与CPU核心执行的处理异步地获取传送请求。然后，数据传送装置识别与传送请求中指定的虚拟地址对应的物理地址。之后，数据传送装置将存储在由传送源的物理地址指定的存储区域中的原始数据转录到与传送目的地的虚拟地址或物理地址相关的高速缓冲存储器中的存储区域。

4. 发明授权

US07913059B2 Information processing device, data transfer method, and information storage medium 有权
标题翻译：信息处理装置，数据传送方法和信息存储介质
公开(公告)号：US07913059B2
公开(公告)日：2011-03-22
申请号：US11834074
申请日：2007-08-06
申请人： Yuji Kawamura , Takeshi Yamazaki
发明人： Yuji Kawamura , Takeshi Yamazaki
IPC分类号： G06F12/00
CPC分类号： G06F12/1081 , G06F12/1072
摘要： The present invention has been conceived in view of the above described situation, and an object of the invention is to provide an information processing device, data transfer method and information storage medium that can commence data transfer to an I/O device immediately, and can stably exhibit data transfer performance. In an information processing device provided with hardware for sharing an address translation table, for translating logical addresses of a memory to physical addresses, between a main processor and a sub-processor, one of the sub-processors is caused to function as means for receiving a transfer request designating a logical address of the memory, means for translating the logical address that has been designated in the transfer request to a physical address using the shared address translation table, and means for executing transfer processing for data stored in the memory 14 according to the translated physical address.
摘要翻译：鉴于上述情况，本发明是考虑到的，其目的在于提供一种信息处理装置，数据传送方法和信息存储介质，可以立即开始数据传送到I / O装置，并且可以稳定展现数据传输性能。在具有用于共享地址转换表的硬件的信息处理装置中，为了将存储器的逻辑地址转换为物理地址，在主处理器和子处理器之间，使得一个子处理器用作接收装置指定存储器的逻辑地址的传送请求，用于使用共享地址转换表将已经在传送请求中指定的逻辑地址转换为物理地址的装置，以及用于对存储在存储器14中的数据执行传送处理的装置，到翻译的物理地址。

5. 发明授权

US08996440B2 Information processing apparatus, information processing method, and program 有权
标题翻译：信息处理装置，信息处理方法和程序
公开(公告)号：US08996440B2
公开(公告)日：2015-03-31
申请号：US13474159
申请日：2012-05-17
申请人： Takeshi Yamazaki , Seiji Wada , Yoshihiro Wakita , Koji Kashima , Natsuki Kimura
发明人： Takeshi Yamazaki , Seiji Wada , Yoshihiro Wakita , Koji Kashima , Natsuki Kimura
IPC分类号： G06N5/02 , G06Q10/10
CPC分类号： G06Q10/109
摘要： An information processing apparatus configured to create a schedule to be presented to a user includes an estimation unit and a creation unit. The estimation unit is configured to estimate whether or not the user acts in accordance with a first schedule including a task to do for accomplishing a preset aim. The creation unit is configured to create, when estimated that the user does not act in accordance with the first schedule, a new second schedule for accomplishing the aim from a state of the user who acts without following the first schedule.
摘要翻译：被配置为创建要呈现给用户的日程表的信息处理设备包括估计单元和创建单元。估计单元被配置为估计用户是否根据包括要完成预设目标的任务的第一调度进行动作。创建单元被配置为当估计用户不按照第一时间表行动时创建新的第二计划，用于从不遵循第一进度的行为的用户的状态完成目标。

6. 发明授权

US08774895B2 Electroencephalographic headset 有权
标题翻译：脑电耳机
公开(公告)号：US08774895B2
公开(公告)日：2014-07-08
申请号：US13616185
申请日：2012-09-14
申请人： Seiji Wada , Takeshi Yamazaki , Natsuki Kimura , Yoshihiro Wakita , Koji Kashima , Tomiji Tanaka , Mitsuhiro Nakamura , Tatsumi Sakaguchi , Haruhiko Soma , Takuro Yamamoto
发明人： Seiji Wada , Takeshi Yamazaki , Natsuki Kimura , Yoshihiro Wakita , Koji Kashima , Tomiji Tanaka , Mitsuhiro Nakamura , Tatsumi Sakaguchi , Haruhiko Soma , Takuro Yamamoto
IPC分类号： A61B5/0478 , A61B5/00
CPC分类号： A61B5/0478 , A61B5/6803 , A61B5/6814 , A61B5/6843
摘要： An electroencephalographic headset includes: a supporter that includes expanding and contracting wires each having expansion and contraction properties and is to be attached to a head of a user by expansion and contraction of each of the expanding and contracting wires; and a plurality of electrodes that are provided to the supporter in defined placement.
摘要翻译：脑电耳机包括：支撑件，其包括每个具有伸缩性能的伸缩线，并且通过每个伸缩线的伸缩来附接到使用者的头部; 以及以规定的位置设置在支撑体上的多个电极。

7. 发明授权

US08761554B2 Wavelength selective switch 有权
标题翻译：波长选择开关
公开(公告)号：US08761554B2
公开(公告)日：2014-06-24
申请号：US13419646
申请日：2012-03-14
申请人： Koji Matsumoto , Satoshi Watanabe , Toshiro Okamura , Takeshi Yamazaki
发明人： Koji Matsumoto , Satoshi Watanabe , Toshiro Okamura , Takeshi Yamazaki
IPC分类号： G02B6/26 , G02B6/42
CPC分类号： G02B6/3518 , G02B6/3534
摘要： Provided is a wavelength selective switch, which includes: an input/output unit; a dispersive portion; a condensing optical system; and the deflection portion. The input/output unit has input/output ports. The dispersive portion disperses signal light incident from the input/output ports. The condensing optical system condenses a plurality of signal light beams dispersed by the dispersive portion. The deflection portion has a plurality of deflection elements. The deflection elements deflect, along a second direction, the signal light beams condensed by the condensing optical system. In the condensing optical system, the aberration amount of the meridional component in a sagittal coma aberration remains substantially constant irrespective of an angle formed between the optical axis of the condensing optical system and a signal light beam incident on the condensing optical system from the input/output portion, at an incident position of the incident signal light beam at a certain height in the second direction.
摘要翻译：提供一种波长选择开关，其包括：输入/输出单元; 分散部分; 聚光光学系统; 和偏转部。输入/输出单元具有输入/输出端口。色散部分分散从输入/输出端口入射的信号光。聚光光学系统凝聚由分散部分散射的多个信号光束。偏转部分具有多个偏转元件。偏转元件沿着第二方向偏转由聚光光学系统会聚的信号光束。在聚光光学系统中，与聚光光学系统的光轴和入射到聚光光学系统的信号光束之间的角度不同，矢状彗差中的子午分量的像差量保持基本恒定，在入射信号光束的入射位置处，在第二方向上处于一定高度。

8. 发明申请

US20120310873A1 INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM 有权
标题翻译：信息处理设备，信息处理方法和程序
公开(公告)号：US20120310873A1
公开(公告)日：2012-12-06
申请号：US13474159
申请日：2012-05-17
申请人： Takeshi Yamazaki , Seiji Wada , Yoshihiro Wakita , Koji Kashima , Natsuki Kimura
发明人： Takeshi Yamazaki , Seiji Wada , Yoshihiro Wakita , Koji Kashima , Natsuki Kimura
IPC分类号： G06N5/02
CPC分类号： G06Q10/109
摘要： An information processing apparatus configured to create a schedule to be presented to a user includes an estimation unit and a creation unit. The estimation unit is configured to estimate whether or not the user acts in accordance with a first schedule including a task to do for accomplishing a preset aim. The creation unit is configured to create, when estimated that the user does not act in accordance with the first schedule, a new second schedule for accomplishing the aim from a state of the user who acts without following the first schedule.
摘要翻译：被配置为创建要呈现给用户的日程表的信息处理设备包括估计单元和创建单元。估计单元被配置为估计用户是否根据包括要完成预设目标的任务的第一调度进行动作。创建单元被配置为当估计用户不按照第一时间表行动时创建新的第二计划，用于从不遵循第一进度的行为的用户的状态完成目标。

9. 发明申请

US20120111550A1 EBULLIENT COOLING DEVICE 审中-公开
标题翻译： EBULLI冷却装置
公开(公告)号：US20120111550A1
公开(公告)日：2012-05-10
申请号：US13254680
申请日：2010-03-09
申请人： Hiromichi Kuno , Yasuji Taketsuna , Mikio Shirai , Hideo Nakamura , Takeshi Yamazaki , Haruhiko Ohta , Yasuhisa Shinmoto , Koichi Suzuki , Yoshiyuki Abe , Osamu Kawanami
发明人： Hiromichi Kuno , Yasuji Taketsuna , Mikio Shirai , Hideo Nakamura , Takeshi Yamazaki , Haruhiko Ohta , Yasuhisa Shinmoto , Koichi Suzuki , Yoshiyuki Abe , Osamu Kawanami
IPC分类号： F28F1/10
CPC分类号： H01L23/427 , F28D15/0266 , F28F3/12 , H01L2924/0002 , H05K7/20936 , H01L2924/00
摘要： An ebullient cooling device having a simple structure and capable of limiting the bubbles to an appropriate volume. The ebullient cooling device for cooling a heat generating element is provided with a plurality of vertically arranged cooling channels comprising a lower channel (2), a middle channel (3) and un upper channel (4). Each cooling channel has cooling fins (12) for guiding a refrigerant to flow in a vertical direction, and a vapor discharge path (16) formed at the side of the cooling fins (12) that is opposite the side in contact with the heat generating element. Furthermore, flow path partition/vapor discharge guiding plates (18) are provided between the cooling channels so that the bubbles that have been generated are guided to the vapor discharge path (16) and prevented from moving into the subsequent cooling channel.
摘要翻译：一种沸腾冷却装置，具有简单的结构并且能够将气泡限制到适当的体积。用于冷却发热元件的沸腾冷却装置设置有多个垂直布置的冷却通道，其包括下通道（2），中间通道（3）和非上通道（4）。每个冷却通道具有用于引导制冷剂沿垂直方向流动的冷却片（12）和形成在与发热量接触的一侧相反的散热片（12）侧的蒸汽排出通道（16）元件。此外，在冷却通道之间设置有流路分隔/蒸汽排出引导板（18），使得已经产生的气泡被引导到蒸气排放路径（16）并阻止其进入随后的冷却通道。

10. 发明授权

US08032849B2 Integrated circuit chip with modular design 失效
标题翻译：集成电路芯片采用模块化设计
公开(公告)号：US08032849B2
公开(公告)日：2011-10-04
申请号：US12130268
申请日：2008-05-30
申请人： Harm Peter Hofstee , James Allan Kahle , Takeshi Yamazaki
发明人： Harm Peter Hofstee , James Allan Kahle , Takeshi Yamazaki
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Disclosed is a procedure or design approach for functional modules that may be used in connection with a multiprocessor integrated circuit chip. The approach includes keeping the dimensions of each module substantially the same and having the bus, power, clock and I/O connection configured the same on all modules. Further requirements for ease of use are to generalize the capability of each module as much as possible and to decentralize functions such as testing to be primarily performed within each module. The use of such considerations or rules substantially eases the design of a given type of custom chips, and based upon an initial chip design greatly facilitates the design of further custom chips, similar in application, but subsequent to the successful completion of the initial chip. The standardization modules and replication of the modules on a given chip also reduces physical verification time in initial chip design as well as redesign time of the initial chip when requirements for chip capability are redefined or otherwise changed. Any subsequent or further custom chips can include more or less of specific modules based upon already established parameters.
摘要翻译：公开了可以与多处理器集成电路芯片结合使用的功能模块的过程或设计方法。该方法包括保持每个模块的尺寸基本相同，并使总线，电源，时钟和I / O连接在所有模块上配置相同。对易用性的进一步要求是尽可能地推广每个模块的能力，并将诸如测试之类的功能分散在每个模块内主要执行。这种考虑或规则的使用大大简化了给定类型的定制芯片的设计，并且基于初始的芯片设计极大地促进了其他定制芯片的设计，其应用类似，但是在初始芯片的成功完成之后。给定芯片上的标准化模块和模块的复制也减少了初始芯片设计中的物理验证时间，以及在重新定义或改变芯片能力要求时初始芯片的重新设计时间。任何后续或进一步的定制芯片可以基于已经建立的参数包括或多或少的特定模块。

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