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1. 发明授权

US6051451A Heavy ion implant process to eliminate polystringers in high density type flash memory devices 失效
标题翻译：重离子注入工艺，消除高密度型闪存器件中的多吸收器
公开(公告)号：US6051451A
公开(公告)日：2000-04-18
申请号：US64041
申请日：1998-04-21
申请人： Yue-song He , Yowjuang William Liu
发明人： Yue-song He , Yowjuang William Liu
IPC分类号： H01L21/3213 , H01L21/8247 , H01L21/335 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/32137
摘要： A method for fabricating a memory device is provided. A first polysilicon (poly I) layer is formed over a substrate. Poly I isolation rows are etched into the poly I layer so as to form electrically isolated poly I lines. An oxide-nitride-oxide (ONO) layer is formed over the poly I lines and field oxide portions exposed via the poly I isolation rows. A second polysilicon (poly II) layer is formed over the ONO layer. Poly II isolation rows are etched into the poly II layer so as to form electrically isolated poly II lines, the poly II isolation rows being perpendicular in direction to the poly I isolation rows, the poly II isolation rows exposing portions of the ONO layer. Heavy ions are implanted into portions of the poly I layer via the exposed portions of the ONO layer, wherein the heavy ions disrupt silicon bonds of the poly I layer portions. The exposed portions of the ONO layer and the poly I layer portions are substantially etched away.
摘要翻译：提供了一种用于制造存储器件的方法。在衬底上形成第一多晶硅（poly I）层。 Poly I隔离行被蚀刻到poly I层中，以形成电隔离的poly I线。在通过聚I隔离行暴露的多晶I线和场氧化物部分上形成氧化物 - 氧化物 - 氧化物（ONO）层。在ONO层上形成第二多晶硅（poly II）层。 Poly II隔离行被蚀刻到聚II层中，以便形成电隔离的聚II线，所述聚II隔离行在多I隔离行的方向上垂直，所述聚II隔离行暴露ONO层的部分。重离子经由ONO层的暴露部分注入到多晶硅层的一部分中，其中重离子破坏多层I层部分的硅键。 ONO层和多层I层部分的露出部分被基本蚀刻掉。

2. 发明授权

US06284602B1 Process to reduce post cycling program VT dispersion for NAND flash memory devices 有权
标题翻译：用于减少NAND闪存器件的后循环程序VT色散的过程
公开(公告)号：US06284602B1
公开(公告)日：2001-09-04
申请号：US09399526
申请日：1999-09-20
申请人： Yue-song He , Kent K. Chang , Allen U. Huang
发明人： Yue-song He , Kent K. Chang , Allen U. Huang
IPC分类号： H01L218247
CPC分类号： H01L27/11526 , H01L27/11529 , Y10S438/981
摘要： In one embodiment, the present invention relates to a method of forming a NAND type flash memory device involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; annealing the first oxide layer and the second oxide layer under an inert gas and at least one of N2O and NO for a period of time from about 1 minute to about 15 minutes; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first in situ doped amorphous silicon layer having a thickness from about 400 Å to about 1,000 Å; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; and forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer, and the select gate transistor comprising the first oxide layer, the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer.
摘要翻译：在一个实施例中，本发明涉及一种形成NAND型闪速存储器件的方法，该器件包括以下步骤：在衬底的至少一部分上生长第一氧化物层，所述衬底包括闪存单元区域和选择栅极区域 ; 去除衬底的闪存单元区域中的第一氧化物层的一部分; 在所述闪存单元区域中的所述衬底的至少一部分上以及所述选择栅极区域中的所述第一氧化物层的至少一部分上生长第二氧化物层; 在惰性气体和N 2 O和NO中的至少一种下将第一氧化物层和第二氧化物层退火约1分钟至约15分钟的时间; 在所述第二氧化物层的至少一部分上沉积第一原位掺杂的非晶硅层，所述第一原位掺杂的非晶硅层具有从约至在的厚度; 在第一原位掺杂的非晶硅层的至少一部分上沉积介电层; 在所述电介质层的至少一部分上沉积第二掺杂非晶硅层; 以及在所述衬底的所述闪存单元区域中形成快闪存储器单元，以及在所述选择栅极区域衬底中形成选择栅极晶体管，所述闪存单元包括所述第二氧化物层，所述第一原位掺杂非晶硅层，所述介电层，和第二掺杂非晶硅层，选择栅极晶体管包括第一氧化物层，第二氧化物层，第一原位掺杂非晶硅层，电介质层和第二掺杂非晶硅层。

3. 发明授权

US06524914B1 Source side boron implanting and diffusing device architecture for deep sub 0.18 micron flash memory 有权
标题翻译：源极硼注入和扩散器件架构，用于深亚0.18微米闪存
公开(公告)号：US06524914B1
公开(公告)日：2003-02-25
申请号：US09699972
申请日：2000-10-30
申请人： Yue-song He , Sameer Haddad , Timothy Thurgate , Chi Chang
发明人： Yue-song He , Sameer Haddad , Timothy Thurgate , Chi Chang
IPC分类号： H01L218247
CPC分类号： H01L29/66825 , H01L29/66833
摘要： One aspect of the present invention relates to a method of making a flash memory cell involving the steps of providing a substrate having a flash memory cell thereon; forming a self-aligned source mask over the substrate, the self aligned source mask having openings corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings in the self-aligned source mask corresponding to source lines; removing the self-aligned source mask from the substrate; cleaning the substrate; and implanting a medium dosage drain implant of a second type to form a source region and a drain region in the substrate adjacent the flash memory cell.
摘要翻译：本发明的一个方面涉及一种制造闪存单元的方法，所述闪存单元包括以下步骤：提供其上具有闪存单元的基板; 在衬底上形成自对准源掩模，所述自对准源掩模具有对应于源极线的开口; 通过对应于源极线的自对准源掩模中的开口将衬底中的第一类型源掺杂剂注入到衬底中; 从衬底去除自对准源掩模; 清洗基材; 以及植入第二类型的介质剂量漏极注入以在所述衬底中邻近所述闪存单元形成源极区域和漏极区域。

4. 发明授权

US06653189B1 Source side boron implant and drain side MDD implant for deep sub 0.18 micron flash memory 有权
标题翻译：源极硼注入和漏极侧MDD植入物用于深亚0.18微米闪存
公开(公告)号：US06653189B1
公开(公告)日：2003-11-25
申请号：US09699711
申请日：2000-10-30
申请人： Sameer Haddad , Yue-song He , Timothy Thurgate , Chi Chang , Mark W. Randolph , Ngaching Wong
发明人： Sameer Haddad , Yue-song He , Timothy Thurgate , Chi Chang , Mark W. Randolph , Ngaching Wong
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L29/66833
摘要： One aspect of the present invention relates to a method of making a flash memory cell, involving the steps of providing a substrate having a flash memory cell thereon; forming a self-aligned source mask over the substrate, the self aligned source mask having openings corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings in the self-aligned source mask corresponding to source lines; removing the self-aligned source mask from the substrate; forming a MDD mask over the substrate, the MDD mask covering the source lines and having openings corresponding to drain lines; and implanting a medium dosage drain implant of a second type to form a drain region in the substrate adjacent the flash memory cell.
摘要翻译：本发明的一个方面涉及一种制造闪存单元的方法，包括以下步骤：在其上提供闪存单元; 在衬底上形成自对准源掩模，所述自对准源掩模具有对应于源极线的开口; 通过对应于源极线的自对准源掩模中的开口将衬底中的第一类型源掺杂剂注入到衬底中; 从衬底去除自对准源掩模; 在衬底上形成MDD掩模，MDD掩模覆盖源极线并具有对应于漏极线的开口; 以及植入第二类型的介质剂量漏极注入，以在与所述闪存单元相邻的所述衬底中形成漏极区域。

5. 发明授权

US06716698B1 Virtual ground silicide bit line process for floating gate flash memory 有权
标题翻译：用于浮动栅极闪存的虚拟接地硅化物位线工艺
公开(公告)号：US06716698B1
公开(公告)日：2004-04-06
申请号：US10238412
申请日：2002-09-10
申请人： Yue-song He , Richard Fastow , Wei Zheng
发明人： Yue-song He , Richard Fastow , Wei Zheng
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521
摘要： One aspect of the invention relates to a virtual ground array floating gate flash memory device with salicided buried bit lines. The bit lines are implanted and salicided after formation of memory cell stacks, but before formation of word lines. The salicide can form over control gates for the memory cells and can contact a third poly layer from which the word lines are patterned. According to another aspect of the invention, an interpoly dielectric coats the sides of the floating gates and significantly improves the capacitance between the floating gate and the memory cell channel. The present invention provides very compact and reliable non-volatile memory.
摘要翻译：本发明的一个方面涉及具有含水埋地位线的虚拟接地阵列浮栅器件闪存器件。位线在形成记忆单元堆之后，但在形成字线之前被植入和浸渍。可以在存储器单元的控制栅上形成自对准硅化物，并且可以接触图形化字线的第三多晶硅层。根据本发明的另一方面，间隔电介质涂覆浮置栅极的侧面并且显着地改善了浮动栅极和存储器单元通道之间的电容。本发明提供非常紧凑和可靠的非易失性存储器。

6. 发明授权

US06570211B1 2Bit/cell architecture for floating gate flash memory product and associated method 有权
标题翻译： 2Bit /单元架构的浮栅闪存产品及相关方法
公开(公告)号：US06570211B1
公开(公告)日：2003-05-27
申请号：US10180673
申请日：2002-06-26
申请人： Yue-song He , Richard Fastow , Zheng Wei
发明人： Yue-song He , Richard Fastow , Zheng Wei
IPC分类号： H01L2976
CPC分类号： H01L27/11568 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/511
摘要： The invention relates to a flash memory devices and a method associated therewith in which combined source/drain regions are shared by more than two memory cells. For example, source/drain regions can be shared by four adjacent memory cells. Such sharing can be accomplished by providing memory cells along main branches of word lines and additional memory cells along dead end branches extending off the main branches. Another aspect of the invention relates to a flash memory device wherein the memory cells are arrayed and a first portion of the memory cells are read with source and drain regions sharing a row of the array and a second portion of the memory cells are read with source and drain regions sharing a column of the array.
摘要翻译：本发明涉及一种闪存器件及其相关方法，其中组合的源/漏区由两个以上的存储单元共享。例如，源/漏区可由四个相邻的存储单元共享。这样的共享可以通过沿着主线的主分支提供存储器单元并且沿着从主分支延伸的死端分支的附加存储器单元来实现。本发明的另一方面涉及一种闪速存储器件，其中存储器单元被排列并且存储单元的第一部分被读取，源区和漏区共享阵列的一行，并且存储单元的第二部分被读取并且漏极区域共享阵列的列。

7. 发明授权

US06888157B1 N-Gate/N-Substrate or P-Gate/P-Substrate capacitor to characterize polysilicon gate depletion evaluation 有权
标题翻译： N栅极/ N基板或P栅极/ P基板电容器来表征多晶硅栅极耗尽评估
公开(公告)号：US06888157B1
公开(公告)日：2005-05-03
申请号：US09917440
申请日：2001-07-27
申请人： Zhigang Wang , Nian Yang , Yue-song He
发明人： Zhigang Wang , Nian Yang , Yue-song He
IPC分类号： H01L23/544 , H01L23/58
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure for characterizing polysilicon gate depletion effects of a particular semiconductor fabrication process. In one embodiment, an N-Gate/N-Substrate capacitor is fabricated with the semiconductor fabrication process which is being evaluated for its polysilicon gate depletion effects. The N-gate of capacitor structure is driven to depletion while the N-substrate is simultaneously driven to accumulation. Capacitance-voltage measurements are taken. Based on these CV measurements, the polysilicon depletion effects are then obtained for that particular semiconductor fabrication process. In another embodiment, a P-Gate/P-Substrate capacitor is fabricated with the semiconductor fabrication process. The gate of the P-Gate/P-Substrate capacitor is driven to depletion while the substrate is simultaneously driven to accumulation. Based on the CV measurements performed on the P-Gate/P-Substrate capacitor, the polysilicon depletion effects can be obtained for that particular semiconductor fabrication process. In a third embodiment, a capacitor structure device is used to evaluate the polysilicon gate depletion effects of a semiconductor fabrication process. Different voltages are selectively applied to the gate of either an N-Gate/N-Substrate capacitor or a P-Gate/P-Substrate capacitor while its capacitance is measured. Based on the CV measurements, the polysilicon gate depletion effects for that particular semiconductor fabrication process is characterized.
摘要翻译：用于表征特定半导体制造工艺的多晶硅栅极耗尽效应的电容器结构。在一个实施例中，通过正在评估其多晶硅栅极耗尽效应的半导体制造工艺来制造N栅极/ N-衬底电容器。驱动电容器结构的N栅极耗尽，同时驱动N衬底进行积累。进行电容电压测量。基于这些CV测量，然后获得针对该特定半导体制造工艺的多晶硅耗尽效应。在另一个实施例中，通过半导体制造工艺制造P栅极/ P-基板电容器。 P栅极/ P基板电容器的栅极被驱动为耗尽，同时基板同时被驱动以累积。基于在P型栅极/ P-基板电容器上执行的CV测量，可以获得针对该特定半导体制造工艺的多晶硅耗尽效应。在第三实施例中，使用电容器结构器件来评估半导体制造工艺的多晶硅栅极耗尽效应。在测量其电容时，不同的电压选择性地施加到N栅极/ N基板电容器或P栅极/ P基板电容器的栅极。基于CV测量，对该特定半导体制造工艺的多晶硅栅极耗尽效应进行了表征。

8. 发明授权

US06436778B1 Re-oxidation approach to improve peripheral gate oxide integrity in a tunnel nitride oxidation process 有权
标题翻译：再氧化方法提高隧道氮化物氧化工艺中的外围栅极氧化物完整性
公开(公告)号：US06436778B1
公开(公告)日：2002-08-20
申请号：US09879738
申请日：2001-06-12
申请人： Hao Fang , Yue-song He
发明人： Hao Fang , Yue-song He
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/11536
摘要： A process for fabricating a semiconductor device 20 that includes providing semiconductor substrate 28 having a core region 24 and a peripheral gate region 26. The semiconductor substrate 28 has at least one shallow trench isolation region 30 and at least one nitrogen-contaminated region 36 in the peripheral gate region 26. A tunnel oxide layer 34 overlies the semiconductor substrate 28 and a first polysilicon layer 38 overlies the tunnel oxide layer 34 in the core region 24. An ONO layer 40 overlies the first polysilicon layer 38 in the core region 24. The process further includes growing a sacrificial oxide layer 42 overlying the nitrogen-contaminated region 36 in the peripheral gate region 26, wherein oxygen from within the sacrificial oxide layer 42 diffuses into the nitrogen-contaminated region 36 and forms silicon dioxide. By allowing oxygen from within the sacrificial oxide layer 42 to diffuse into the nitrogen-contaminated region 36 and form silicon dioxide, the nitrogen 56 can be removed from within the semiconductor substrate 28 by removing the silicon dioxide.
摘要翻译：一种制造半导体器件20的方法，其包括提供具有芯区24和外围栅区26的半导体衬底28.半导体衬底28具有至少一个浅沟槽隔离区30和至少一个氮污染区36 隧道氧化物层34覆盖在半导体衬底28上，并且第一多晶硅层38覆盖在芯区域24中的隧道氧化物层34上.OOO层40覆盖在核心区域24中的第一多晶硅层38上。工艺还包括在外围栅极区域26中生长覆盖氮污染区域36的牺牲氧化物层42，其中来自牺牲氧化物层42内的氧气扩散到氮污染区域36中并形成二氧化硅。通过允许牺牲氧化物层42内的氧气扩散到氮污染区域36中并形成二氧化硅，可以通过去除二氧化硅从半导体衬底28内去除氮56。

9. 发明授权

US06380033B1 Process to improve read disturb for NAND flash memory devices 有权
标题翻译：改善NAND闪存设备读取干扰的过程
公开(公告)号：US06380033B1
公开(公告)日：2002-04-30
申请号：US09399414
申请日：1999-09-20
申请人： Yue-song He , Kent K. Chang , Allen U. Huang
发明人： Yue-song He , Kent K. Chang , Allen U. Huang
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11531
摘要： In one embodiment, the present invention relates to a method of forming a NAND type flash memory device capable of more than about 1×105 program/erase cycles without significant read disturb problems involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; annealing the first oxide layer and the second oxide layer under an inert gas and at least one of N2O and NO for a period of time from about 1 minute to about 15 minutes; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; and forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer, and the select gate transistor comprising the first oxide layer, the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer.
摘要翻译：在一个实施例中，本发明涉及一种形成能够超过大约1×10 5个编程/擦除周期的NAND型闪速存储器件的方法，而没有显着的读取干扰问题，涉及以下步骤：在第一氧化物层的至少一部分上生长第一氧化物层衬底，所述衬底包括闪存单元区域和选择栅极区域; 去除衬底的闪存单元区域中的第一氧化物层的一部分; 在所述闪存单元区域中的所述衬底的至少一部分上以及所述选择栅极区域中的所述第一氧化物层的至少一部分上生长第二氧化物层; 在惰性气体和N 2 O和NO中的至少一种下将第一氧化物层和第二氧化物层退火约1分钟至约15分钟的时间; 在所述第二氧化物层的至少一部分上沉积第一原位掺杂的非晶硅层; 在第一原位掺杂的非晶硅层的至少一部分上沉积介电层; 在所述电介质层的至少一部分上沉积第二掺杂非晶硅层; 以及在所述衬底的所述闪存单元区域中形成快闪存储器单元，以及在所述选择栅极区域衬底中形成选择栅极晶体管，所述闪存单元包括所述第二氧化物层，所述第一原位掺杂非晶硅层，所述介电层，和第二掺杂非晶硅层，选择栅极晶体管包括第一氧化物层，第二氧化物层，第一原位掺杂非晶硅层，电介质层和第二掺杂非晶硅层。

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