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1. 发明申请

US20130029451A1 METHOD FOR MAKING A SOLAR CELL 审中-公开
标题翻译：制造太阳能电池的方法
公开(公告)号：US20130029451A1
公开(公告)日：2013-01-31
申请号：US13355822
申请日：2012-01-23
申请人： Yu-Lun Chueh , Chin-Hung Liu , Chih-Huang Lai
发明人： Yu-Lun Chueh , Chin-Hung Liu , Chih-Huang Lai
IPC分类号： H01L31/0272 , H01L31/0264
CPC分类号： H01L31/0322 , H01L31/02363 , H01L31/0749 , Y02E10/541 , Y02P70/521
摘要： A method for making a solar cell includes: (a) forming over a substrate a photoelectric transformation layer that is made of a chalcopyrite-based photovoltaic material; (b) performing an ion milling treatment, in which ions are injected to an upper surface of the photoelectric transformation layer at an ion incident angle with respect to the upper surface to partially etch the photoelectric transformation layer, so that the photoelectric transformation layer is formed with a plurality of nano-pillar structures, the ion incident angle ranging from 0° to 90°; and (c) forming an electrode unit to transmit electricity from the photoelectric transformation layer.
摘要翻译：制造太阳能电池的方法包括：（a）在基板上形成由基于黄铜矿的光伏材料制成的光电转换层; （b）进行离子研磨处理，其中离子以相对于上表面的离子入射角注入光电转换层的上表面以部分蚀刻光电转换层，从而形成光电转换层具有多个纳米柱结构，离子入射角为0°至90°; 和（c）形成电极单元以从光电转换层传输电能。

2. 发明授权

US07244975B2 High-voltage device structure 有权
标题翻译：高压器件结构
公开(公告)号：US07244975B2
公开(公告)日：2007-07-17
申请号：US11160657
申请日：2005-07-05
申请人： Anchor Chen , Chih-Hung Lin , Hwi-Huang Chen , Jih-Wei Liou , Chin-Hung Liu , Ming-Tsung Tung , Chien-Ming Lin , Jung-Ching Chen
发明人： Anchor Chen , Chih-Hung Lin , Hwi-Huang Chen , Jih-Wei Liou , Chin-Hung Liu , Ming-Tsung Tung , Chien-Ming Lin , Jung-Ching Chen
IPC分类号： H01L27/10 , H01L29/739 , H01L29/73 , H01L29/76 , H01L29/94
CPC分类号： H01L29/0692 , H01L29/0638 , H01L29/1041 , H01L29/7833
摘要： A high-voltage device structure includes a high-voltage device disposed on a semiconductor substrate. The semiconductor includes an active region and an isolation region, and the high-voltage device is disposed in the active region. The high-voltage device structure includes a source diffusion region of a first conductive type, a drain region of the first conductive type, and a gate longer than the source diffusion region and the drain diffusion region so as to form spare regions on both sides of the gate. The isolation region is outside the active region and surrounds the active region. In the isolation region, an isolation ion implantation region of a second conductive type and an extended ion implantation region are disposed to prevent parasitic current from being generating between the source diffusion region and the drain diffusion region.
摘要翻译：高压器件结构包括设置在半导体衬底上的高电压器件。半导体包括有源区和隔离区，高压器件设置在有源区中。高电压器件结构包括第一导电类型的源极扩散区域，第一导电类型的漏极区域和比源极扩散区域和漏极扩散区域更长的栅极，以在第二导电类型的两侧形成备用区域大门。隔离区域在有源区域之外并且围绕有源区域。在隔离区域中，设置第二导电型隔离离子注入区域和延伸离子注入区域，以防止在源极扩散区域和漏极扩散区域之间产生寄生电流。

3. 发明授权

US07560774B1 IC chip 有权
标题翻译： IC芯片
公开(公告)号：US07560774B1
公开(公告)日：2009-07-14
申请号：US12018638
申请日：2008-01-23
申请人： Chin-Hung Liu , Chin-Lung Chen , Ming-Tsung Tung , Wen-Kuo Li
发明人： Chin-Hung Liu , Chin-Lung Chen , Ming-Tsung Tung , Wen-Kuo Li
IPC分类号： H01L29/76
CPC分类号： H01L27/088 , H01L21/823418 , H01L27/0207 , H01L29/0653 , H01L29/0696 , H01L29/086 , H01L29/0878 , H01L29/4238 , H01L29/7816
摘要： An IC chip, including a switch LDMOS device and an analog LDMOS device, is configured on a substrate having a first conductive type. Components of the two LDMOS devices respectively include two gate conductive layers configured on two first active regions of the substrate. A common source contact region having a second conductive type is configured in a second active region, which is configured between the two first active regions. An isolation structure is included for isolating the second active region and the first active regions. The isolation structure between the first active regions and the second active region has a length “A” extending along a longitudinal direction of a channel under each gate conductive layer, and each gate conductive layer on each first active region has a length “L” extending along the longitudinal direction of the channel, the two LDMOS devices have different A/L values.
摘要翻译：包括开关LDMOS器件和模拟LDMOS器件的IC芯片配置在具有第一导电类型的衬底上。两个LDMOS器件的组件分别包括配置在衬底的两个第一有源区上的两个栅极导电层。具有第二导电类型的公共源极接触区域被配置在第二有源区域中，第二有源区域被配置在两个第一有源区域之间。包括用于隔离第二有源区和第一有源区的隔离结构。第一有源区和第二有源区之间的隔离结构具有沿着每个栅极导电层下方的沟道的纵向方向延伸的长度“A”，并且每个第一有源区上的每个栅极导电层具有长度“L” 沿着通道的纵向方向，两个LDMOS器件具有不同的A / L值。

4. 发明申请

US20070018258A1 High-Voltage Device Structure 有权
标题翻译：高压器件结构
公开(公告)号：US20070018258A1
公开(公告)日：2007-01-25
申请号：US11160657
申请日：2005-07-05
申请人： Anchor Chen , Chih-Hung Lin , Hwi-Huang Chen , Jih-Wei Liou , Chin-Hung Liu , Ming-Tsung Tung , Chien-Ming Lin , Jung-Ching CHEN
发明人： Anchor Chen , Chih-Hung Lin , Hwi-Huang Chen , Jih-Wei Liou , Chin-Hung Liu , Ming-Tsung Tung , Chien-Ming Lin , Jung-Ching CHEN
IPC分类号： H01L29/76
CPC分类号： H01L29/0692 , H01L29/0638 , H01L29/1041 , H01L29/7833
摘要： A high-voltage device structure includes a high-voltage device disposed on a semiconductor substrate. The semiconductor includes an active region and an isolation region, and the high-voltage device is disposed in the active region. The high-voltage device structure includes a source diffusion region of a first conductive type, a drain region of the first conductive type, and a gate longer than the source diffusion region and the drain diffusion region so as to form spare regions on both sides of the gate. The isolation region is outside the active region and surrounds the active region. In the isolation region, an isolation ion implantation region of a second conductive type and an extended ion implantation region are disposed to prevent parasitic current from being generating between the source diffusion region and the drain diffusion region.
摘要翻译：高压器件结构包括设置在半导体衬底上的高电压器件。半导体包括有源区和隔离区，高压器件设置在有源区中。高压器件结构包括第一导电类型的源极扩散区域，第一导电类型的漏极区域和比源极扩散区域和漏极扩散区域更长的栅极，以在第二导电类型的两侧形成备用区域大门。隔离区域在有源区域之外并且围绕有源区域。在隔离区域中，设置第二导电型隔离离子注入区域和延伸离子注入区域，以防止在源极扩散区域和漏极扩散区域之间产生寄生电流。

5. 发明申请

US20060270162A1 HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICES AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：高电压金属氧化物半导体晶体管器件及其制造方法
公开(公告)号：US20060270162A1
公开(公告)日：2006-11-30
申请号：US11307075
申请日：2006-01-23
申请人： Chien-Ming Lin , Ming-Tsung Tung , Chin-Hung Liu
发明人： Chien-Ming Lin , Ming-Tsung Tung , Chin-Hung Liu
IPC分类号： H01L21/8234 , H01L29/76
CPC分类号： H01L27/11526 , H01L21/823462 , H01L21/823468 , H01L27/105 , H01L27/1052 , H01L27/11546
摘要： A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polysilicon layer not masked by the resist mask, thereby forming a gate electrode; etching a thickness of the gate dielectric layer not covered by the gate electrode; stripping the resist mask; forming a salicide block resist mask covering the gate electrode and a portions of the remaining gate dielectric layer; etching away the remaining gate dielectric layer not covered by the salicide block resist mask, thereby exposing the substrate and forming a salicide block lug portions on two opposite sides of the gate electrode; and making a metal layer react with the substrate, thereby forming a salicide layer that is kept a distance “d” away from the gate electrode.
摘要翻译：提供了制造金属氧化物半导体器件的方法。该方法包括在基板上形成栅介电层; 在所述栅极电介质层上沉积多晶硅层; 在所述多晶硅层上形成抗蚀剂掩模; 蚀刻未被抗蚀剂掩模掩蔽的多晶硅层，从而形成栅电极; 蚀刻未被栅电极覆盖的栅极电介质层的厚度; 剥离抗蚀剂掩模; 形成覆盖所述栅极电极和所述剩余栅极介电层的一部分的自对准硅化物阻挡掩模; 蚀刻除了未被所述自对准硅化物阻挡掩模掩盖的剩余栅极电介质层，从而暴露所述基板并在所述栅电极的两个相对侧上形成自对准硅嵌块凸块部分; 并且使金属层与基板反应，从而形成与栅电极保持距离“d”的自对准硅化物层。

6. 发明申请

US20090184368A1 IC CHIP 有权
标题翻译： IC芯片
公开(公告)号：US20090184368A1
公开(公告)日：2009-07-23
申请号：US12018638
申请日：2008-01-23
申请人： Chin-Hung Liu , Chin-Lung Chen , Ming-Tsung Tung , Wen-Kuo Li
发明人： Chin-Hung Liu , Chin-Lung Chen , Ming-Tsung Tung , Wen-Kuo Li
IPC分类号： H01L29/78
CPC分类号： H01L27/088 , H01L21/823418 , H01L27/0207 , H01L29/0653 , H01L29/0696 , H01L29/086 , H01L29/0878 , H01L29/4238 , H01L29/7816
摘要： An IC chip, including a switch LDMOS device and an analog LDMOS device, is configured on a substrate having a first conductive type. Components of the two LDMOS devices respectively include two gate conductive layers configured on two first active regions of the substrate. A common source contact region having a second conductive type is configured in a second active region, which is configured between the two first active regions. An isolation structure is included for isolating the second active region and the first active regions. The isolation structure between the first active regions and the second active region has a length “A” extending along a longitudinal direction of a channel under each gate conductive layer, and each gate conductive layer on each first active region has a length “L” extending along the longitudinal direction of the channel, the two LDMOS devices have different A/L values.
摘要翻译：包括开关LDMOS器件和模拟LDMOS器件的IC芯片配置在具有第一导电类型的衬底上。两个LDMOS器件的组件分别包括配置在衬底的两个第一有源区上的两个栅极导电层。具有第二导电类型的公共源极接触区域被配置在第二有源区域中，第二有源区域被配置在两个第一有源区域之间。包括用于隔离第二有源区和第一有源区的隔离结构。第一有源区和第二有源区之间的隔离结构具有沿着每个栅极导电层下方的沟道的纵向方向延伸的长度“A”，并且每个第一有源区上的每个栅极导电层具有长度“L” 沿着通道的纵向方向，两个LDMOS器件具有不同的A / L值。

7. 发明授权

US07256095B2 High voltage metal-oxide-semiconductor transistor devices and method of making the same 有权
标题翻译：高压金属氧化物半导体晶体管器件及其制造方法
公开(公告)号：US07256095B2
公开(公告)日：2007-08-14
申请号：US11468782
申请日：2006-08-31
申请人： Chien-Ming Lin , Ming-Tsung Tung , Chin-Hung Liu
发明人： Chien-Ming Lin , Ming-Tsung Tung , Chin-Hung Liu
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L21/823462 , H01L21/823468 , H01L27/105 , H01L27/1052 , H01L27/11546
摘要： A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polysilicon layer not masked by the resist mask, thereby forming a gate electrode; etching a thickness of the gate dielectric layer not covered by the gate electrode; stripping the resist mask; forming a salicide block resist mask covering the gate electrode and a portions of the remaining gate dielectric layer; etching away the remaining gate dielectric layer not covered by the salicide block resist mask, thereby exposing the substrate and forming a salicide block lug portions on two opposite sides of the gate electrode; and making a metal layer react with the substrate, thereby forming a salicide layer that is kept a distance “d” away from the gate electrode.
摘要翻译：提供了制造金属氧化物半导体器件的方法。该方法包括在基板上形成栅介电层; 在所述栅极电介质层上沉积多晶硅层; 在所述多晶硅层上形成抗蚀剂掩模; 蚀刻未被抗蚀剂掩模掩蔽的多晶硅层，从而形成栅电极; 蚀刻未被栅电极覆盖的栅极电介质层的厚度; 剥离抗蚀剂掩模; 形成覆盖所述栅极电极和所述剩余栅极介电层的一部分的自对准硅化物阻挡掩模; 蚀刻除了未被所述自对准硅化物阻挡掩模掩盖的剩余栅极电介质层，从而暴露所述基板并在所述栅电极的两个相对侧上形成自对准硅嵌块凸块部分; 并且使金属层与基板反应，从而形成与栅电极保持距离“d”的自对准硅化物层。

8. 发明申请

US20070141776A1 SEMICONDUCTOR DEVICE HAVING CAPACITOR AND FABRICATING METHOD THEREOF 审中-公开
标题翻译：具有电容器的半导体器件及其制造方法
公开(公告)号：US20070141776A1
公开(公告)日：2007-06-21
申请号：US11306162
申请日：2005-12-19
申请人： Jung-Ching Chen , Chin-Hung Liu , Chien-Ming Lin , Ming-Tsung Tung
发明人： Jung-Ching Chen , Chin-Hung Liu , Chien-Ming Lin , Ming-Tsung Tung
IPC分类号： H01L21/8244
CPC分类号： H01L28/40 , H01L27/1085
摘要： A semiconductor device having a capacitor is provided. The semiconductor device includes a substrate, a capacitor and a metal-oxide-semiconductor (MOS) transistor. The MOS transistor is located in a MOS transistor region of the substrate, and the MOS transistor region has a first bottom diffusion region. The capacitor is located in a capacitor region of the substrate and consisted of a second bottom diffusion region located in the substrate, a first dielectric layer located over the second bottom diffusion region, a bottom conductive layer located over the first dielectric layer, a second dielectric layer located over the bottom conductive layer, and a top conductive layer located over the second dielectric layer. The first bottom diffusion region and the second bottom diffusion region are different conductive type.
摘要翻译：提供具有电容器的半导体器件。半导体器件包括衬底，电容器和金属氧化物半导体（MOS）晶体管。 MOS晶体管位于衬底的MOS晶体管区域中，并且MOS晶体管区域具有第一底部扩散区域。电容器位于衬底的电容器区域中，由位于衬底中的第二底部扩散区域，位于第二底部扩散区域上方的第一电介质层，位于第一电介质层上方的底部导电层，第二电介质层位于所述底部导电层上方的层，以及位于所述第二介电层上方的顶部导电层。第一底部扩散区域和第二底部扩散区域是不同的导电类型。

9. 发明申请

US20070254417A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A CAPACITOR 审中-公开
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US20070254417A1
公开(公告)日：2007-11-01
申请号：US11777294
申请日：2007-07-13
申请人： Jung-Ching Chen , Chin-Hung Liu , Chien-Ming Lin , Ming-Tsung Tung
发明人： Jung-Ching Chen , Chin-Hung Liu , Chien-Ming Lin , Ming-Tsung Tung
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L28/40 , H01L27/1085
摘要： A semiconductor device having a capacitor is provided. The semiconductor device includes a substrate, a capacitor and a metal-oxide-semiconductor (MOS) transistor. The MOS transistor is located in a MOS transistor region of the substrate, and the MOS transistor region has a first bottom diffusion region. The capacitor is located in a capacitor region of the substrate and consisted of a second bottom diffusion region located in the substrate, a first dielectric layer located over the second bottom diffusion region, a bottom conductive layer located over the first dielectric layer, a second dielectric layer located over the bottom conductive layer, and a top conductive layer located over the second dielectric layer. The first bottom diffusion region and the second bottom diffusion region are different conductive type.
摘要翻译：提供具有电容器的半导体器件。半导体器件包括衬底，电容器和金属氧化物半导体（MOS）晶体管。 MOS晶体管位于衬底的MOS晶体管区域中，并且MOS晶体管区域具有第一底部扩散区域。电容器位于衬底的电容器区域中，由位于衬底中的第二底部扩散区域，位于第二底部扩散区域上方的第一电介质层，位于第一电介质层上方的底部导电层，第二电介质层位于所述底部导电层上方的层，以及位于所述第二介电层上方的顶部导电层。第一底部扩散区域和第二底部扩散区域是不同的导电类型。

10. 发明申请

US20060292803A1 HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICES AND METHOD OF MAKING THE SAME 有权
公开(公告)号：US20060292803A1
公开(公告)日：2006-12-28
申请号：US11468782
申请日：2006-08-31
申请人： Chien-Ming Lin , Ming-Tsung Tung , Chin-Hung Liu
发明人： Chien-Ming Lin , Ming-Tsung Tung , Chin-Hung Liu
IPC分类号： H01L21/8234
CPC分类号： H01L27/11526 , H01L21/823462 , H01L21/823468 , H01L27/105 , H01L27/1052 , H01L27/11546
摘要： A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polysilicon layer not masked by the resist mask, thereby forming a gate electrode; etching a thickness of the gate dielectric layer not covered by the gate electrode; stripping the resist mask; forming a salicide block resist mask covering the gate electrode and a portions of the remaining gate dielectric layer; etching away the remaining gate dielectric layer not covered by the salicide block resist mask, thereby exposing the substrate and forming a salicide block lug portions on two opposite sides of the gate electrode; and making a metal layer react with the substrate, thereby forming a salicide layer that is kept a distance “d” away from the gate electrode.

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