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    • 3. 发明授权
    • Display and method thereof for signal transmission
    • 信号传输的显示及其方法
    • US08421779B2
    • 2013-04-16
    • US12129254
    • 2008-05-29
    • Wen-Teng FanChien-Ru Chen
    • Wen-Teng FanChien-Ru Chen
    • G09G5/00
    • G09G3/3611G09G5/006G09G2310/08G09G2370/08
    • A display and a method for signal transmission of the display are provided. The display has a source driver, a panel, and a timing controller having at least one data pin and a clock signal pin. The timing controller sends a clock signal to the source driver via the clock signal pin, and then sends a start pulse pattern to the source driver via the at least one data pin such that the source driver is notified to receive setting signals and display data signals. The source driver drives the panel according to the setting signals and the display data signals received from the timing controller via the at least one data pin. One or more of the setting signals are received by the source driver within every clock of the clock signal.
    • 提供了一种用于显示器的信号传输的显示器和方法。 显示器具有源驱动器,面板和具有至少一个数据引脚和时钟信号引脚的定时控制器。 定时控制器通过时钟信号引脚向源驱动器发送时钟信号,然后经由至少一个数据引脚向源驱动器发送起始脉冲模式,以便通知源驱动器接收设置信号和显示数据信号 。 源驱动器根据设置信号和经由至少一个数据引脚从定时控制器接收到的显示数据信号驱动面板。 源驱动器在时钟信号的每个时钟内接收一个或多个设置信号。
    • 5. 发明授权
    • Compact layout structure for decoder with pre-decoding and source driving circuit using the same
    • 具有预解码和解码驱动电路的解码器的紧凑布局结构
    • US08179389B2
    • 2012-05-15
    • US12121300
    • 2008-05-15
    • Wen-Teng Fan
    • Wen-Teng Fan
    • G09G5/00
    • H03M1/682G09G3/3696G09G2320/0276G09G2320/0673H03M1/76
    • Provided is a decoder for receiving a digital data and outputting an analog voltage. The decoder comprising a main switch array, a first pre-decoding switch array, and a second pre-decoding switch array. The main switch array receives the digital data and outputs a voltage if the digital data is in a first range. The first pre-decoding switch array is for receiving the digital data, pre-decoding a part of the digital data, and outputting a voltage if the digital data is in a second range. The second pre-decoding switch array is for receiving the digital data, pre-decoding the part of the digital data, and outputting a voltage if the digital data is in a third range. Combination of the main switch array, the first pre-decoding switch array, and the second pre-decoding switch array is in a substantially rectangular layout structure.
    • 提供了一种用于接收数字数据并输出模拟电压的解码器。 解码器包括主开关阵列,第一预解码开关阵列和第二预解码开关阵列。 如果数字数据处于第一范围,则主开关阵列接收数字数据并输出电压。 第一预解码开关阵列用于接收数字数据,对数字数据的一部分进行预解码,并且如果数字数据处于第二范围则输出电压。 第二预解码开关阵列用于接收数字数据,对数字数据的一部分进行预解码,并且如果数字数据处于第三范围则输出电压。 主开关阵列,第一预解码开关阵列和第二预解码开关阵列的组合是基本上矩形的布局结构。
    • 6. 发明申请
    • PHASE SELECTOR
    • 相位选择器
    • US20110255867A1
    • 2011-10-20
    • US12759886
    • 2010-04-14
    • Wen-Teng FanChan-Fei LinShih-Chun Lin
    • Wen-Teng FanChan-Fei LinShih-Chun Lin
    • H04J14/00
    • H03K5/135H03K2005/00052H03L7/0812
    • A phase selector including a plurality of buffers, a multiplexer, a first inverter, and a selecting circuit is provided. Each of the buffers provides a clock signal, and the clock signals have different phases. The multiplexer selectively outputs one of the clock signals as a switch signal according to a first control signal, wherein the first control signal is first portion of bits of a selecting signal. The input terminal of the first inverter receives a second control signal, wherein the second control signal is second portion of bits of the selecting signal, and the output terminal of the first inverter outputs an inverted signal. The selecting circuit transmits the second control signal of the selecting signal or the inverted signal to the output terminal of the phase selector according to the logic state of the switch signal.
    • 提供了包括多个缓冲器的相位选择器,多路复用器,第一反相器和选择电路。 每个缓冲器提供时钟信号,并且时钟信号具有不同的相位。 复用器根据第一控制信号选择性地输出其中一个时钟信号作为开关信号,其中第一控制信号是选择信号的位的第一部分。 第一反相器的输入端接收第二控制信号,其中第二控制信号是选择信号的位的第二部分,第一反相器的输出端输出反相信号。 选择电路根据开关信号的逻辑状态将选择信号或反相信号的第二控制信号发送到相位选择器的输出端。
    • 8. 发明授权
    • Timing controller and clock signal detection circuit thereof
    • 定时控制器及其时钟信号检测电路
    • US08390614B2
    • 2013-03-05
    • US12719649
    • 2010-03-08
    • Wen-Teng FanShih-Chun Lin
    • Wen-Teng FanShih-Chun Lin
    • G06F3/038G09G5/00
    • G06F3/038H03L7/06
    • The clock signal detection circuit includes a lock detection circuit, a duty cycle detection circuit, a first logic circuit, and a counter. The lock detection circuit detects whether an input clock signal and a feedback clock signal of a delay locked loop are in phase. The duty cycle detection circuit detects whether the duty cycle of the input clock signal is within a percentage range. The first logic circuit, electrically connected to the lock detection circuit and the duty cycle detection circuit, outputs a detecting result signal which is at first logic level when the input clock signal are in phase with the feedback clock signal, and the duty cycle of the input clock signal is within a percentage range. The counter outputs a lock detection signal which is at the first logic level when the detecting result signal has maintained at the first logic level for a first constant period of time.
    • 时钟信号检测电路包括锁定检测电路,占空比检测电路,第一逻辑电路和计数器。 锁定检测电路检测延迟锁定环路的输入时钟信号和反馈时钟信号是否同相。 占空比检测电路检测输入时钟信号的占空比是否在百分比范围内。 与锁定检测电路和占空比检测电路电连接的第一逻辑电路输出当输入时钟信号与反馈时钟信号同相时处于第一逻辑电平的检测结果信号, 输入时钟信号在百分比范围内。 当检测结果信号在第一恒定时间段内保持在第一逻辑电平时,计数器输出处于第一逻辑电平的锁定检测信号。
    • 9. 发明授权
    • Spread-spectrum generator
    • 扩频发生器
    • US08180006B2
    • 2012-05-15
    • US12540817
    • 2009-08-13
    • Wen-Teng FanShih-Chun Lin
    • Wen-Teng FanShih-Chun Lin
    • H04L7/00H03D3/24H04B1/00
    • H04B15/06H04B2215/064H04B2215/067
    • A spread-spectrum generator is provided. The spread-spectrum generator includes a delay module and a control module. The delay module is controlled by a first control signal to delay an input signal by a delay time, and thereby generate a delay signal. The control module is coupled to the delay module for detecting a first edge of the delay signal, and thereby generating the first control signal. Accordingly, the spread-spectrum generator can spread the frequency of the input signal by delaying the input signal by various delay time, and the spread-spectrum generator can also reduce electromagnetic interference (EMI).
    • 提供扩频发生器。 扩频发生器包括延迟模块和控制模块。 延迟模块由第一控制信号控制,以将输入信号延迟延迟时间,从而产生延迟信号。 控制模块耦合到延迟模块,用于检测延迟信号的第一边缘,从而产生第一控制信号。 因此,扩频发生器可以通过延迟输入信号各种延迟时间来扩展输入信号的频率,扩频发生器也可以减小电磁干扰(EMI)。