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1. 发明申请

US20110255867A1 PHASE SELECTOR 有权
标题翻译：相位选择器
公开(公告)号：US20110255867A1
公开(公告)日：2011-10-20
申请号：US12759886
申请日：2010-04-14
申请人： Wen-Teng Fan , Chan-Fei Lin , Shih-Chun Lin
发明人： Wen-Teng Fan , Chan-Fei Lin , Shih-Chun Lin
IPC分类号： H04J14/00
CPC分类号： H03K5/135 , H03K2005/00052 , H03L7/0812
摘要： A phase selector including a plurality of buffers, a multiplexer, a first inverter, and a selecting circuit is provided. Each of the buffers provides a clock signal, and the clock signals have different phases. The multiplexer selectively outputs one of the clock signals as a switch signal according to a first control signal, wherein the first control signal is first portion of bits of a selecting signal. The input terminal of the first inverter receives a second control signal, wherein the second control signal is second portion of bits of the selecting signal, and the output terminal of the first inverter outputs an inverted signal. The selecting circuit transmits the second control signal of the selecting signal or the inverted signal to the output terminal of the phase selector according to the logic state of the switch signal.
摘要翻译：提供了包括多个缓冲器的相位选择器，多路复用器，第一反相器和选择电路。每个缓冲器提供时钟信号，并且时钟信号具有不同的相位。复用器根据第一控制信号选择性地输出其中一个时钟信号作为开关信号，其中第一控制信号是选择信号的位的第一部分。第一反相器的输入端接收第二控制信号，其中第二控制信号是选择信号的位的第二部分，第一反相器的输出端输出反相信号。选择电路根据开关信号的逻辑状态将选择信号或反相信号的第二控制信号发送到相位选择器的输出端。

2. 发明授权

US08390614B2 Timing controller and clock signal detection circuit thereof 有权
标题翻译：定时控制器及其时钟信号检测电路
公开(公告)号：US08390614B2
公开(公告)日：2013-03-05
申请号：US12719649
申请日：2010-03-08
申请人： Wen-Teng Fan , Shih-Chun Lin
发明人： Wen-Teng Fan , Shih-Chun Lin
IPC分类号： G06F3/038 , G09G5/00
CPC分类号： G06F3/038 , H03L7/06
摘要： The clock signal detection circuit includes a lock detection circuit, a duty cycle detection circuit, a first logic circuit, and a counter. The lock detection circuit detects whether an input clock signal and a feedback clock signal of a delay locked loop are in phase. The duty cycle detection circuit detects whether the duty cycle of the input clock signal is within a percentage range. The first logic circuit, electrically connected to the lock detection circuit and the duty cycle detection circuit, outputs a detecting result signal which is at first logic level when the input clock signal are in phase with the feedback clock signal, and the duty cycle of the input clock signal is within a percentage range. The counter outputs a lock detection signal which is at the first logic level when the detecting result signal has maintained at the first logic level for a first constant period of time.
摘要翻译：时钟信号检测电路包括锁定检测电路，占空比检测电路，第一逻辑电路和计数器。锁定检测电路检测延迟锁定环路的输入时钟信号和反馈时钟信号是否同相。占空比检测电路检测输入时钟信号的占空比是否在百分比范围内。与锁定检测电路和占空比检测电路电连接的第一逻辑电路输出当输入时钟信号与反馈时钟信号同相时处于第一逻辑电平的检测结果信号，输入时钟信号在百分比范围内。当检测结果信号在第一恒定时间段内保持在第一逻辑电平时，计数器输出处于第一逻辑电平的锁定检测信号。

3. 发明授权

US08180006B2 Spread-spectrum generator 有权
标题翻译：扩频发生器
公开(公告)号：US08180006B2
公开(公告)日：2012-05-15
申请号：US12540817
申请日：2009-08-13
申请人： Wen-Teng Fan , Shih-Chun Lin
发明人： Wen-Teng Fan , Shih-Chun Lin
IPC分类号： H04L7/00 , H03D3/24 , H04B1/00
CPC分类号： H04B15/06 , H04B2215/064 , H04B2215/067
摘要： A spread-spectrum generator is provided. The spread-spectrum generator includes a delay module and a control module. The delay module is controlled by a first control signal to delay an input signal by a delay time, and thereby generate a delay signal. The control module is coupled to the delay module for detecting a first edge of the delay signal, and thereby generating the first control signal. Accordingly, the spread-spectrum generator can spread the frequency of the input signal by delaying the input signal by various delay time, and the spread-spectrum generator can also reduce electromagnetic interference (EMI).
摘要翻译：提供扩频发生器。扩频发生器包括延迟模块和控制模块。延迟模块由第一控制信号控制，以将输入信号延迟延迟时间，从而产生延迟信号。控制模块耦合到延迟模块，用于检测延迟信号的第一边缘，从而产生第一控制信号。因此，扩频发生器可以通过延迟输入信号各种延迟时间来扩展输入信号的频率，扩频发生器也可以减小电磁干扰（EMI）。

4. 发明申请

US20110038397A1 SPREAD-SPECTRUM GENERATOR 有权
标题翻译：扩频发生器
公开(公告)号：US20110038397A1
公开(公告)日：2011-02-17
申请号：US12540817
申请日：2009-08-13
申请人： Wen-Teng Fan , Shih-Chun Lin
发明人： Wen-Teng Fan , Shih-Chun Lin
IPC分类号： H04B1/69
CPC分类号： H04B15/06 , H04B2215/064 , H04B2215/067
摘要： A spread-spectrum generator is provided. The spread-spectrum generator includes a delay module and a control module. The delay module is controlled by a first control signal to delay an input signal by a delay time, and thereby generate a delay signal. The control module is coupled to the delay module for detecting a first edge of the delay signal, and thereby generating the first control signal. Accordingly, the spread-spectrum generator can spread the frequency of the input signal by delaying the input signal by various delay time, and the spread-spectrum generator can also reduce electromagnetic interference (EMI).
摘要翻译：提供扩频发生器。扩频发生器包括延迟模块和控制模块。延迟模块由第一控制信号控制，以将输入信号延迟延迟时间，从而产生延迟信号。控制模块耦合到延迟模块，用于检测延迟信号的第一边缘，从而产生第一控制信号。因此，扩频发生器可以通过延迟输入信号各种延迟时间来扩展输入信号的频率，扩频发生器也可以减小电磁干扰（EMI）。

5. 发明授权

US08222941B2 Phase selector 有权
标题翻译：相位选择器
公开(公告)号：US08222941B2
公开(公告)日：2012-07-17
申请号：US12759886
申请日：2010-04-14
申请人： Wen-Teng Fan , Chan-Fei Lin , Shih-Chun Lin
发明人： Wen-Teng Fan , Chan-Fei Lin , Shih-Chun Lin
IPC分类号： H03L7/00
CPC分类号： H03K5/135 , H03K2005/00052 , H03L7/0812
摘要： A phase selector including a plurality of buffers, a multiplexer, a first inverter, and a selecting circuit is provided. Each of the buffers provides a clock signal, and the clock signals have different phases. The multiplexer selectively outputs one of the clock signals as a switch signal according to a first control signal, wherein the first control signal is first portion of bits of a selecting signal. The input terminal of the first inverter receives a second control signal, wherein the second control signal is second portion of bits of the selecting signal, and the output terminal of the first inverter outputs an inverted signal. The selecting circuit transmits the second control signal of the selecting signal or the inverted signal to the output terminal of the phase selector according to the logic state of the switch signal.
摘要翻译：提供了包括多个缓冲器的相位选择器，多路复用器，第一反相器和选择电路。每个缓冲器提供时钟信号，并且时钟信号具有不同的相位。复用器根据第一控制信号选择性地输出其中一个时钟信号作为开关信号，其中第一控制信号是选择信号的位的第一部分。第一反相器的输入端接收第二控制信号，其中第二控制信号是选择信号的位的第二部分，第一反相器的输出端输出反相信号。选择电路根据开关信号的逻辑状态将选择信号或反相信号的第二控制信号发送到相位选择器的输出端。

6. 发明授权

US08780093B2 Method for transmitting image data through RSDS transmission interfaces 有权
标题翻译：通过RSDS传输接口传输图像数据的方法
公开(公告)号：US08780093B2
公开(公告)日：2014-07-15
申请号：US12411172
申请日：2009-03-25
申请人： Ying-Lieh Chen , Wen-Teng Fan , Chao-Ching Chi
发明人： Ying-Lieh Chen , Wen-Teng Fan , Chao-Ching Chi
IPC分类号： G06F3/038
CPC分类号： G09G3/20 , G09G2370/14
摘要： A method for transmitting image data in a display is provided. The method includes the steps of: sending first pixel data through a first bus to a source driver; sending second pixel data through a second bus to the source driver; reorganizing the first pixel data and the second pixel data in the source driver; and generating third pixel data according to the reorganization of the first pixel data and the second pixel data for channels in the source driver. A display is also disclosed herein.
摘要翻译：提供了一种在显示器中传送图像数据的方法。该方法包括以下步骤：通过第一总线将第一像素数据发送到源驱动器; 通过第二总线向源驱动器发送第二像素数据; 重新组织源驱动器中的第一像素数据和第二像素数据; 以及根据所述源驱动器中的所述第一像素数据和所述第二像素数据的重新组合来生成第三像素数据。本文还公开了一种显示器。

7. 发明授权

US08421779B2 Display and method thereof for signal transmission 有权
标题翻译：信号传输的显示及其方法
公开(公告)号：US08421779B2
公开(公告)日：2013-04-16
申请号：US12129254
申请日：2008-05-29
申请人： Wen-Teng Fan , Chien-Ru Chen
发明人： Wen-Teng Fan , Chien-Ru Chen
IPC分类号： G09G5/00
CPC分类号： G09G3/3611 , G09G5/006 , G09G2310/08 , G09G2370/08
摘要： A display and a method for signal transmission of the display are provided. The display has a source driver, a panel, and a timing controller having at least one data pin and a clock signal pin. The timing controller sends a clock signal to the source driver via the clock signal pin, and then sends a start pulse pattern to the source driver via the at least one data pin such that the source driver is notified to receive setting signals and display data signals. The source driver drives the panel according to the setting signals and the display data signals received from the timing controller via the at least one data pin. One or more of the setting signals are received by the source driver within every clock of the clock signal.
摘要翻译：提供了一种用于显示器的信号传输的显示器和方法。显示器具有源驱动器，面板和具有至少一个数据引脚和时钟信号引脚的定时控制器。定时控制器通过时钟信号引脚向源驱动器发送时钟信号，然后经由至少一个数据引脚向源驱动器发送起始脉冲模式，以便通知源驱动器接收设置信号和显示数据信号。源驱动器根据设置信号和经由至少一个数据引脚从定时控制器接收到的显示数据信号驱动面板。源驱动器在时钟信号的每个时钟内接收一个或多个设置信号。

8. 发明授权

US07965271B2 Liquid crystal display driving circuit and method thereof 有权
标题翻译：液晶显示驱动电路及其方法
公开(公告)号：US07965271B2
公开(公告)日：2011-06-21
申请号：US11752586
申请日：2007-05-23
申请人： Wen-Teng Fan , Chien-Ru Chen , Ying-Lieh Chen
发明人： Wen-Teng Fan , Chien-Ru Chen , Ying-Lieh Chen
IPC分类号： G09G3/36
CPC分类号： G09G3/3611 , G09G3/3688 , G09G2310/08 , G09G2370/08
摘要： The present invention provides a liquid crystal display comprising a display panel, a plurality of gate drivers sequentially enabling rows of pixels of the display panel, a plurality of source drivers outputting a plurality of driving signals to the enabled row of the pixels of the display panel, and a timing controller outputting each of a plurality of start pulses to all the source drivers and sequentially enabling the source drivers so that each source driver respectively receives one of the start pulses, wherein each of the source drivers latch a plurality of image signals when receiving one of the start pulses.
摘要翻译：本发明提供了一种液晶显示器，其包括显示面板，多个栅极驱动器，其顺序地使所述显示面板的像素行排列;多个源极驱动器，将多个驱动信号输出到所述显示面板的所述能量行的像素以及定时控制器，其向所有源极驱动器输出多个起始脉冲中的每一个，并且顺序地使能源极驱动器，使得每个源极驱动器分别接收其中一个起始脉冲，其中每个源极驱动器锁存多个图像信号，当接收一个起始脉冲。

9. 发明授权

US08179389B2 Compact layout structure for decoder with pre-decoding and source driving circuit using the same 有权
标题翻译：具有预解码和解码驱动电路的解码器的紧凑布局结构
公开(公告)号：US08179389B2
公开(公告)日：2012-05-15
申请号：US12121300
申请日：2008-05-15
申请人： Wen-Teng Fan
发明人： Wen-Teng Fan
IPC分类号： G09G5/00
CPC分类号： H03M1/682 , G09G3/3696 , G09G2320/0276 , G09G2320/0673 , H03M1/76
摘要： Provided is a decoder for receiving a digital data and outputting an analog voltage. The decoder comprising a main switch array, a first pre-decoding switch array, and a second pre-decoding switch array. The main switch array receives the digital data and outputs a voltage if the digital data is in a first range. The first pre-decoding switch array is for receiving the digital data, pre-decoding a part of the digital data, and outputting a voltage if the digital data is in a second range. The second pre-decoding switch array is for receiving the digital data, pre-decoding the part of the digital data, and outputting a voltage if the digital data is in a third range. Combination of the main switch array, the first pre-decoding switch array, and the second pre-decoding switch array is in a substantially rectangular layout structure.
摘要翻译：提供了一种用于接收数字数据并输出模拟电压的解码器。解码器包括主开关阵列，第一预解码开关阵列和第二预解码开关阵列。如果数字数据处于第一范围，则主开关阵列接收数字数据并输出电压。第一预解码开关阵列用于接收数字数据，对数字数据的一部分进行预解码，并且如果数字数据处于第二范围则输出电压。第二预解码开关阵列用于接收数字数据，对数字数据的一部分进行预解码，并且如果数字数据处于第三范围则输出电压。主开关阵列，第一预解码开关阵列和第二预解码开关阵列的组合是基本上矩形的布局结构。

10. 发明申请

US20100188379A1 Display and Method for Driving the Same 审中-公开
标题翻译：显示器及其驱动方法
公开(公告)号：US20100188379A1
公开(公告)日：2010-07-29
申请号：US12358558
申请日：2009-01-23
申请人： Ying-Lieh Chen , Wen-Teng Fan , Chao-Ching Chi
发明人： Ying-Lieh Chen , Wen-Teng Fan , Chao-Ching Chi
IPC分类号： G06F3/038
CPC分类号： G09G3/20 , G09G2310/0275 , G09G2310/08 , G09G2320/0223
摘要： A display comprises a panel, a gate driver and a plurality of source drivers. The panel comprises a plurality of pixels arranged in an array. The gate driver is provided for selectively activating a gate line of the panel. The source drivers, during a line period, receive a plurality of transfer pulses, each of which corresponds to one of the source drivers. The source drivers drive one row of the pixels corresponding to the activated gate line, while triggered by the corresponding transfer pulse, wherein the transfer pulses are not all identical. A method for driving a display is also disclosed herein.
摘要翻译：显示器包括面板，门驱动器和多个源驱动器。面板包括排列成阵列的多个像素。栅极驱动器被提供用于选择性地激活面板的栅极线。源极驱动器在线路周期期间接收多个传输脉冲，每个传输脉冲对应于一个源驱动器。源驱动器驱动对应于激活的栅极线的一行像素，同时由相应的传输脉冲触发，其中传输脉冲并不全部相同。本文还公开了一种用于驱动显示器的方法。

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