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1. 发明申请

US20160027754A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160027754A1
公开(公告)日：2016-01-28
申请号：US14773817
申请日：2014-03-10
申请人： Mitsuaki KATAGIRI , Yu HASEGAWA , Satoshi ISA , PS4 Luxco S.a.r.l.
发明人： Mitsuaki Katagiri , Yu Hasegawa , Satoshi Isa
IPC分类号： H01L23/00 , H01L23/31 , H01L23/48 , H01L23/498
CPC分类号： H01L24/17 , H01L21/561 , H01L22/32 , H01L23/12 , H01L23/3107 , H01L23/3128 , H01L23/481 , H01L23/49816 , H01L23/49838 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L2224/0235 , H01L2224/02375 , H01L2224/0345 , H01L2224/03912 , H01L2224/0392 , H01L2224/0401 , H01L2224/05014 , H01L2224/05015 , H01L2224/05025 , H01L2224/05166 , H01L2224/05548 , H01L2224/05554 , H01L2224/05647 , H01L2224/0603 , H01L2224/06051 , H01L2224/06102 , H01L2224/11462 , H01L2224/11472 , H01L2224/11849 , H01L2224/13006 , H01L2224/13007 , H01L2224/13013 , H01L2224/13014 , H01L2224/13017 , H01L2224/13018 , H01L2224/13021 , H01L2224/13022 , H01L2224/13024 , H01L2224/13025 , H01L2224/13028 , H01L2224/131 , H01L2224/13147 , H01L2224/1403 , H01L2224/14051 , H01L2224/1411 , H01L2224/14131 , H01L2224/14135 , H01L2224/14136 , H01L2224/14177 , H01L2224/14181 , H01L2224/14515 , H01L2224/16145 , H01L2224/16146 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/17181 , H01L2224/17517 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81801 , H01L2224/83102 , H01L2224/83862 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/15311 , H01L2924/3011 , H01L2924/3511 , H05K1/025 , H05K1/141 , H05K1/185 , H05K2201/10734 , H01L2224/81 , H01L2224/83 , H01L2924/00012 , H01L2924/00014 , H01L2224/11 , H01L2924/014 , H01L2924/00
摘要： To provide a semiconductor device with a wafer level package structure that allows for probing while reducing the area occupied by the pad electrodes.[Solution] In the present invention, the following are provided: a semiconductor chip (100) that has first and second pad electrodes (120a, 120b) disposed on the main surface thereof; insulating films (310, 330) that cover the main surface of the semiconductor chip (100); a rewiring layer (320) that is disposed between the insulating films (310, 330); and a plurality of external terminals (340) disposed on the top of the insulating film (330). The plane size of the first pad electrode (120a) and the second pad electrode (120b) differ from one another, and the first pad electrode (120a) and the second pad electrode (120b) are connected to any of the plurality of external terminals (340) via the rewiring layer (320). According to the present invention, because the pad electrodes (120a, 120b) of different sizes are intermixed, probing can be easily performed while reducing the area occupied by the pad electrodes.
摘要翻译：提供具有晶片级封装结构的半导体器件，其允许在减小焊盘电极占据的面积的同时进行探测。 [解决方案]在本发明中，提供了一种半导体芯片（100），其具有设置在其主表面上的第一和第二焊盘电极（120a，120b）覆盖半导体芯片（100）的主表面的绝缘膜（310,330）; 布置在所述绝缘膜（310,330）之间的再布线层（320）; 以及设置在绝缘膜（330）的顶部上的多个外部端子（340）。第一焊盘电极（120a）和第二焊盘电极（120b）的平面尺寸彼此不同，并且第一焊盘电极（120a）和第二焊盘电极（120b）连接到多个外部端子（340）经由重新布线层（320）。根据本发明，由于不同尺寸的焊盘电极（120a，120b）是混合的，所以可以容易地进行探测，同时减少焊盘电极占据的面积。

2. 发明授权

US08581417B2 Semiconductor device stack with bonding layer and wire retaining member 失效
公开(公告)号：US08581417B2
公开(公告)日：2013-11-12
申请号：US12687311
申请日：2010-01-14
申请人： Yu Hasegawa , Mitsuaki Katagiri , Satoshi Isa , Ken Iwakura , Dai Sasaki
发明人： Yu Hasegawa , Mitsuaki Katagiri , Satoshi Isa , Ken Iwakura , Dai Sasaki
IPC分类号： H01L23/02 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L25/0657 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/48599 , H01L2224/4899 , H01L2224/49171 , H01L2224/73265 , H01L2224/85007 , H01L2224/85051 , H01L2224/85444 , H01L2225/0651 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/20755 , H01L2924/30105 , H01L2924/00 , H01L2224/48132 , H01L2924/00012 , H01L2924/20757 , H01L2924/2075 , H01L2924/20754 , H01L2224/4554 , H01L2224/85399 , H01L2224/05599
摘要： In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip.

3. 发明授权

US09589921B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09589921B2
公开(公告)日：2017-03-07
申请号：US14773817
申请日：2014-03-10
申请人： PS4 Luxco S.a.r.l. , Mitsuaki Katagiri , Yu Hasegawa , Satoshi Isa
发明人： Mitsuaki Katagiri , Yu Hasegawa , Satoshi Isa
IPC分类号： H01L23/00 , H01L23/31 , H01L23/48 , H01L23/498 , H01L25/065 , H01L23/12 , H01L21/56 , H01L21/66 , H05K1/02 , H05K1/14 , H05K1/18
CPC分类号： H01L24/17 , H01L21/561 , H01L22/32 , H01L23/12 , H01L23/3107 , H01L23/3128 , H01L23/481 , H01L23/49816 , H01L23/49838 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L2224/0235 , H01L2224/02375 , H01L2224/0345 , H01L2224/03912 , H01L2224/0392 , H01L2224/0401 , H01L2224/05014 , H01L2224/05015 , H01L2224/05025 , H01L2224/05166 , H01L2224/05548 , H01L2224/05554 , H01L2224/05647 , H01L2224/0603 , H01L2224/06051 , H01L2224/06102 , H01L2224/11462 , H01L2224/11472 , H01L2224/11849 , H01L2224/13006 , H01L2224/13007 , H01L2224/13013 , H01L2224/13014 , H01L2224/13017 , H01L2224/13018 , H01L2224/13021 , H01L2224/13022 , H01L2224/13024 , H01L2224/13025 , H01L2224/13028 , H01L2224/131 , H01L2224/13147 , H01L2224/1403 , H01L2224/14051 , H01L2224/1411 , H01L2224/14131 , H01L2224/14135 , H01L2224/14136 , H01L2224/14177 , H01L2224/14181 , H01L2224/14515 , H01L2224/16145 , H01L2224/16146 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/17181 , H01L2224/17517 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81801 , H01L2224/83102 , H01L2224/83862 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/15311 , H01L2924/3011 , H01L2924/3511 , H05K1/025 , H05K1/141 , H05K1/185 , H05K2201/10734 , H01L2224/81 , H01L2224/83 , H01L2924/00012 , H01L2924/00014 , H01L2224/11 , H01L2924/014 , H01L2924/00
摘要： In one semiconductor device, a semiconductor chip has first and second pad electrodes disposed on the main surface thereof, insulating films that cover the main surface of the semiconductor chip, a rewiring layer that is disposed between the insulating films, and a plurality of external terminals disposed on the top of the insulating film. The plane size of the first pad electrode and the second pad electrode differ from one another, and the first pad electrode and the second pad electrode are connected to any of the plurality of external terminals via the rewiring layer.
摘要翻译：在一个半导体器件中，半导体芯片具有设置在其主表面上的第一和第二焊盘电极，覆盖半导体芯片的主表面的绝缘膜，布置在绝缘膜之间的再布线层和多个外部端子设置在绝缘膜的顶部。第一焊盘电极和第二焊盘电极的平面尺寸彼此不同，并且第一焊盘电极和第二焊盘电极经由重新布线层连接到多个外部端子中的任何一个。

4. 发明授权

US08487433B2 Semiconductor device 失效
公开(公告)号：US08487433B2
公开(公告)日：2013-07-16
申请号：US13192065
申请日：2011-07-27
申请人： Yu Hasegawa , Mitsuaki Katagiri
发明人： Yu Hasegawa , Mitsuaki Katagiri
IPC分类号： H01L23/498 , H01L23/522
CPC分类号： H01L23/49811 , H01L23/13 , H01L23/538 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/78 , H01L24/83 , H01L24/85 , H01L24/97 , H01L25/0657 , H01L2224/05554 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/4813 , H01L2224/48227 , H01L2224/4824 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/4911 , H01L2224/49175 , H01L2224/49426 , H01L2224/73215 , H01L2224/73265 , H01L2224/78301 , H01L2224/83192 , H01L2224/85051 , H01L2224/85186 , H01L2224/85203 , H01L2224/85205 , H01L2224/85207 , H01L2224/92147 , H01L2224/97 , H01L2225/0651 , H01L2225/06558 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/15311 , H01L2924/181 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2224/4554
摘要： A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.

5. 发明申请

US20110084395A1 Semiconductor package substrate and semiconductor device having the same 审中-公开
标题翻译：半导体封装基板和具有该半导体封装基板的半导体器件
公开(公告)号：US20110084395A1
公开(公告)日：2011-04-14
申请号：US12923712
申请日：2010-10-05
申请人： Hiromasa Takeda , Satoshi Isa , Mitsuaki Katagiri , Ken Iwakura , Yu Hasegawa
发明人： Hiromasa Takeda , Satoshi Isa , Mitsuaki Katagiri , Ken Iwakura , Yu Hasegawa
IPC分类号： H01L23/48
CPC分类号： H01L24/50 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L23/50 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/01005 , H01L2924/01006 , H01L2924/0102 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/00
摘要： A semiconductor device includes a semiconductor chip and a package substrate on which the semiconductor chip is mounted. The package substrate has internal terminals connected to the semiconductor chip, front surface wirings connected to the internal terminals, rear surface wirings connected to external electrodes, and contacts connecting the front surface wiring and rear surface wiring. Out of the plurality of contact, some contacts included in the wirings for signal transmission are disposed near the internal terminals. Thus, a signal led out from the semiconductor chip is immediately taken away from the chip mounting surface of the package substrate. This reduces the floating capacitance between the wirings on the package substrate and chip, thereby improving the signal quality.
摘要翻译：半导体器件包括其上安装半导体芯片的半导体芯片和封装衬底。封装衬底具有连接到半导体芯片的内部端子，连接到内部端子的前表面布线，连接到外部电极的后表面布线以及连接前表面布线和背面布线的触点。在多个接触中，用于信号传输的布线中包括的一些触点设置在内部端子附近。因此，从半导体芯片引出的信号立即从封装基板的芯片安装表面取走。这降低了封装衬底和芯片之间的布线之间的浮动电容，从而提高了信号质量。

6. 发明申请

US20100314779A1 SEMICONDUCTOR DEVICE THAT SUPPRESSES MALFUNCTIONS DUE TO NOISE GENERATED IN INTERNAL CIRCUIT 失效
标题翻译：抑制由内部电路产生的噪音引起的故障的半导体器件
公开(公告)号：US20100314779A1
公开(公告)日：2010-12-16
申请号：US12787873
申请日：2010-05-26
申请人： Hiromasa TAKEDA , Satoshi Isa , Shotaro Kobayashi , Mitsuaki Katagiri
发明人： Hiromasa TAKEDA , Satoshi Isa , Shotaro Kobayashi , Mitsuaki Katagiri
IPC分类号： H01L23/485
CPC分类号： H01L24/06 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/05599 , H01L2224/4824 , H01L2224/49171 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/0102 , H01L2924/01033 , H01L2924/01056 , H01L2924/014 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor device includes a first pad row and a second pad row, a first ground potential supply electrode which is connected to a first interconnect provided near the first pad row, and a second ground potential supply electrode which is connected to a second interconnect provided near the second pad row. The first pad row includes a first pad connected to the first circuit within the chip and connected to the first interconnect via a first bonding wire, and includes a second pad connected to a second circuit within the chip and connected to the second interconnect via a second bonding wire crossing over the second pad row.
摘要翻译：半导体器件包括第一焊盘行和第二焊盘行，第一接地电位供应电极，连接到设置在第一焊盘行附近的第一互连件，以及第二接地电位供应电极，其连接到靠近第二垫排。第一焊盘行包括连接到芯片内的第一电路并经由第一接合线连接到第一互连的第一焊盘，并且包括连接到芯片内的第二电路并经由第二焊盘连接到第二互连的第二焊盘接合线穿过第二垫排。

7. 发明授权

US07823096B2 Inductance analysis system and method and program therefor 有权
标题翻译：电感分析系统及其方法和程序
公开(公告)号：US07823096B2
公开(公告)日：2010-10-26
申请号：US11495711
申请日：2006-07-31
申请人： Mitsuaki Katagiri , Takashi Iida , Hiroya Shimizu , Satoshi Isa
发明人： Mitsuaki Katagiri , Takashi Iida , Hiroya Shimizu , Satoshi Isa
IPC分类号： G06F17/50 , H01L23/52
CPC分类号： G06F17/5036 , H05K1/115 , H05K3/0005
摘要： System, method and program for inductance analysis for reducing time for analysis, to cope with increase in the system size, to achieve high accuracy in the analysis. Information on a power supply plane, in a state in which a beginning point of non-coupled current of return current accompanying a signal current is placed in the vicinity of a signal through-hole on the power supply plane, based on position information of said signal through-hole, is received. Potential distribution in the power supply plane is determined and output. The non-coupled inductance from the signal through-hole to the power supply through-hole in the power supply plane is evaluated. In the potential analysis, non-coupled inductance L from the signal through-hole to the power supply through-hole is represented by resistance R. The relationship that a voltage increment ΔV is represented by the product of the non-coupled inductance L and the rate of time change of the current, ΔV=LΔI/Δt, is replaced by the relationship that the voltage V is represented by the product of resistance R and non-coupled current I, V=R×I. Potential analysis is performed by analyzing two-dimensional heat diffusion in the power supply plane assuming that a heat source is placed at a beginning point of the non-coupled current.
摘要翻译：用于电感分析的系统，方法和程序，用于减少分析时间，以应对系统尺寸的增加，在分析中达到高精度。基于所述电源平面的位置信息，在电源平面的信息通过孔附近，在电源平面附近的信号通孔附近设置电源面的信息，信号通孔，被接收。确定并输出电源平面中的电位分布。评估从信号通孔到电源平面中电源通孔的非耦合电感。在电位分析中，由电阻R表示从信号通孔到电源通孔的非耦合电感L.电压增量与Dgr，V之间的关系由非耦合电感L 并且电流的时间变化率＆Dgr; V = L＆Dgr; I /＆Dgr; t被替换为电压V由非电阻R和非耦合电流I的乘积表示的关系，V = R× 一世。假设热源位于非耦合电流的起始点，通过分析供电平面中的二维热扩散来执行潜在分析。

8. 发明授权

US07714424B2 Stacked-type semiconductor package 有权
标题翻译：堆叠型半导体封装
公开(公告)号：US07714424B2
公开(公告)日：2010-05-11
申请号：US12081264
申请日：2008-04-14
申请人： Mitsuaki Katagiri , Atsushi Hiraishi , Fumiyuki Osanai
发明人： Mitsuaki Katagiri , Atsushi Hiraishi , Fumiyuki Osanai
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L23/3128 , H01L25/105 , H01L2224/50 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311
摘要： Corresponding parts to a first path portion in a first signal transmission path to a first semiconductor chip are an interconnection member and a second path portion a second signal transmission path to a second semiconductor chip and are not formed on the first tape. An electric length of the second signal transmission path is allowed to be adjusted independently of the first tape, so that the electric length of the second signal transmission path can be easily made equal to or substantially equal to that of the first signal transmission path.
摘要翻译：与第一半导体芯片的第一信号传输路径中的第一路径部分的对应部分是互连部件和第二路径部分，到第二半导体芯片的第二信号传输路径，并且不形成在第一条带上。允许第二信号传输路径的电长度独立于第一带被调整，使得第二信号传输路径的电长度可以容易地等于或基本等于第一信号传输路径的电长度。

9. 发明申请

US20100095257A1 ELECTROMAGNETIC FIELD ANALYSIS OF SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR CHIP MOUNTED THEREON 审中-公开
标题翻译：具有半导体芯片安装的半导体封装的电磁场分析
公开(公告)号：US20100095257A1
公开(公告)日：2010-04-15
申请号：US12574980
申请日：2009-10-07
申请人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa
发明人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： An electromagnetic field analysis of a semiconductor package with a semiconductor chip mounted thereon can be performed simply with a high accuracy. First modeling and second modeling of the semiconductor package with the semiconductor chip mounted thereon are carried out, thereby performing first and second electromagnetic field analyses. Results of the first and second electromagnetic field analyses are synthesized to determine electrical characteristics of the semiconductor package. Specifically, an inductance analysis is performed with the entire semiconductor chip regarded as a dielectric, thereby determining an inductance component of an equivalent circuit. A capacitance analysis is performed with the semiconductor chip regarded as a dielectric having a metal thin film on its surface, thereby determining a capacitance component of an equivalent circuit. Results of the inductance analysis and the capacitance analysis are synthesized to determine an equivalent circuit.
摘要翻译：可以简单地以高精度进行安装有半导体芯片的半导体封装的电磁场分析。对其上安装有半导体芯片的半导体封装的第一建模和第二建模进行，从而进行第一和第二电磁场分析。合成第一和第二电磁场分析的结果以确定半导体封装的电特性。具体地说，以整个半导体芯片作为电介质进行电感分析，从而确定等效电路的电感分量。在半导体芯片被认为是其表面具有金属薄膜的电介质的情况下进行电容分析，从而确定等效电路的电容分量。电感分析和电容分析的结果被合成以确定等效电路。

10. 发明申请

US20090250801A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090250801A1
公开(公告)日：2009-10-08
申请号：US12385138
申请日：2009-03-31
申请人： Satoshi Isa , Mitsuaki Katagiri , Dai Sasaki
发明人： Satoshi Isa , Mitsuaki Katagiri , Dai Sasaki
IPC分类号： H01L25/16
CPC分类号： H01L25/105 , H01G4/35 , H01G4/40 , H01L23/50 , H01L23/642 , H01L24/48 , H01L25/0657 , H01L25/16 , H01L2224/05554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/48227 , H01L2225/0652 , H01L2225/06541 , H01L2225/06572 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2225/1088 , H01L2924/00014 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device in which a plurality of semiconductor elements are stacked, yet realizing high speed operation of the semiconductor elements. The semiconductor device is provided with semiconductor packages, and a spacer. The semiconductor packages are stacked, with the spacer interposed therebetween. The semiconductor packages have, respectively, package boards, and semiconductor elements mounted on the package boards. The spacer has a plurality of conductive vias and a capacitor element. The semiconductor packages are electrically connected through the conductive vias. The capacitor element is electrically connected, among the conductive vias, to a conductive via that electrically connects the semiconductor element and power supply, and a conductive via that electrically connects the semiconductor element and ground.
摘要翻译：其中堆叠多个半导体元件，但实现半导体元件的高速操作的半导体器件。半导体器件设置有半导体封装和间隔件。堆叠半导体封装，间隔件插入其间。半导体封装分别具有封装板和安装在封装板上的半导体元件。间隔物具有多个导电通孔和电容器元件。半导体封装通过导电通孔电连接。导电通孔中的电容器元件电连接到电连接半导体元件和电源的导电通孔和电连接半导体元件和接地的导电通孔。

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