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1. 发明授权

US09589921B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09589921B2
公开(公告)日：2017-03-07
申请号：US14773817
申请日：2014-03-10
申请人： PS4 Luxco S.a.r.l. , Mitsuaki Katagiri , Yu Hasegawa , Satoshi Isa
发明人： Mitsuaki Katagiri , Yu Hasegawa , Satoshi Isa
IPC分类号： H01L23/00 , H01L23/31 , H01L23/48 , H01L23/498 , H01L25/065 , H01L23/12 , H01L21/56 , H01L21/66 , H05K1/02 , H05K1/14 , H05K1/18
CPC分类号： H01L24/17 , H01L21/561 , H01L22/32 , H01L23/12 , H01L23/3107 , H01L23/3128 , H01L23/481 , H01L23/49816 , H01L23/49838 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L2224/0235 , H01L2224/02375 , H01L2224/0345 , H01L2224/03912 , H01L2224/0392 , H01L2224/0401 , H01L2224/05014 , H01L2224/05015 , H01L2224/05025 , H01L2224/05166 , H01L2224/05548 , H01L2224/05554 , H01L2224/05647 , H01L2224/0603 , H01L2224/06051 , H01L2224/06102 , H01L2224/11462 , H01L2224/11472 , H01L2224/11849 , H01L2224/13006 , H01L2224/13007 , H01L2224/13013 , H01L2224/13014 , H01L2224/13017 , H01L2224/13018 , H01L2224/13021 , H01L2224/13022 , H01L2224/13024 , H01L2224/13025 , H01L2224/13028 , H01L2224/131 , H01L2224/13147 , H01L2224/1403 , H01L2224/14051 , H01L2224/1411 , H01L2224/14131 , H01L2224/14135 , H01L2224/14136 , H01L2224/14177 , H01L2224/14181 , H01L2224/14515 , H01L2224/16145 , H01L2224/16146 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/17181 , H01L2224/17517 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81801 , H01L2224/83102 , H01L2224/83862 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/15311 , H01L2924/3011 , H01L2924/3511 , H05K1/025 , H05K1/141 , H05K1/185 , H05K2201/10734 , H01L2224/81 , H01L2224/83 , H01L2924/00012 , H01L2924/00014 , H01L2224/11 , H01L2924/014 , H01L2924/00
摘要： In one semiconductor device, a semiconductor chip has first and second pad electrodes disposed on the main surface thereof, insulating films that cover the main surface of the semiconductor chip, a rewiring layer that is disposed between the insulating films, and a plurality of external terminals disposed on the top of the insulating film. The plane size of the first pad electrode and the second pad electrode differ from one another, and the first pad electrode and the second pad electrode are connected to any of the plurality of external terminals via the rewiring layer.
摘要翻译：在一个半导体器件中，半导体芯片具有设置在其主表面上的第一和第二焊盘电极，覆盖半导体芯片的主表面的绝缘膜，布置在绝缘膜之间的再布线层和多个外部端子设置在绝缘膜的顶部。第一焊盘电极和第二焊盘电极的平面尺寸彼此不同，并且第一焊盘电极和第二焊盘电极经由重新布线层连接到多个外部端子中的任何一个。

2. 发明申请

US20160027754A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160027754A1
公开(公告)日：2016-01-28
申请号：US14773817
申请日：2014-03-10
申请人： Mitsuaki KATAGIRI , Yu HASEGAWA , Satoshi ISA , PS4 Luxco S.a.r.l.
发明人： Mitsuaki Katagiri , Yu Hasegawa , Satoshi Isa
IPC分类号： H01L23/00 , H01L23/31 , H01L23/48 , H01L23/498
CPC分类号： H01L24/17 , H01L21/561 , H01L22/32 , H01L23/12 , H01L23/3107 , H01L23/3128 , H01L23/481 , H01L23/49816 , H01L23/49838 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L2224/0235 , H01L2224/02375 , H01L2224/0345 , H01L2224/03912 , H01L2224/0392 , H01L2224/0401 , H01L2224/05014 , H01L2224/05015 , H01L2224/05025 , H01L2224/05166 , H01L2224/05548 , H01L2224/05554 , H01L2224/05647 , H01L2224/0603 , H01L2224/06051 , H01L2224/06102 , H01L2224/11462 , H01L2224/11472 , H01L2224/11849 , H01L2224/13006 , H01L2224/13007 , H01L2224/13013 , H01L2224/13014 , H01L2224/13017 , H01L2224/13018 , H01L2224/13021 , H01L2224/13022 , H01L2224/13024 , H01L2224/13025 , H01L2224/13028 , H01L2224/131 , H01L2224/13147 , H01L2224/1403 , H01L2224/14051 , H01L2224/1411 , H01L2224/14131 , H01L2224/14135 , H01L2224/14136 , H01L2224/14177 , H01L2224/14181 , H01L2224/14515 , H01L2224/16145 , H01L2224/16146 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/17181 , H01L2224/17517 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81801 , H01L2224/83102 , H01L2224/83862 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/15311 , H01L2924/3011 , H01L2924/3511 , H05K1/025 , H05K1/141 , H05K1/185 , H05K2201/10734 , H01L2224/81 , H01L2224/83 , H01L2924/00012 , H01L2924/00014 , H01L2224/11 , H01L2924/014 , H01L2924/00
摘要： To provide a semiconductor device with a wafer level package structure that allows for probing while reducing the area occupied by the pad electrodes.[Solution] In the present invention, the following are provided: a semiconductor chip (100) that has first and second pad electrodes (120a, 120b) disposed on the main surface thereof; insulating films (310, 330) that cover the main surface of the semiconductor chip (100); a rewiring layer (320) that is disposed between the insulating films (310, 330); and a plurality of external terminals (340) disposed on the top of the insulating film (330). The plane size of the first pad electrode (120a) and the second pad electrode (120b) differ from one another, and the first pad electrode (120a) and the second pad electrode (120b) are connected to any of the plurality of external terminals (340) via the rewiring layer (320). According to the present invention, because the pad electrodes (120a, 120b) of different sizes are intermixed, probing can be easily performed while reducing the area occupied by the pad electrodes.
摘要翻译：提供具有晶片级封装结构的半导体器件，其允许在减小焊盘电极占据的面积的同时进行探测。 [解决方案]在本发明中，提供了一种半导体芯片（100），其具有设置在其主表面上的第一和第二焊盘电极（120a，120b）覆盖半导体芯片（100）的主表面的绝缘膜（310,330）; 布置在所述绝缘膜（310,330）之间的再布线层（320）; 以及设置在绝缘膜（330）的顶部上的多个外部端子（340）。第一焊盘电极（120a）和第二焊盘电极（120b）的平面尺寸彼此不同，并且第一焊盘电极（120a）和第二焊盘电极（120b）连接到多个外部端子（340）经由重新布线层（320）。根据本发明，由于不同尺寸的焊盘电极（120a，120b）是混合的，所以可以容易地进行探测，同时减少焊盘电极占据的面积。

3. 发明申请

US20110084395A1 Semiconductor package substrate and semiconductor device having the same 审中-公开
标题翻译：半导体封装基板和具有该半导体封装基板的半导体器件
公开(公告)号：US20110084395A1
公开(公告)日：2011-04-14
申请号：US12923712
申请日：2010-10-05
申请人： Hiromasa Takeda , Satoshi Isa , Mitsuaki Katagiri , Ken Iwakura , Yu Hasegawa
发明人： Hiromasa Takeda , Satoshi Isa , Mitsuaki Katagiri , Ken Iwakura , Yu Hasegawa
IPC分类号： H01L23/48
CPC分类号： H01L24/50 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L23/50 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/01005 , H01L2924/01006 , H01L2924/0102 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/00
摘要： A semiconductor device includes a semiconductor chip and a package substrate on which the semiconductor chip is mounted. The package substrate has internal terminals connected to the semiconductor chip, front surface wirings connected to the internal terminals, rear surface wirings connected to external electrodes, and contacts connecting the front surface wiring and rear surface wiring. Out of the plurality of contact, some contacts included in the wirings for signal transmission are disposed near the internal terminals. Thus, a signal led out from the semiconductor chip is immediately taken away from the chip mounting surface of the package substrate. This reduces the floating capacitance between the wirings on the package substrate and chip, thereby improving the signal quality.
摘要翻译：半导体器件包括其上安装半导体芯片的半导体芯片和封装衬底。封装衬底具有连接到半导体芯片的内部端子，连接到内部端子的前表面布线，连接到外部电极的后表面布线以及连接前表面布线和背面布线的触点。在多个接触中，用于信号传输的布线中包括的一些触点设置在内部端子附近。因此，从半导体芯片引出的信号立即从封装基板的芯片安装表面取走。这降低了封装衬底和芯片之间的布线之间的浮动电容，从而提高了信号质量。

4. 发明授权

US08581417B2 Semiconductor device stack with bonding layer and wire retaining member 失效
公开(公告)号：US08581417B2
公开(公告)日：2013-11-12
申请号：US12687311
申请日：2010-01-14
申请人： Yu Hasegawa , Mitsuaki Katagiri , Satoshi Isa , Ken Iwakura , Dai Sasaki
发明人： Yu Hasegawa , Mitsuaki Katagiri , Satoshi Isa , Ken Iwakura , Dai Sasaki
IPC分类号： H01L23/02 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L25/0657 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/48599 , H01L2224/4899 , H01L2224/49171 , H01L2224/73265 , H01L2224/85007 , H01L2224/85051 , H01L2224/85444 , H01L2225/0651 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/20755 , H01L2924/30105 , H01L2924/00 , H01L2224/48132 , H01L2924/00012 , H01L2924/20757 , H01L2924/2075 , H01L2924/20754 , H01L2224/4554 , H01L2224/85399 , H01L2224/05599
摘要： In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip.

5. 发明申请

US20120146242A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120146242A1
公开(公告)日：2012-06-14
申请号：US13323246
申请日：2011-12-12
申请人： Hiroyuki Fujishima , Dai Sasaki , Satoshi Isa , Mitsuaki Katagiri
发明人： Hiroyuki Fujishima , Dai Sasaki , Satoshi Isa , Mitsuaki Katagiri
IPC分类号： H01L23/498
CPC分类号： H01L21/563 , H01L21/561 , H01L23/3128 , H01L23/3185 , H01L23/481 , H01L23/49816 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/83192 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/01029 , H01L2924/15311 , H01L2924/181 , H01L2224/81 , H01L2924/00 , H01L2924/3512 , H01L2924/00012
摘要： A semiconductor device includes a wiring board, a stack of semiconductor chips, and a first sealing member. The wiring board has a first surface. The wiring board includes a first insulating layer formed over the first surface. The first insulating layer has a first opening. The stack of semiconductor chips is mounted over the first surface of the wiring board. The stack of semiconductor chips includes a first semiconductor chip. The first semiconductor chip is closer to the wiring board than the other semiconductor chips. The first sealing member seals at least the first semiconductor chip. The first sealing member includes a protruding portion. The first opening of the insulating layer faces toward the protruding portion of the first sealing member.
摘要翻译：半导体器件包括布线板，半导体芯片堆叠和第一密封构件。布线板具有第一表面。布线板包括形成在第一表面上的第一绝缘层。第一绝缘层具有第一开口。半导体芯片的堆叠被安装在布线板的第一表面上。半导体芯片堆叠包括第一半导体芯片。第一半导体芯片比其他半导体芯片更接近布线板。第一密封构件至少密封第一半导体芯片。第一密封构件包括突出部。绝缘层的第一开口朝向第一密封构件的突出部分。

6. 发明授权

US07777350B2 Semiconductor stack package having wiring extension part which has hole for wiring 有权
标题翻译：半导体堆叠封装，具有布线延伸部分，其具有用于布线的孔
公开(公告)号：US07777350B2
公开(公告)日：2010-08-17
申请号：US12219839
申请日：2008-07-29
申请人： Dai Sasaki , Mitsuaki Katagiri , Satoshi Isa
发明人： Dai Sasaki , Mitsuaki Katagiri , Satoshi Isa
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40 , H01L23/02 , H01L27/146 , H01L27/148
CPC分类号： H01L25/0657 , H01L23/3128 , H01L24/06 , H01L24/45 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/32145 , H01L2224/45015 , H01L2224/45144 , H01L2224/48227 , H01L2224/4824 , H01L2224/4911 , H01L2224/85399 , H01L2225/0651 , H01L2225/06517 , H01L2225/06527 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor stack package includes a first printed wiring board; a plurality of semiconductor chips stacked on the first printed wiring board, wherein among the semiconductor chips, the uppermost semiconductor chip has an electrode pad for providing power supply, a ground pad for providing grounding, and a signal pad for signal transmission in a center area on the upper surface of the chip; connection lands formed on the first printed wiring board on the outside of the stacked semiconductor chips; a wiring extension part which is formed on the uppermost semiconductor chip, and has wiring circuits extending from the center to the periphery thereof, wherein at least one of the electrode pad and the ground pad is electrically connected to one end of one of the wiring circuits; and a wire for connecting the other end of the relevant wiring circuit of the wiring extension part and one of the connection lands on the first printed wiring board.
摘要翻译：半导体堆叠封装包括第一印刷线路板; 堆叠在第一印刷线路板上的多个半导体芯片，其中在半导体芯片中，最上半导体芯片具有用于提供电源的电极焊盘，用于提供接地的接地焊盘和用于在中心区域中进行信号传输的信号焊盘在芯片的上表面; 在叠层半导体芯片的外侧的第一印刷布线板上形成的连接焊盘; 布线延伸部，形成在最上半导体芯片上，并且具有从中心延伸到其周边的布线电路，其中电极焊盘和接地焊盘中的至少一个电连接到一个布线电路的一端 ; 以及用于连接布线延伸部分的相关布线电路的另一端和第一印刷布线板上的一个连接焊盘的导线。

7. 发明申请

US20100193929A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100193929A1
公开(公告)日：2010-08-05
申请号：US12686567
申请日：2010-01-13
申请人： Ken IWAKURA , Mitsuaki Katagiri , Satoshi Isa , Dai Sasaki
发明人： Ken IWAKURA , Mitsuaki Katagiri , Satoshi Isa , Dai Sasaki
IPC分类号： H01L23/522
CPC分类号： H01L23/49833 , H01L23/3128 , H01L24/06 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L2224/0401 , H01L2224/05554 , H01L2224/05599 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2224/85399 , H01L2225/0651 , H01L2225/06527 , H01L2225/06572 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/014 , H01L2924/07802 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011 , H01L2224/45099 , H01L2924/00 , H01L2224/32145 , H01L2924/00012
摘要： A semiconductor device includes a package board, first connectors, and a first multi-layered structure. The package board has first and second regions. The first connectors are in the first region. The first multi-layered structure includes a first semiconductor chip, a wiring board, and second to fifth connectors. The first semiconductor chip has first and second surfaces. The first surface covers the second region. The wiring board has third and fourth surfaces. The third surface is fixed to the second surface. The second to fourth connectors are in the center regions of the second to fourth surfaces, respectively. The fifth connectors are aligned along opposing two sides of the fourth surface. The second connectors electrically connect to the third connectors. The third connectors electrically connect to the fourth and fifth connectors. The first connectors electrically connect to the fourth and fifth connectors.
摘要翻译：半导体器件包括封装板，第一连接器和第一多层结构。封装板具有第一和第二区域。第一个连接器位于第一个区域。第一多层结构包括第一半导体芯片，布线板和第二至第五连接器。第一半导体芯片具有第一和第二表面。第一个表面覆盖第二个区域。布线板具有第三和第四表面。第三表面固定到第二表面。第二至第四连接器分别位于第二至第四表面的中心区域。第五连接器沿着第四表面的相对的两侧排列。第二连接器电连接到第三连接器。第三连接器电连接到第四和第五连接器。第一连接器电连接到第四和第五连接器。

8. 发明授权

US07694245B2 Method for designing semiconductor package, system for aiding to design semiconductor package, and computer program product therefor 失效
标题翻译：半导体封装设计方法，半导体封装设计系统及其计算机程序产品
公开(公告)号：US07694245B2
公开(公告)日：2010-04-06
申请号：US11710965
申请日：2007-02-27
申请人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Yoji Nishio , Satoshi Isa , Satoshi Itaya
发明人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Yoji Nishio , Satoshi Isa , Satoshi Itaya
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L23/50 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for designing a semiconductor package is disclosed, wherein the semiconductor package comprises a semiconductor chip and an adjustment target. A first target variable is calculated in consideration of a first transition state where an output level of the semiconductor chip changes from a low level to a high level. A second target variable is calculated in consideration of a second transition state where an output level of the semiconductor chip changes from the high level to the low level. Inferior one of the first and the second target variables is selected as a main target variable. The main target variable and a predetermined constraint represented in frequency domain are compared to decide design guidelines for the adjustment target.
摘要翻译：公开了一种用于设计半导体封装的方法，其中半导体封装包括半导体芯片和调整对象。考虑到半导体芯片的输出电平从低电平变为高电平的第一转变状态来计算第一目标变量。考虑到半导体芯片的输出电平从高电平变为低电平的第二过渡状态来计算第二目标变量。选择第一和第二目标变量之一作为主要目标变量。比较主要目标变量和在频域中表示的预定约束，以决定调整目标的设计指南。

9. 发明申请

US20090140409A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090140409A1
公开(公告)日：2009-06-04
申请号：US12327649
申请日：2008-12-03
申请人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa , Dai Sasaki
发明人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa , Dai Sasaki
IPC分类号： H01L23/48
CPC分类号： H01L23/3135 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/03 , H01L2224/06135 , H01L2224/06136 , H01L2224/32145 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48011 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/484 , H01L2224/48599 , H01L2224/48699 , H01L2224/49 , H01L2224/73215 , H01L2224/73265 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/30105 , H01L2924/30107 , H01L2924/00012 , H01L2224/32225 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor device includes a substrate having bumps on the backside thereof, a first semiconductor chip mounted on the surface of the substrate, a second semiconductor chip mounted on the first semiconductor chip above the surface of the substrate, a first bonding wire having a length L1 for connecting the first semiconductor chip to the substrate, a second bonding wire having a length L2 (where L2>L1) for connecting the second semiconductor chip to the substrate, a first resin seal having a dielectric constant ε1 for sealing the first bonding wire, and a second resin seal having a dielectric constant ε2 (where ε2
摘要翻译：半导体器件包括其背面具有凸块的衬底，安装在衬底表面上的第一半导体芯片，安装在衬底表面上的第一半导体芯片上的第二半导体芯片，具有长度L1 为了将第一半导体芯片连接到基板，具有用于将第二半导体芯片连接到基板的长度L2（其中L2> L1）的第二接合线，具有用于密封第一接合线的介电常数ε1的第一树脂密封件，以及具有用于密封第二接合线的介电常数ε2（其中ε2 <ε1）的第二树脂密封件。长度L1和L2之间的关系以及介电常数ε1和ε2由ε1= epsilon2（L2 / L1）2的等式定义。

10. 发明申请

US20070033553A1 Inductance analysis system and method and program therefor 有权
标题翻译：电感分析系统及其方法和程序
公开(公告)号：US20070033553A1
公开(公告)日：2007-02-08
申请号：US11495711
申请日：2006-07-31
申请人： Mitsuaki Katagiri , Takashi Iida , Hiroya Shimizu , Satoshi Isa
发明人： Mitsuaki Katagiri , Takashi Iida , Hiroya Shimizu , Satoshi Isa
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H05K1/115 , H05K3/0005
摘要： System, method and program for inductance analysis for reducing time for analysis, to cope with increase in the system size, to achieve high accuracy in the analysis. Information on a power supply plane, in a state in which a beginning point of non-coupled current of return current accompanying a signal current is placed in the vicinity of a signal through-hole on the power supply plane, based on position information of said signal through-hole, is received. Potential distribution in the power supply plane is determined and output. The non-coupled inductance from the signal through-hole to the power supply through-hole in the power supply plane is evaluated. In the potential analysis, non-coupled inductance L from the signal through-hole to the power supply through-hole is represented by resistance R. The relationship that a voltage increment ΔV is represented by the product of the non-coupled inductance L and the rate of time change of the current, ΔV=LΔI/Δt, is replaced by the relationship that the voltage V is represented by the product of resistance R and non-coupled current I, V=R×I. Potential analysis is performed by analyzing two-dimensional heat diffusion in the power supply plane assuming that a heat source is placed at a beginning point of the non-coupled current.
摘要翻译：用于电感分析的系统，方法和程序，用于减少分析时间，以应对系统尺寸的增加，在分析中达到高精度。基于所述电源平面的位置信息，在电源平面的信息通过孔附近，在电源平面附近的信号通孔附近设置电源面的信息，信号通孔，被接收。确定并输出电源平面中的电位分布。评估从信号通孔到电源平面中电源通孔的非耦合电感。在电位分析中，由电阻R表示从信号通孔到电源通孔的非耦合电感L.电压增量DeltaV由非耦合电感L和电流的时间变化DeltaV = LDeltaI / Deltat由电压R和非耦合电流I，V = RxI的乘积表示的电压代替。假设热源位于非耦合电流的起始点，通过分析供电平面中的二维热扩散来执行潜在分析。

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