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    • 4. 发明授权
    • Wafer inspection system and method thereof
    • 晶圆检查系统及其方法
    • US07601555B2
    • 2009-10-13
    • US11132352
    • 2005-05-19
    • Kwang-soo KimKoung-su ShinSeung-min ChoiYu-han Jeong
    • Kwang-soo KimKoung-su ShinSeung-min ChoiYu-han Jeong
    • H01L21/00
    • G06T7/0004G01R31/2831G06T2207/30148
    • A wafer inspection system includes an electrical testing part to control a probe to be in contact with a pad of a wafer to perform a predetermined electrical test, a defect detecting part to detect a defect in the wafer passing through the electrical test, a defect sorting part to sort the defect detected in the defect detecting part by an in-line method, and a defective determining part to determine whether the wafer is a defective according to a sorting result of the defect sorting part. The wafer inspection system and a method thereof can determine the kinds of the defect in the wafer during a fabricating procedure, so that it is possible to instantly and correctly determine whether the die on the wafer is a defective.
    • 晶片检查系统包括电测试部分,用于控制探针与晶片的焊盘接触以执行预定的电测试;缺陷检测部分,用于检测通过电测试的晶片中的缺陷,缺陷分类 通过在线方式对在缺陷检测部分中检测到的缺陷进行分类的部分,以及根据缺陷分类部分的分类结果确定晶片是否有缺陷的缺陷确定部分。 晶片检查系统及其方法可以在制造过程中确定晶片中的缺陷的种类,使得可以立即且正确地确定晶片上的裸片是否有缺陷。
    • 6. 发明授权
    • Fabrication method and structure for providing a recessed channel in a nonvolatile memory device
    • 用于在非易失性存储器件中提供凹陷通道的制造方法和结构
    • US07531409B2
    • 2009-05-12
    • US11583796
    • 2006-10-20
    • Sang-Pil SimKwang-soo KimChan-Kwang ParkHeon-Kyu Lee
    • Sang-Pil SimKwang-soo KimChan-Kwang ParkHeon-Kyu Lee
    • H01L21/336
    • H01L27/11524H01L21/28273H01L27/0207H01L27/115H01L27/11519H01L27/11521
    • A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially includes the recessed region and forming first and second trenches that differ in depth, intersect the recessed region, and link with each other. The method includes forming a device isolation layer having rugged bottoms and defining an active region by filling an insulating material in the first and second trenches. The method includes forming a gate insulation layer on the semiconductor substrate of the active region including the recessed region and forming a gate structure on the gate insulation layer, to fill the recessed region, the gate structure including a floating gate, an intergate insulating pattern, and a control gate.
    • 制造非易失性存储器件的方法包括制备包括单元阵列区域的半导体衬底。 该方法还包括通过蚀刻半导体衬底在电池阵列区域中形成凹陷区域。 该方法包括蚀刻半导体衬底的至少一部分,其部分地包括凹陷区域并形成深度不同,与凹陷区域相交并彼此连接的第一和第二沟槽。 该方法包括形成具有粗糙底部的器件隔离层,并且通过在第一和第二沟槽中填充绝缘材料来限定有源区。 该方法包括在包括凹陷区域的有源区的半导体衬底上形成栅极绝缘层,并在栅极绝缘层上形成栅极结构,以填充凹陷区域,栅极结构包括浮置栅极,栅极间绝缘图案, 和控制门。
    • 9. 发明申请
    • FABRICATION METHOD AND STRUCTURE FOR PROVIDING A RECESSED CHANNEL IN A NONVOLATILE MEMORY DEVICE
    • 用于在非易失性存储器件中提供被记录的通道的制造方法和结构
    • US20090200596A1
    • 2009-08-13
    • US12417127
    • 2009-04-02
    • Sang-Pil SimKwang-soo KimChan-Kwang ParkHeon-Kyu Lee
    • Sang-Pil SimKwang-soo KimChan-Kwang ParkHeon-Kyu Lee
    • H01L29/788
    • H01L27/11524H01L27/0207H01L27/115H01L27/11519H01L27/11521H01L29/40114
    • A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially includes the recessed region and forming first and second trenches that differ in depth, intersect the recessed region, and link with each other. The method includes forming a device isolation layer having rugged bottoms and defining an active region by filling an insulating material in the first and second trenches. The method includes forming a gate insulation layer on the semiconductor substrate of the active region including the recessed region and forming a gate structure on the gate insulation layer, to fill the recessed region, the gate structure including a floating gate, an intergate insulating pattern, and a control gate.
    • 制造非易失性存储器件的方法包括制备包括单元阵列区域的半导体衬底。 该方法还包括通过蚀刻半导体衬底在电池阵列区域中形成凹陷区域。 该方法包括蚀刻半导体衬底的至少一部分,其部分地包括凹陷区域并形成深度不同,与凹陷区域相交并彼此连接的第一和第二沟槽。 该方法包括形成具有粗糙底部的器件隔离层,并且通过在第一和第二沟槽中填充绝缘材料来限定有源区。 该方法包括在包括凹陷区域的有源区的半导体衬底上形成栅极绝缘层,并在栅极绝缘层上形成栅极结构,以填充凹陷区域,栅极结构包括浮置栅极,栅极间绝缘图案, 和控制门。