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1. 发明授权

US5422295A Method for forming a semiconductor memory device having a vertical multi-layered storage electrode 失效
标题翻译：用于形成具有垂直多层存储电极的半导体存储器件的方法
公开(公告)号：US5422295A
公开(公告)日：1995-06-06
申请号：US164671
申请日：1993-12-10
申请人： Young-jae Choi , Tae-young Chung , Jong-woo Park , Young-pil Kim
发明人： Young-jae Choi , Tae-young Chung , Jong-woo Park , Young-pil Kim
IPC分类号： H01L27/04 , H01L21/02 , H01L21/265 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L28/86 , H01L21/26533 , H01L28/87 , H01L28/88
摘要： A manufacturing method for a semiconductor memory device including a capacitor having a double fin-shaped structure is provided, wherein a storage electrode is formed by applying a thick planar material capable of being wet-etched between the double fins consisting of conductive layers. The storage electrode is formed by forming a thin, high temperature oxide film having an etching rate which is great. Thus, the resulting memory cell's topography is improved and damage to the storage electrode is decreased.
摘要翻译：提供了一种包括具有双鳍状结构的电容器的半导体存储器件的制造方法，其中通过在由导电层组成的双翅片之间施加能够被湿蚀刻的厚平面材料形成存储电极。存储电极通过形成蚀刻速率大的薄的高温氧化膜形成。因此，所得到的存储单元的形貌得到改善，并且对存储电极的损坏降低。

2. 发明申请

US20080088025A1 SEMICONDUCTOR DEVICES HAVING ELONGATED CONTACT PLUGS 有权
标题翻译：具有短接触片的半导体器件
公开(公告)号：US20080088025A1
公开(公告)日：2008-04-17
申请号：US11954349
申请日：2007-12-12
申请人： Cheol-ju Yun , Tae-young Chung , Dong-jun Lee
发明人： Cheol-ju Yun , Tae-young Chung , Dong-jun Lee
IPC分类号： H01L23/48
CPC分类号： H01L27/10888 , H01L21/76804 , H01L21/76829 , H01L21/76834 , H01L21/76897 , H01L27/10855 , H01L27/10885 , H01L27/10891
摘要： A method of manufacturing a semiconductor device includes forming conductive structures on a substrate. Each of the conductive structures has a line shape that extends along a first direction parallel to the substrate. Insulating spacers are formed on upper sidewalls of the conductive structures. An insulating interlayer is formed that covers the conductive structures. A portion of the insulating interlayer between the conductive structures is etched to form a contact hole. An upper portion of the contact hole is larger than a lower portion thereof. The upper portion of the contact hole has a first width along the first direction and a second width along a second direction parallel to the substrate and substantially perpendicular to the first direction. The first width is substantially larger than the second width. The contact hole is filled with a conductive material to form a contact plug.
摘要翻译：制造半导体器件的方法包括在衬底上形成导电结构。每个导电结构具有沿平行于基板的第一方向延伸的线状。绝缘垫片形成在导电结构的上侧壁上。形成覆盖导电结构的绝缘中间层。导电结构之间的绝缘中间层的一部分被蚀刻以形成接触孔。接触孔的上部大于其下部。接触孔的上部具有沿着第一方向的第一宽度和沿着平行于基底并基本上垂直于第一方向的第二方向的第二宽度。第一宽度基本上大于第二宽度。接触孔填充有导电材料以形成接触塞。

3. 发明授权

US07326613B2 Methods of manufacturing semiconductor devices having elongated contact plugs 有权
标题翻译：制造具有细长接触插塞的半导体器件的方法
公开(公告)号：US07326613B2
公开(公告)日：2008-02-05
申请号：US11096129
申请日：2005-03-31
申请人： Cheol-ju Yun , Tae-young Chung , Dong-jun Lee
发明人： Cheol-ju Yun , Tae-young Chung , Dong-jun Lee
IPC分类号： H01L21/8242
CPC分类号： H01L27/10888 , H01L21/76804 , H01L21/76829 , H01L21/76834 , H01L21/76897 , H01L27/10855 , H01L27/10885 , H01L27/10891
摘要： A method of manufacturing a semiconductor device includes forming conductive structures on a substrate. Each of the conductive structures has a line shape that extends along a first direction parallel to the substrate. Insulating spacers are formed on upper sidewalls of the conductive structures. An insulating interlayer is formed that covers the conductive structures. A portion of the insulating interlayer between the conductive structures is etched to form a contact hole. An upper portion of the contact hole is larger than a lower portion thereof. The upper portion of the contact hole has a first width along the first direction and a second width along a second direction parallel to the substrate and substantially perpendicular to the first direction. The first width is substantially larger than the second width. The contact hole is filled with a conductive material to form a contact plug.
摘要翻译：制造半导体器件的方法包括在衬底上形成导电结构。每个导电结构具有沿平行于基板的第一方向延伸的线状。绝缘垫片形成在导电结构的上侧壁上。形成覆盖导电结构的绝缘中间层。导电结构之间的绝缘中间层的一部分被蚀刻以形成接触孔。接触孔的上部大于其下部。接触孔的上部具有沿着第一方向的第一宽度和沿着平行于基底并基本上垂直于第一方向的第二方向的第二宽度。第一宽度基本上大于第二宽度。接触孔填充有导电材料以形成接触塞。

4. 发明申请

US20050218408A1 Semiconductor devices having elongated contact plugs and methods of manufacturing the same 有权
标题翻译：具有细长接触插塞的半导体器件及其制造方法
公开(公告)号：US20050218408A1
公开(公告)日：2005-10-06
申请号：US11096129
申请日：2005-03-31
申请人： Cheol-ju Yun , Tae-young Chung , Dong-jun Lee
发明人： Cheol-ju Yun , Tae-young Chung , Dong-jun Lee
IPC分类号： H01L27/108 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L29/12
CPC分类号： H01L27/10888 , H01L21/76804 , H01L21/76829 , H01L21/76834 , H01L21/76897 , H01L27/10855 , H01L27/10885 , H01L27/10891
摘要： A method of manufacturing a semiconductor device includes forming conductive structures on a substrate. Each of the conductive structures has a line shape that extends along a first direction parallel to the substrate. Insulating spacers are formed on upper sidewalls of the conductive structures. An insulating interlayer is formed that covers the conductive structures. A portion of the insulating interlayer between the conductive structures is etched to form a contact hole. An upper portion of the contact hole is larger than a lower portion thereof. The upper portion of the contact hole has a first width along the first direction and a second width along a second direction parallel to the substrate and substantially perpendicular to the first direction. The first width is substantially larger than the second width. The contact hole is filled with a conductive material to form a contact plug.
摘要翻译：制造半导体器件的方法包括在衬底上形成导电结构。每个导电结构具有沿平行于基板的第一方向延伸的线状。绝缘垫片形成在导电结构的上侧壁上。形成覆盖导电结构的绝缘中间层。导电结构之间的绝缘中间层的一部分被蚀刻以形成接触孔。接触孔的上部大于其下部。接触孔的上部具有沿着第一方向的第一宽度和沿着平行于基底并基本上垂直于第一方向的第二方向的第二宽度。第一宽度基本上大于第二宽度。接触孔填充有导电材料以形成接触塞。

5. 发明授权

US08101515B2 Methods of manufacturing semiconductor devices having contact plugs in insulation layers 有权
标题翻译：制造在绝缘层中具有接触插塞的半导体器件的方法
公开(公告)号：US08101515B2
公开(公告)日：2012-01-24
申请号：US12766137
申请日：2010-04-23
申请人： Joon-ho Sung , Ju-yong Lee , Mi-kyung Park , Tae-young Chung
发明人： Joon-ho Sung , Ju-yong Lee , Mi-kyung Park , Tae-young Chung
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/60 , H01L21/74 , H01L21/8238 , H01L21/8234 , H01L21/8242 , H01L21/20
CPC分类号： H01L21/76897 , H01L21/76885 , H01L27/10855 , H01L27/10885 , H01L27/10888
摘要： Methods of manufacturing semiconductor devices are provided in which a first contact plug is formed on a first active region in a substrate and a second contact plug is formed on a second active region in the substrate. A height of an upper surface of the second contact plug from the substrate is greater than a height of an upper surface of the first contact plug from the substrate. A third contact plug is formed on the second contact plug. A first spacer is formed on a side surface of the third contact plug. A third interlayer insulation layer is formed that covers the third contact plug. The third interlayer insulation layer is patterned to form a third opening that exposes the first contact plug. A fourth contact plug is formed in the third opening that is electrically connected to the first contact plug.
摘要翻译：提供制造半导体器件的方法，其中第一接触插塞形成在衬底中的第一有源区上，并且第二接触插塞形成在衬底中的第二有源区上。第二接触塞从基板的上表面的高度大于第一接触塞从基板的上表面的高度。在第二接触插塞上形成第三接触插塞。第一间隔件形成在第三接触插塞的侧表面上。形成覆盖第三接触插塞的第三层间绝缘层。图案化第三层间绝缘层以形成暴露第一接触插塞的第三开口。第四接触插塞形成在电连接到第一接触插塞的第三开口中。

6. 发明申请

US20100210087A1 Methods of Manufacturing Semiconductor Devices Having Contact Plugs in Insulation Layers 有权
标题翻译：制造具有接触插头在绝缘层中的半导体器件的方法
公开(公告)号：US20100210087A1
公开(公告)日：2010-08-19
申请号：US12766137
申请日：2010-04-23
申请人： Joon-ho Sung , Ju-yong Lee , Mi-kyung Park , Tae-young Chung
发明人： Joon-ho Sung , Ju-yong Lee , Mi-kyung Park , Tae-young Chung
IPC分类号： H01L21/768 , H01L21/02
CPC分类号： H01L21/76897 , H01L21/76885 , H01L27/10855 , H01L27/10885 , H01L27/10888
摘要： Methods of manufacturing semiconductor devices are provided in which a first contact plug is formed on a first active region in a substrate and a second contact plug is formed on a second active region in the substrate. A height of an upper surface of the second contact plug from the substrate is greater than a height of an upper surface of the first contact plug from the substrate. A third contact plug is formed on the second contact plug. A first spacer is formed on a side surface of the third contact plug. A third interlayer insulation layer is formed that covers the third contact plug. The third interlayer insulation layer is patterned to form a third opening that exposes the first contact plug. A fourth contact plug is formed in the third opening that is electrically connected to the first contact plug.
摘要翻译：提供制造半导体器件的方法，其中第一接触插塞形成在衬底中的第一有源区上，并且第二接触插塞形成在衬底中的第二有源区上。第二接触塞从基板的上表面的高度大于第一接触塞从基板的上表面的高度。在第二接触插塞上形成第三接触插塞。第一间隔件形成在第三接触插塞的侧表面上。形成覆盖第三接触插塞的第三层间绝缘层。图案化第三层间绝缘层以形成暴露第一接触插塞的第三开口。第四接触插塞形成在电连接到第一接触插塞的第三开口中。

7. 发明申请

US20090104749A1 Methods of Manufacturing Semiconductor Devices Having Contact Plugs in Insulation Layers 有权
标题翻译：制造具有接触插头在绝缘层中的半导体器件的方法
公开(公告)号：US20090104749A1
公开(公告)日：2009-04-23
申请号：US12108012
申请日：2008-04-23
申请人： Joon-Ho Sung , Ju-yong Lee , Mi-Kyung Park , Tae-young Chung
发明人： Joon-Ho Sung , Ju-yong Lee , Mi-Kyung Park , Tae-young Chung
IPC分类号： H01L21/02 , H01L21/4763
CPC分类号： H01L21/76897 , H01L21/76885 , H01L27/10855 , H01L27/10885 , H01L27/10888
摘要： Methods of manufacturing semiconductor devices are provided in which a first contact plug is formed on a first active region in a substrate and a second contact plug is formed on a second active region in the substrate. A height of an upper surface of the second contact plug from the substrate is greater than a height of an upper surface of the first contact plug from the substrate. A third contact plug is formed on the second contact plug. A first spacer is formed on a side surface of the third contact plug. A third interlayer insulation layer is formed that covers the third contact plug. The third interlayer insulation layer is patterned to form a third opening that exposes the first contact plug. A fourth contact plug is formed in the third opening that is electrically connected to the first contact plug.
摘要翻译：提供制造半导体器件的方法，其中第一接触插塞形成在衬底中的第一有源区上，并且第二接触插塞形成在衬底中的第二有源区上。第二接触塞从基板的上表面的高度大于第一接触塞从基板的上表面的高度。在第二接触插塞上形成第三接触插塞。第一间隔件形成在第三接触插塞的侧表面上。形成覆盖第三接触插塞的第三层间绝缘层。图案化第三层间绝缘层以形成暴露第一接触插塞的第三开口。第四接触插塞形成在电连接到第一接触插塞的第三开口中。

8. 发明授权

US07732323B2 Methods of manufacturing semiconductor devices having contact plugs in insulation layers 有权
标题翻译：制造在绝缘层中具有接触插塞的半导体器件的方法
公开(公告)号：US07732323B2
公开(公告)日：2010-06-08
申请号：US12108012
申请日：2008-04-23
申请人： Joon-ho Sung , Ju-yong Lee , Mi-kyung Park , Tae-young Chung
发明人： Joon-ho Sung , Ju-yong Lee , Mi-kyung Park , Tae-young Chung
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/60 , H01L21/74 , H01L21/8238 , H01L21/8234 , H01L21/8242 , H01L21/20
CPC分类号： H01L21/76897 , H01L21/76885 , H01L27/10855 , H01L27/10885 , H01L27/10888
摘要： Methods of manufacturing semiconductor devices are provided in which a first contact plug is formed on a first active region in a substrate and a second contact plug is formed on a second active region in the substrate. A height of an upper surface of the second contact plug from the substrate is greater than a height of an upper surface of the first contact plug from the substrate. A third contact plug is formed on the second contact plug. A first spacer is formed on a side surface of the third contact plug. A third interlayer insulation layer is formed that covers the third contact plug. The third interlayer insulation layer is patterned to form a third opening that exposes the first contact plug. A fourth contact plug is formed in the third opening that is electrically connected to the first contact plug.
摘要翻译：提供制造半导体器件的方法，其中第一接触插塞形成在衬底中的第一有源区上，并且第二接触插塞形成在衬底中的第二有源区上。第二接触塞从基板的上表面的高度大于第一接触塞从基板的上表面的高度。在第二接触插塞上形成第三接触插塞。第一间隔件形成在第三接触插塞的侧表面上。形成覆盖第三接触插塞的第三层间绝缘层。图案化第三层间绝缘层以形成暴露第一接触插塞的第三开口。第四接触插塞形成在电连接到第一接触插塞的第三开口中。

9. 发明授权

US07547938B2 Semiconductor devices having elongated contact plugs 有权
标题翻译：具有细长接触插头的半导体器件
公开(公告)号：US07547938B2
公开(公告)日：2009-06-16
申请号：US11954349
申请日：2007-12-12
申请人： Cheol-ju Yun , Tae-young Chung , Dong-jun Lee
发明人： Cheol-ju Yun , Tae-young Chung , Dong-jun Lee
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/10888 , H01L21/76804 , H01L21/76829 , H01L21/76834 , H01L21/76897 , H01L27/10855 , H01L27/10885 , H01L27/10891
摘要： A method of manufacturing a semiconductor device includes forming conductive structures on a substrate. Each of the conductive structures has a line shape that extends along a first direction parallel to the substrate. Insulating spacers are formed on upper sidewalls of the conductive structures. An insulating interlayer is formed that covers the conductive structures. A portion of the insulating interlayer between the conductive structures is etched to form a contact hole. An upper portion of the contact hole is larger than a lower portion thereof. The upper portion of the contact hole has a first width along the first direction and a second width along a second direction parallel to the substrate and substantially perpendicular to the first direction. The first width is substantially larger than the second width. The contact hole is filled with a conductive material to form a contact plug.
摘要翻译：制造半导体器件的方法包括在衬底上形成导电结构。每个导电结构具有沿平行于基板的第一方向延伸的线状。绝缘垫片形成在导电结构的上侧壁上。形成覆盖导电结构的绝缘中间层。导电结构之间的绝缘中间层的一部分被蚀刻以形成接触孔。接触孔的上部大于其下部。接触孔的上部具有沿着第一方向的第一宽度和沿着平行于基底并基本上垂直于第一方向的第二方向的第二宽度。第一宽度基本上大于第二宽度。接触孔填充有导电材料以形成接触塞。

10. 发明授权

US06890841B2 Methods of forming integrated circuit memory devices that include a plurality of landing pad holes that are arranged in a staggered pattern and integrated circuit memory devices formed thereby 有权
标题翻译：形成集成电路存储器件的方法包括以交错图案布置的多个着陆焊盘孔和由此形成的集成电路存储器件
公开(公告)号：US06890841B2
公开(公告)日：2005-05-10
申请号：US10442481
申请日：2003-05-21
申请人： Kyu-hyun Lee , Tae-young Chung , Chang-hyun Cho , Yang-keun Park , Sang-bum Kim
发明人： Kyu-hyun Lee , Tae-young Chung , Chang-hyun Cho , Yang-keun Park , Sang-bum Kim
IPC分类号： H01L21/28 , H01L21/02 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L21/20 , H01L29/94
CPC分类号： H01L28/60 , H01L21/76895 , H01L28/91 , Y10S257/908
摘要： An integrated circuit memory device is formed by forming an interlevel insulating layer on a substrate. A plurality of storage node contact holes are formed in the interlayer insulating layer and are arranged in a pattern. A plurality of contact plugs are formed in the plurality of storage node contact holes, respectively. A material layer is formed on the interlevel insulating layer that has a plurality of landing pad holes that expose the plurality of contact plugs, respectively, the plurality of landing pad holes are arranged in a pattern that is offset with respect to the pattern of the storage node contact holes. A plurality of landing pads are formed in the plurality of landing pad holes and are connected to the plurality of contact plugs, respectively. A plurality of storage nodes are formed that are connected to the plurality of landing pads, respectively.
摘要翻译：通过在衬底上形成层间绝缘层来形成集成电路存储器件。在层间绝缘层中形成多个存储节点接触孔，并以图案排列。多个接触插塞分别形成在多个存储节点接触孔中。在层间绝缘层上形成材料层，其具有分别露出多个接触插塞的多个着陆焊盘孔，多个着陆焊盘孔以相对于存储器的图案偏移的图案布置节点接触孔。多个着陆焊盘形成在多个着陆焊盘孔中，分别连接到多个接触插塞。形成分别连接到多个着陆焊盘的多个存储节点。

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