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1. 发明授权

US08659464B2 Analog-digital converter and converting method using clock delay 失效
标题翻译：模数转换器和使用时钟延迟的转换方法
公开(公告)号：US08659464B2
公开(公告)日：2014-02-25
申请号：US13593301
申请日：2012-08-23
申请人： Young-deuk Jeon , Woo Seok Yang , Tae Moon Roh , Jong-Kee Kwon , Jongdae Kim
发明人： Young-deuk Jeon , Woo Seok Yang , Tae Moon Roh , Jong-Kee Kwon , Jongdae Kim
IPC分类号： H03M1/34
CPC分类号： H03M1/462
摘要： The present inventive concept relates to an analog-digital converter. The analog-digital converter includes a clock generating unit generating a clock signal; a clock delay adjusting unit outputting one of a first clock signal to a Kth clock signal according to a control signal; a capacitive digital-analog converting unit outputting a difference between the analog signal and a reference signal; a comparison unit judging whether an output of the capacitive digital-analog converting unit is 0, a positive number, or a negative number, in response to an output of the clock delay adjusting unit; and an SAR logic unit transferring an output of the comparison unit to the capacitive digital-analog converting unit in response to an output of the clock delay adjusting unit and performing a successive approximation operation to output the N-bit digital signal.
摘要翻译：本发明构思涉及一种模数转换器。模拟数字转换器包括产生时钟信号的时钟产生单元; 时钟延迟调整单元，根据控制信号将第一时钟信号中的一个输出到第K个时钟信号; 输出模拟信号和参考信号之间的差的电容数字 - 模拟转换单元; 比较单元，响应于时钟延迟调整单元的输出，判定电容数字 - 模拟转换单元的输出是0，正数还是负数; 以及SAR逻辑单元，响应于时钟延迟调整单元的输出，将比较单元的输出传送到电容数字 - 模拟转换单元，并执行逐次逼近操作以输出N位数字信号。

2. 发明申请

US20130156069A1 PROCESS INDEPENDENT TEMPERATURE SENSOR BASED ON OSCILLATOR 有权
标题翻译：基于振荡器的过程独立温度传感器
公开(公告)号：US20130156069A1
公开(公告)日：2013-06-20
申请号：US13620594
申请日：2012-09-14
申请人： Seok Ju Yun , Young-deuk Jeon , Tae Moon Roh , Jong-Kee Kwon , Woo Seok Yang , Jongdae Kim
发明人： Seok Ju Yun , Young-deuk Jeon , Tae Moon Roh , Jong-Kee Kwon , Woo Seok Yang , Jongdae Kim
IPC分类号： G01K7/00
CPC分类号： G01K7/32
摘要： The inventive concept discloses a new temperature sensor structure based on oscillator which is insensitive to a process change and improves an error rate of temperature output. The temperature sensor based on oscillator compares an oscillator circuit structure insensitive to a temperature change with an oscillator circuit structure having a frequency change in proportion to a temperature change to output a relative difference between the two oscillator circuit structures and thereby it is compensated itself. In the temperature sensor based on oscillator, a problem of performance reduction due to an external environment and a process deviation of temperature sensor is improved and an output distortion and temperature nonlinearity are effectively improved. Thus, since the temperature sensor based on oscillator has a structure of high performance, low power and low cost, it can be variously used in a detection equipment of temperature environment.
摘要翻译：本发明的概念公开了一种基于振荡器的新型温度传感器结构，其对过程变化不敏感并且提高了温度输出的误差率。基于振荡器的温度传感器将对温度变化不敏感的振荡器电路结构与具有与温度变化成比例的频率变化的振荡器电路结构进行比较，以输出两个振荡器电路结构之间的相对差，由此自身进行补偿。在基于振荡器的温度传感器中，提高了由于外部环境导致的性能降低和温度传感器的工艺偏差的问题，并且有效地提高了输出失真和温度非线性。因此，由于基于振荡器的温度传感器具有高性能，低功率和低成本的结构，因此可以被多种用于温度环境的检测设备中。

3. 发明授权

US09068896B2 Process independent temperature sensor based on oscillator 有权
标题翻译：基于振荡器的独立温度传感器
公开(公告)号：US09068896B2
公开(公告)日：2015-06-30
申请号：US13620594
申请日：2012-09-14
申请人： Seok Ju Yun , Young-deuk Jeon , Tae Moon Roh , Jong-Kee Kwon , Woo Seok Yang , Jongdae Kim
发明人： Seok Ju Yun , Young-deuk Jeon , Tae Moon Roh , Jong-Kee Kwon , Woo Seok Yang , Jongdae Kim
IPC分类号： G01K11/00 , G01K7/32
CPC分类号： G01K7/32
摘要： The inventive concept discloses a new temperature sensor structure based on oscillator which is insensitive to a process change and improves an error rate of temperature output. The temperature sensor based on oscillator compares an oscillator circuit structure insensitive to a temperature change with an oscillator circuit structure having a frequency change in proportion to a temperature change to output a relative difference between the two oscillator circuit structures and thereby it is compensated itself. In the temperature sensor based on oscillator, a problem of performance reduction due to an external environment and a process deviation of temperature sensor is improved and an output distortion and temperature nonlinearity are effectively improved. Thus, since the temperature sensor based on oscillator has a structure of high performance, low power and low cost, it can be variously used in a detection equipment of temperature environment.
摘要翻译：本发明的概念公开了一种基于振荡器的新型温度传感器结构，其对过程变化不敏感并且提高了温度输出的误差率。基于振荡器的温度传感器将对温度变化不敏感的振荡器电路结构与具有与温度变化成比例的频率变化的振荡器电路结构进行比较，以输出两个振荡器电路结构之间的相对差，由此自身进行补偿。在基于振荡器的温度传感器中，提高了由于外部环境导致的性能降低和温度传感器的工艺偏差的问题，并且有效地提高了输出失真和温度非线性。因此，由于基于振荡器的温度传感器具有高性能，低功率和低成本的结构，因此可以被多种用于温度环境的检测设备中。

4. 发明授权

US09077287B2 Sound detecting circuit and amplifier circuit thereof 有权
标题翻译：声音检测电路及其放大电路
公开(公告)号：US09077287B2
公开(公告)日：2015-07-07
申请号：US13531437
申请日：2012-06-22
申请人： Yi-Gyeong Kim , Min-Hyung Cho , Tae Moon Roh , Jong-Kee Kwon , Woo Seok Yang , Jongdae Kim
发明人： Yi-Gyeong Kim , Min-Hyung Cho , Tae Moon Roh , Jong-Kee Kwon , Woo Seok Yang , Jongdae Kim
IPC分类号： H03F99/00 , H03F3/08
CPC分类号： H03F3/08
摘要： Disclosed is a sound detecting circuit which includes a sensing unit configured to generate an AC signal in response to a sound pressure level of a sound signal; an amplification unit configured to amplify the AC signal; and a bias voltage generating unit configured to generate a bias voltage to be provided to the amplification unit. The bias voltage generating unit comprises a current source configured to provide a power current; and a current-voltage converting circuit configured to convert the power current into the bias voltage and to reduce a noise due to the power current.
摘要翻译：公开了一种声音检测电路，其包括：感测单元，被配置为响应于声音信号的声压级产生AC信号; 放大单元，被配置为放大AC信号; 以及偏置电压产生单元，被配置为产生要提供给所述放大单元的偏置电压。偏置电压产生单元包括被配置为提供功率电流的电流源; 以及电流电压转换电路，被配置为将功率电流转换成偏置电压并且减少由于功率电流引起的噪声。

5. 发明申请

US20110153878A1 MEMORY SYSTEM AND INTEGRATED MANAGEMENT METHOD FOR PLURALITY OF DMA CHANNELS 有权
标题翻译：用于DMA通道多重的存储系统和集成管理方法
公开(公告)号：US20110153878A1
公开(公告)日：2011-06-23
申请号：US12882141
申请日：2010-09-14
申请人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.
摘要翻译：提供了用于多个直接存储器访问（DMA）通道的存储器系统和集成管理方法。存储器系统包括存储器控制器，其与存储器交换数据并且具有物理上彼此分离的多个通道;以及DMA控制器，其具有彼此物理上彼此分离并与存储器的多个通道接触的多个DMA通道控制器，并且经由多个DMA通道和存储器控制器与存储器交换数据。

6. 发明申请

US20110022767A1 DMA CONTROLLER WITH INTERRUPT CONTROL PROCESSOR 审中-公开
标题翻译：具有中断控制处理器的DMA控制器
公开(公告)号：US20110022767A1
公开(公告)日：2011-01-27
申请号：US12843801
申请日：2010-07-26
申请人： Ik Jae CHUN , Chun Gi Lyuh , Jung Hee Suk , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Ik Jae CHUN , Chun Gi Lyuh , Jung Hee Suk , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F13/28 , G06F13/24
CPC分类号： G06F13/32
摘要： Provided is a direct memory access (DMA) controller having an interrupt control processor that can process DMA transmission-related interrupts according to a control program modifiable by a user. The DMA controller includes the interrupt control processor that can process a DMA transmission-related interrupt and a DMA request interrupt transmitted from peripheral devices and control the DMA channel through the control program that can be modified by the user, so that DMA channel control and relevant interrupt processing loads caused by a plurality of DMA data transmissions are reduced, and the flexibility of DMA channel control and interrupt processing in control of the DMA controller is provided to the user.
摘要翻译：提供了具有中断控制处理器的直接存储器访问（DMA）控制器，其可以根据用户可修改的控制程序来处理与DMA传输相关的中断。 DMA控制器包括可处理DMA传输相关中断的中断控制处理器和从外围设备发送的DMA请求中断，并通过可由用户修改的控制程序控制DMA通道，从而使DMA通道控制和相关减少由多个DMA数据传输引起的中断处理负载，并且向用户提供DMA控制的DMA通道控制和中断处理的灵活性。

7. 发明授权

US08205021B2 Memory system and integrated management method for plurality of DMA channels 有权
标题翻译：用于多个DMA通道的存储系统和集成管理方法
公开(公告)号：US08205021B2
公开(公告)日：2012-06-19
申请号：US12882141
申请日：2010-09-14
申请人： Ik Jae Chun , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Ik Jae Chun , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.
摘要翻译：提供了用于多个直接存储器访问（DMA）通道的存储器系统和集成管理方法。存储器系统包括存储器控制器，其与存储器交换数据并且具有物理上彼此分离的多个通道;以及DMA控制器，其具有彼此物理上彼此分离并与存储器的多个通道接触的多个DMA通道控制器，并且经由多个DMA通道和存储器控制器与存储器交换数据。

8. 发明申请

US20110145549A1 PIPELINED DECODING APPARATUS AND METHOD BASED ON PARALLEL PROCESSING 审中-公开
标题翻译：基于并行处理的管道解码设备和方法
公开(公告)号：US20110145549A1
公开(公告)日：2011-06-16
申请号：US12862565
申请日：2010-08-24
申请人： Jung Hee SUK , Chun Gi Lyuh , Ik Jae Chun , Se Wan Heo , Soon II Yeo , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Jung Hee SUK , Chun Gi Lyuh , Ik Jae Chun , Se Wan Heo , Soon II Yeo , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： H04N19/436 , H04N19/44
摘要： An apparatus and method for decoding moving images based on parallel processing are provided. The apparatus for decoding images based on parallel processing can improve operational performance by pipelining massive-data transmission between processors while performing context-adaptive variable length decoding (CAVLD), inverse quantization (IQ), inverse transformation (IT), motion compensation (MC), intra prediction (IP) and deblocking filter (DF) operations in parallel in units of pluralities of macroblocks (MBs).
摘要翻译：提供了一种基于并行处理来解码运动图像的装置和方法。用于基于并行处理的图像解码装置可以通过在执行上下文自适应可变长度解码（CAVLD），逆量化（IQ），逆变换（IT），运动补偿（MC））之间流水线处理大规模数据传输来提高操作性能，，帧内预测（IP）和去块滤波器（DF）操作以多个宏块（MB）为单位并行。

9. 发明授权

US08407276B2 Apparatus for calculating absolute difference 有权
标题翻译：用于计算绝对差的装置
公开(公告)号：US08407276B2
公开(公告)日：2013-03-26
申请号：US12843550
申请日：2010-07-26
申请人： Chun Gi Lyuh , Ik Jae Chun , Jung Hee Suk , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Chun Gi Lyuh , Ik Jae Chun , Jung Hee Suk , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F7/50
CPC分类号： G06F7/544
摘要： Provided is an apparatus for calculating an absolute difference capable of efficiently performing an absolute difference using an adder. The apparatus for calculating an absolute difference includes a comparator comparing values of two integers, first and second selectors each selecting and outputting one of the two integers according to the comparison results of the comparator, an inverter complementing the result value selected by the second selector; and an adder adding up the result value selected by the first selector, the value complemented by the inverter, and 1.
摘要翻译：提供了一种用于计算能够使用加法器有效地执行绝对差的绝对差的装置。用于计算绝对差的装置包括比较器，比较器比较两个整数的值，第一和第二选择器，每个选择器根据比较器的比较结果选择和输出两个整数中的一个;逆变器，补偿由第二选择器选择的结果值; 和加法器将由第一选择器选择的结果值相加，由逆变器补充的值，以及1。

10. 发明申请

US20120226831A1 MEMORY SYSTEM AND INTEGRATED MANAGEMENT METHOD FOR PLURALITY OF DMA CHANNELS 审中-公开
标题翻译：用于DMA通道多重的存储系统和集成管理方法
公开(公告)号：US20120226831A1
公开(公告)日：2012-09-06
申请号：US13471236
申请日：2012-05-14
申请人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.
摘要翻译：提供了用于多个直接存储器访问（DMA）通道的存储器系统和集成管理方法。存储器系统包括存储器控制器，其与存储器交换数据并且具有物理上彼此分离的多个通道;以及DMA控制器，其具有彼此物理上彼此分离并与存储器的多个通道接触的多个DMA通道控制器，并且经由多个DMA通道和存储器控制器与存储器交换数据。

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