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1. 发明授权

US07974375B2 Linear phase detector and clock/data recovery circuit thereof 有权
标题翻译：线性相位检测器及其时钟/数据恢复电路
公开(公告)号：US07974375B2
公开(公告)日：2011-07-05
申请号：US11843785
申请日：2007-08-23
申请人： Chul-Woo Kim , Seok-Soo Yoon , Young-Ho Kwak , In-Ho Lee , Ki-Hong Kim
发明人： Chul-Woo Kim , Seok-Soo Yoon , Young-Ho Kwak , In-Ho Lee , Ki-Hong Kim
IPC分类号： H03D3/24
CPC分类号： H03L7/087 , H03D13/00 , H03L7/0891
摘要： A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.
摘要翻译：线性相位检测器包括响应于接收的数据信号和恢复的时钟信号而工作的上/下脉冲发生器。相位检测器产生具有与接收的数据信号的转变和恢复的时钟信号的边沿之间的相位差成比例的脉冲宽度的上升和下降脉冲。通过使用与相位误差成比例的线性相位检测器产生上升和下降脉冲，数据信号被有效地恢复，甚至具有显着抖动的数据信号。

2. 发明授权

US08442178B2 Linear phase detector and clock/data recovery circuit thereof 有权
标题翻译：线性相位检测器及其时钟/数据恢复电路
公开(公告)号：US08442178B2
公开(公告)日：2013-05-14
申请号：US13152497
申请日：2011-06-03
申请人： Chul-Woo Kim , Seok-Soo Yoon , Young-Ho Kwak , In-Ho Lee , Ki-Hong Kim
发明人： Chul-Woo Kim , Seok-Soo Yoon , Young-Ho Kwak , In-Ho Lee , Ki-Hong Kim
IPC分类号： H03D3/24
CPC分类号： H03L7/087 , H03D13/00 , H03L7/0891
摘要： A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.
摘要翻译：线性相位检测器包括响应于接收的数据信号和恢复的时钟信号而工作的上/下脉冲发生器。相位检测器产生具有与接收的数据信号的转变和恢复的时钟信号的边沿之间的相位差成比例的脉冲宽度的上升和下降脉冲。通过使用与相位误差成比例的线性相位检测器产生上升和下降脉冲，数据信号被有效地恢复，甚至具有显着抖动的数据信号。

3. 发明申请

US20090189652A1 Frequency Multiplier 有权
标题翻译：频率乘数
公开(公告)号：US20090189652A1
公开(公告)日：2009-07-30
申请号：US11659023
申请日：2005-07-27
申请人： Chul-Woo Kim , Jin-Han Kim , Seok-Ryung Yoon , Young-Ho Kwak , Seok-Soo Yoon
发明人： Chul-Woo Kim , Jin-Han Kim , Seok-Ryung Yoon , Young-Ho Kwak , Seok-Soo Yoon
IPC分类号： H03B19/00
CPC分类号： G06F7/68
摘要： A frequency multiplier is disclosed. A plurality of voltage regulators each regulate levels of voltages at first and second common nodes in response to a corresponding one of input signals from a voltage-controlled delay line. An input buffer charges the first node or discharges the second node in response to a feedback signal. An output buffer regulates a level of a voltage at an output node and outputs a frequency-multiplied clock signal and the feedback signal corresponding to the voltage level of the output node. A discharge circuit discharges the first node before a rising edge of each of the input signals from the voltage-controlled delay line is inputted. A charge circuit charges the second node before the rising edge of each of the input signals from the voltage-controlled delay line is inputted.
摘要翻译：公开了一种倍频器。多个电压调节器响应于来自电压控制延迟线的输入信号中的相应一个，调节第一和第二公共节点处的电压电平。输入缓冲器对第一节点进行充电或响应于反馈信号对第二节点进行放电。输出缓冲器调节输出节点处的电压电平，并输出倍频时钟信号和对应于输出节点电压电平的反馈信号。在输入来自压控延迟线的每个输入信号的上升沿之前，放电电路对第一节点放电。在输入来自压控延迟线的每个输入信号的上升沿之前，充电电路对第二节点充电。

4. 发明授权

US07830184B2 Frequency multiplier 有权
标题翻译：倍频器
公开(公告)号：US07830184B2
公开(公告)日：2010-11-09
申请号：US11659023
申请日：2005-07-27
申请人： Chul-Woo Kim , Jin-Han Kim , Seok-Ryung Yoon , Young-Ho Kwak , Seok-Soo Yoon
发明人： Chul-Woo Kim , Jin-Han Kim , Seok-Ryung Yoon , Young-Ho Kwak , Seok-Soo Yoon
IPC分类号： H03B19/00
CPC分类号： G06F7/68
摘要： A frequency multiplier is disclosed. A plurality of voltage regulators each regulate levels of voltages at first and second common nodes in response to a corresponding one of input signals from a voltage-controlled delay line. An input buffer charges the first node or discharges the second node in response to a feedback signal. An output buffer regulates a level of a voltage at an output node and outputs a frequency-multiplied clock signal and the feedback signal corresponding to the voltage level of the output node. A discharge circuit discharges the first node before a rising edge of each of the input signals from the voltage-controlled delay line is inputted. A charge circuit charges the second node before the rising edge of each of the input signals from the voltage-controlled delay line is inputted.
摘要翻译：公开了一种倍频器。多个电压调节器响应于来自电压控制延迟线的输入信号中的相应一个，调节第一和第二公共节点处的电压电平。输入缓冲器对第一节点进行充电或响应于反馈信号对第二节点进行放电。输出缓冲器调节输出节点处的电压电平，并输出倍频时钟信号和对应于输出节点电压电平的反馈信号。在输入来自压控延迟线的每个输入信号的上升沿之前，放电电路对第一节点放电。在输入来自压控延迟线的每个输入信号的上升沿之前，充电电路对第二节点充电。

5. 发明授权

US07106117B2 Delayed clock signal generator 有权
标题翻译：延时时钟信号发生器
公开(公告)号：US07106117B2
公开(公告)日：2006-09-12
申请号：US10910644
申请日：2004-08-04
申请人： Gun-Ok Jung , Jin-Han Kim , Sung-Bae Park , Chul-Woo Kim , Seok-Soo Yoon , Seok-Ryoung Yoon
发明人： Gun-Ok Jung , Jin-Han Kim , Sung-Bae Park , Chul-Woo Kim , Seok-Soo Yoon , Seok-Ryoung Yoon
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K5/135 , H03K2005/00156 , H03K2005/00286
摘要： A device which may be configured to generate delayed clock signals by a specified phase difference, which may include a clock generator circuit for generating at least one clock signal, a delayed clock signal generator for delaying the at least one clock signal, a phase detect circuit for generating a selecting signal based on the amount of phase delay detected according to a half-cycle (π), and in comparison with the clock signal, a phase interpolation circuit for controlling the delay time of the delayed clock signals and interpolating the delayed clock signals, and a selecting circuit which outputs the delayed clock signal delayed by a specified phase difference.
摘要翻译：一种可被配置为通过指定的相位差产生延迟的时钟信号的装置，其可以包括用于产生至少一个时钟信号的时钟发生器电路，用于延迟所述至少一个时钟信号的延迟时钟信号发生器，相位检测电路用于基于根据半周期（pi）检测到的相位延迟量来生成选择信号，并且与时钟信号相比，相位插值电路用于控制延迟的时钟信号的延迟时间并内插延迟的时钟信号，以及输出延迟了指定相位差的延迟时钟信号的选择电路。

6. 发明申请

US20050052211A1 Delayed clock signal generator 有权
标题翻译：延时时钟信号发生器
公开(公告)号：US20050052211A1
公开(公告)日：2005-03-10
申请号：US10910644
申请日：2004-08-04
申请人： Gun-Ok Jung , Jin-Han Kim , Sung-Bae Park , Chul-Woo Kim , Seok-Soo Yoon , Seok-Ryoung Yoon
发明人： Gun-Ok Jung , Jin-Han Kim , Sung-Bae Park , Chul-Woo Kim , Seok-Soo Yoon , Seok-Ryoung Yoon
IPC分类号： G06F1/06 , H03H11/26 , H03K5/00 , H03K5/05 , H03K5/13 , H03K5/135 , H03K5/15 , H03K5/26 , H03L7/081 , H04L7/02
CPC分类号： H03K5/133 , H03K5/135 , H03K2005/00156 , H03K2005/00286
摘要： A device which may be configured to generate delayed clock signals by a specified phase difference, which may include a clock generator circuit for generating at least one clock signal, a delayed clock signal generator for delaying the at least one clock signal, a phase detect circuit for generating a selecting signal based on the amount of phase delay detected according to a half-cycle (π), and in comparison with the clock signal, a phase interpolation circuit for controlling the delay time of the delayed clock signals and interpolating the delayed clock signals, and a selecting circuit which outputs the delayed clock signal delayed by a specified phase difference.
摘要翻译：一种可以被配置为通过指定的相位差产生延迟的时钟信号的装置，其可以包括用于产生至少一个时钟信号的时钟发生器电路，用于延迟所述至少一个时钟信号的延迟时钟信号发生器，相位检测电路用于基于根据半周期（pi）检测到的相位延迟量来生成选择信号，并且与时钟信号相比，相位插值电路用于控制延迟的时钟信号的延迟时间并内插延迟的时钟信号，以及输出延迟了指定相位差的延迟时钟信号的选择电路。

7. 发明授权

US08989662B2 Method and apparatus for automatic bluetooth connection in a mobile communication terminal 有权
标题翻译：移动通信终端中自动蓝牙连接的方法和装置
公开(公告)号：US08989662B2
公开(公告)日：2015-03-24
申请号：US11583397
申请日：2006-10-19
申请人： Chul-Woo Kim
发明人： Chul-Woo Kim
IPC分类号： H04B7/00 , H04W12/06 , H04L29/06 , H04M1/725 , H04W84/18
CPC分类号： H04W12/06 , H04L63/0492 , H04M1/7253 , H04M1/7258 , H04M2250/02 , H04W12/04 , H04W84/18
摘要： A method of automatically connecting to a peripheral Bluetooth device and service in a mobile communication terminal having a Bluetooth module is provided. Upon input of a key, it is determined whether the key includes a Bluetooth mode key. If the key includes the Bluetooth mode key, the terminal transitions to a Bluetooth mode. A Bluetooth device or service corresponding to the key as a short key is detected and connected.
摘要翻译：提供了一种在具有蓝牙模块的移动通信终端中自动连接到外围蓝牙设备和服务的方法。一键输入后，确定键是否包括蓝牙模式键。如果键包括蓝牙模式键，则终端转换到蓝牙模式。检测并连接与密钥对应的蓝牙设备或服务作为短信。

8. 发明申请

US20140117536A1 WIRING SUBSTRATE, TAPE PACKAGE HAVING THE SAME, AND DISPLAY DEVICE HAVING THE SAME 审中-公开
标题翻译：接线基板，具有该基板的带包装及其相关的显示装置
公开(公告)号：US20140117536A1
公开(公告)日：2014-05-01
申请号：US13693142
申请日：2012-12-04
申请人： Ji-Hwan HWANG , Dong-Han Kim , Chul-Woo Kim , Chung-Ye Chung , Kwang-Jin Bae
发明人： Ji-Hwan HWANG , Dong-Han Kim , Chul-Woo Kim , Chung-Ye Chung , Kwang-Jin Bae
IPC分类号： H05K1/02 , H01L23/00
CPC分类号： H05K1/0277 , H01L23/49838 , H01L23/4985 , H01L24/50 , H01L2924/14 , H01L2924/181 , H05K1/111 , H05K1/189 , H05K2201/097 , H05K2201/09709 , H05K2201/10128 , H05K2201/10674 , Y02P70/611 , H01L2924/00
摘要： A wiring substrate includes a base film, a plurality of first wirings and a plurality of second wirings. The base film has a chip-mounting region configured for mounting a semiconductor chip thereon. The first wirings extend in a first direction from inside the chip-mounting region to outside the chip-mounting region, and include first connection end portions extending in a second direction different from the first direction. The first connection end portions may be formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip. The second wirings extend in the first direction from inside the chip-mounting region to outside the chip-mounting region, and include second connection end portions extending in the opposite direction to the second direction in which the first connection end portions extend, and the second connection end portions may be formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip.
摘要翻译：布线基板包括基膜，多个第一布线和多个第二布线。基膜具有芯片安装区域，用于在其上安装半导体芯片。第一布线沿芯片安装区域内的第一方向延伸到芯片安装区域的外部，并且包括沿与第一方向不同的第二方向延伸的第一连接端部。第一连接端部可以形成在芯片安装区域的内部并且被配置为电连接到半导体芯片。所述第二配线从所述芯片安装区域的内部朝向所述芯片安装区域的外部沿所述第一方向延伸，并且包括沿与所述第一连接端部延伸的所述第二方向相反的方向延伸的第二连接端部，连接端部可以形成在芯片安装区域内部，并且被配置为电连接到半导体芯片。

9. 发明申请

US20110227221A1 ELECTRONIC DEVICE HAVING INTERCONNECTIONS AND PADS 有权
标题翻译：具有互连和贴片的电子设备
公开(公告)号：US20110227221A1
公开(公告)日：2011-09-22
申请号：US13028836
申请日：2011-02-16
申请人： Ji-Yong Park , Hee-Seok Lee , Chul-Woo Kim , Sang-Gui Jo , Kwang-Jin Bae , Seung-Hwan Kim
发明人： Ji-Yong Park , Hee-Seok Lee , Chul-Woo Kim , Sang-Gui Jo , Kwang-Jin Bae , Seung-Hwan Kim
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L24/03 , H01L23/49811 , H01L23/49816 , H01L23/49822 , H01L24/05 , H01L24/06 , H01L24/13 , H01L2224/02166 , H01L2224/0401 , H01L2224/05553 , H01L2224/05558 , H01L2224/05559 , H01L2224/0557 , H01L2224/0603 , H01L2224/13006 , H01L2224/13007 , H01L2224/1403 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2224/05552 , H01L2924/00
摘要： An electronic device includes first and second interconnections formed on a first surface of a substrate and spaced apart from each other. The electronic device includes a first insulating material layer disposed on the substrate including the first and second interconnections and including a first opening exposing a predetermined region of the first interconnection. The electronic device further includes a first pad filling the first opening and having a greater width than the first opening. The first pad covers at least a part of the second interconnection adjacent to one end of the first interconnection, and the first pad is electrically insulated from the second interconnection by the first insulating material layer.
摘要翻译：电子设备包括形成在基板的第一表面上并彼此间隔开的第一和第二互连。电子设备包括设置在基板上的第一绝缘材料层，包括第一和第二互连，并且包括暴露第一互连的预定区域的第一开口。电子设备还包括填充第一开口并且具有比第一开口更大的宽度的第一垫。第一焊盘覆盖与第一互连的一端相邻的第二互连的至少一部分，并且第一焊盘通过第一绝缘材料层与第二互连电绝缘。

10. 发明授权

US08339561B2 Wiring substrate, tape package having the same, and display device having the same 有权
标题翻译：配线基板，具有该布线基板的带包装及其显示装置
公开(公告)号：US08339561B2
公开(公告)日：2012-12-25
申请号：US12353317
申请日：2009-01-14
申请人： Ji-Hwan Hwang , Dong-Han Kim , Chul-Woo Kim , Chung-Ye Chung , Kwang-Jin Bae
发明人： Ji-Hwan Hwang , Dong-Han Kim , Chul-Woo Kim , Chung-Ye Chung , Kwang-Jin Bae
IPC分类号： G02F1/1345
CPC分类号： H05K1/0277 , H01L23/49838 , H01L23/4985 , H01L24/50 , H01L2924/14 , H01L2924/181 , H05K1/111 , H05K1/189 , H05K2201/097 , H05K2201/09709 , H05K2201/10128 , H05K2201/10674 , Y02P70/611 , H01L2924/00
摘要： A wiring substrate includes a base film, a plurality of first wirings and a plurality of second wirings. The base film has a chip-mounting region configured for mounting a semiconductor chip thereon. The first wirings extend in a first direction from inside the chip-mounting region to outside the chip-mounting region, and include first connection end portions extending in a second direction different from the first direction. The first connection end portions may be formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip. The second wirings extend in the first direction from inside the chip-mounting region to outside the chip-mounting region, and include second connection end portions extending in the opposite direction to the second direction in which the first connection end portions extend, and the second connection end portions may be formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip.
摘要翻译：布线基板包括基膜，多个第一布线和多个第二布线。基膜具有芯片安装区域，用于在其上安装半导体芯片。第一布线沿芯片安装区域内的第一方向延伸到芯片安装区域的外部，并且包括沿与第一方向不同的第二方向延伸的第一连接端部。第一连接端部可以形成在芯片安装区域的内部并且被配置为电连接到半导体芯片。所述第二配线从所述芯片安装区域的内部朝向所述芯片安装区域的外侧沿所述第一方向延伸，并且包括沿与所述第一连接端部延伸的所述第二方向相反的方向延伸的第二连接端部，连接端部可以形成在芯片安装区域内部，并且被配置为电连接到半导体芯片。

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