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1. 发明申请

US20120064680A1 METHODS OF FORMING A CAPACITOR STRUCTURE AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME 审中-公开
标题翻译：形成电容器结构的方法和使用其制造半导体器件的方法
公开(公告)号：US20120064680A1
公开(公告)日：2012-03-15
申请号：US13228867
申请日：2011-09-09
申请人： Jung-Min Oh , Bo-Un Yoon , Gyu-Wan Choi , Kun-Tack Lee , Dae-Hyuk Kang , Im-Soo Park , Dong-Seok Lee , Young-Hoo Kim
发明人： Jung-Min Oh , Bo-Un Yoon , Gyu-Wan Choi , Kun-Tack Lee , Dae-Hyuk Kang , Im-Soo Park , Dong-Seok Lee , Young-Hoo Kim
IPC分类号： H01L21/336 , H01G13/06
CPC分类号： H01G13/06
摘要： A method of forming a capacitor structure and manufacturing a semiconductor device, the method of forming a capacitor structure including sequentially forming a first mold layer, a supporting layer, a second mold layer, an anti-bowing layer, and a third mold layer on a substrate having a conductive region thereon; partially removing the third mold layer, the anti-bowing layer, the second mold layer, the supporting layer, and the first mold layer to form a first opening exposing the conductive region; forming a lower electrode on a sidewall and bottom of the first opening, the lower electrode being electrically connected to the conductive region; further removing the third mold layer, the anti-bowing layer, and the second mold layer; partially removing the supporting layer to form a supporting layer pattern; removing the first mold layer; and sequentially forming a dielectric layer and upper electrode on the lower electrode and the supporting layer pattern.
摘要翻译：一种形成电容器结构并制造半导体器件的方法，形成电容器结构的方法包括：依次形成第一模具层，支撑层，第二模具层，抗弯曲层和第三模具层衬底，其上具有导电区域; 部分地去除第三模具层，抗弯曲层，第二模具层，支撑层和第一模具层，以形成暴露导电区域的第一开口; 在所述第一开口的侧壁和底部形成下电极，所述下电极电连接到所述导电区域; 进一步去除第三模具层，抗弯曲层和第二模具层; 部分地去除支撑层以形成支撑层图案; 去除第一模具层; 并且在下电极和支撑层图案上依次形成电介质层和上电极。

2. 发明申请

US20110159660A1 Methods of Forming Integrated Circuit Capacitors Having Sidewall Supports and Capacitors Formed Thereby 有权
标题翻译：形成具有侧壁支撑和形成电容器的集成电路电容器的方法
公开(公告)号：US20110159660A1
公开(公告)日：2011-06-30
申请号：US12906184
申请日：2010-10-18
申请人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
发明人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
IPC分类号： H01L21/02 , H01G13/00
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/87
摘要： In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
摘要翻译：在形成电容器的方法中，可以在基板上形成包括第一绝缘材料的第一模层图案。第一模层图案可以具有沟槽。可以在沟槽中形成包括第二绝缘材料的支撑层。第二绝缘材料可以具有相对于第一绝缘材料的蚀刻选择性。可以在第一模层图案和支撑层图案上形成第二模层。可以通过第二模具层和第一模具层图案形成下部电极。下电极可以与支撑层图案的侧壁接触。可以去除第一模层图案和第二模层。电介质层和上电极可以形成在下电极和支撑层图案上。

3. 发明申请

US20110306197A1 Methods of Manufacturing Semiconductor Devices 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20110306197A1
公开(公告)日：2011-12-15
申请号：US13156729
申请日：2011-06-09
申请人： Young-Hoo Kim , Bo-Un Yoon , Kun-Tack Lee , Dae-Hyuk Kang , Im-Soo Park
发明人： Young-Hoo Kim , Bo-Un Yoon , Kun-Tack Lee , Dae-Hyuk Kang , Im-Soo Park
IPC分类号： H01L21/3205
CPC分类号： H01L28/82
摘要： Method of manufacturing semiconductor device are provided including forming an insulation layer having a pad on a substrate; forming an etch stop layer on the insulation layer and the pad; forming a mold structure having at least one mold layer on the etch stop layer; forming a first supporting layer on the mold structure; etching the first supporting layer and the mold structure to form a first opening exposing the etch stop layer; forming a spacer on a sidewall of the first opening; etching the etch stop layer using the spacer as an etching mask to form a second opening, different from the first opening, exposing a first portion of the pad having a first associated area; etching the etch stop layer using the spacer as an etching mask to form a third opening exposing a second portion of the pad having a second associated area, the second associated area being larger than the first associated area; and etching the mold structure to form a fourth opening having a width larger than a width of the third opening.
摘要翻译：提供制造半导体器件的方法，包括在衬底上形成具有衬垫的绝缘层; 在所述绝缘层和所述焊盘上形成蚀刻停止层; 形成在所述蚀刻停止层上具有至少一个模制层的模具结构; 在模具结构上形成第一支撑层; 蚀刻第一支撑层和模具结构以形成暴露蚀刻停止层的第一开口; 在所述第一开口的侧壁上形成间隔件; 使用所述间隔物作为蚀刻掩模来蚀刻所述蚀刻停止层，以形成不同于所述第一开口的第二开口，暴露所述焊盘的具有第一相关区域的第一部分; 使用所述间隔物作为蚀刻掩模来蚀刻所述蚀刻停止层，以形成暴露所述焊盘的具有第二相关区域的第二部分的第三开口，所述第二相关区域大于所述第一相关区域; 并且蚀刻所述模具结构以形成宽度大于所述第三开口的宽度的第四开口。

4. 发明授权

US08119476B2 Methods of forming integrated circuit capacitors having sidewall supports and capacitors formed thereby 有权
标题翻译：形成具有侧壁支撑件的集成电路电容器和由此形成的电容器的方法
公开(公告)号：US08119476B2
公开(公告)日：2012-02-21
申请号：US12906184
申请日：2010-10-18
申请人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
发明人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/87
摘要： In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
摘要翻译：在形成电容器的方法中，可以在基板上形成包括第一绝缘材料的第一模层图案。第一模层图案可以具有沟槽。可以在沟槽中形成包括第二绝缘材料的支撑层。第二绝缘材料可以具有相对于第一绝缘材料的蚀刻选择性。可以在第一模层图案和支撑层图案上形成第二模层。可以通过第二模具层和第一模具层图案形成下部电极。下电极可以与支撑层图案的侧壁接触。可以去除第一模层图案和第二模层。电介质层和上电极可以形成在下电极和支撑层图案上。

5. 发明授权

US08766343B2 Integrated circuit capacitors having sidewall supports 有权
标题翻译：具有侧壁支撑件的集成电路电容器
公开(公告)号：US08766343B2
公开(公告)日：2014-07-01
申请号：US13356032
申请日：2012-01-23
申请人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
发明人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/87
摘要： In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
摘要翻译：在形成电容器的方法中，可以在基板上形成包括第一绝缘材料的第一模层图案。第一模层图案可以具有沟槽。可以在沟槽中形成包括第二绝缘材料的支撑层。第二绝缘材料可以具有相对于第一绝缘材料的蚀刻选择性。可以在第一模层图案和支撑层图案上形成第二模层。可以通过第二模具层和第一模具层图案形成下部电极。下电极可以与支撑层图案的侧壁接触。可以去除第一模层图案和第二模层。电介质层和上电极可以形成在下电极和支撑层图案上。

6. 发明申请

US20120112317A1 INTEGRATED CIRCUIT CAPACITORS HAVING SIDEWALL SUPPORTS 有权
标题翻译：集成电路电容器具有支持端口
公开(公告)号：US20120112317A1
公开(公告)日：2012-05-10
申请号：US13356032
申请日：2012-01-23
申请人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
发明人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
IPC分类号： H01L21/02
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/87
摘要： In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
摘要翻译：在形成电容器的方法中，可以在基板上形成包括第一绝缘材料的第一模层图案。第一模层图案可以具有沟槽。可以在沟槽中形成包括第二绝缘材料的支撑层。第二绝缘材料可以具有相对于第一绝缘材料的蚀刻选择性。可以在第一模层图案和支撑层图案上形成第二模层。可以通过第二模具层和第一模具层图案形成下部电极。下电极可以与支撑层图案的侧壁接触。可以去除第一模层图案和第二模层。电介质层和上电极可以形成在下电极和支撑层图案上。

7. 发明授权

US08344385B2 Vertical-type semiconductor device 有权
标题翻译：垂直型半导体器件
公开(公告)号：US08344385B2
公开(公告)日：2013-01-01
申请号：US12872270
申请日：2010-08-31
申请人： Young-Hoo Kim , Hyo-San Lee , Sang-Won Bae , Bo-Un Yoon , Kun-Tack Lee
发明人： Young-Hoo Kim , Hyo-San Lee , Sang-Won Bae , Bo-Un Yoon , Kun-Tack Lee
IPC分类号： H01L29/06 , H01L29/792
CPC分类号： H01L27/11578 , H01L27/11556 , H01L27/11582
摘要： In a vertical-type non-volatile memory device, an insulation layer pattern is provided on a substrate, the insulation layer pattern having a linear shape. Single-crystalline semiconductor patterns are provided on the substrate to make contact with both sidewalls of the insulation layer pattern, the single-crystalline semiconductor patterns having a pillar shape that extends in a vertical direction relative to the substrate. A tunnel oxide layer is provided on the single-crystalline semiconductor pattern. A lower electrode layer pattern is provided on the tunnel oxide layer and on the substrate. A plurality of insulation interlayer patterns is provided on the lower electrode layer pattern, the insulation interlayer patterns being spaced apart from one another by a predetermined distance along the single-crystalline semiconductor pattern. A charge-trapping layer and a blocking dielectric layer are sequentially formed on the tunnel oxide layer between the insulation interlayer patterns. A plurality of control gate patterns is provided on the blocking dielectric layer between the insulation interlayer patterns. An upper electrode layer pattern is provided on the tunnel oxide layer and on the uppermost insulation interlayer pattern.
摘要翻译：在垂直型非易失性存储器件中，在衬底上设置绝缘层图案，绝缘层图案具有直线形状。单晶半导体图案设置在基板上以与绝缘层图案的两个侧壁接触，单晶半导体图案具有相对于基板在垂直方向上延伸的柱状。隧道氧化物层设置在单晶半导体图案上。在隧道氧化物层和衬底上提供下电极层图案。在下电极层图案上设置多个绝缘层间图案，绝缘层间图案沿着单晶半导体图案彼此隔开预定距离。在绝缘层间图案之间的隧道氧化物层上依次形成电荷捕获层和阻挡介质层。在绝缘夹层图案之间的阻挡介质层上设置多个控制栅极图案。在隧道氧化物层和最上层的绝缘层间图案上设置上电极层图案。

8. 发明申请

US20110073866A1 VERTICAL-TYPE SEMICONDUCTOR DEVICE 有权
标题翻译：垂直型半导体器件
公开(公告)号：US20110073866A1
公开(公告)日：2011-03-31
申请号：US12872270
申请日：2010-08-31
申请人： Young-Hoo Kim , Hyo-San Lee , Sang-Won Bae , Bo-Un Yoon , Kun-Tack Lee
发明人： Young-Hoo Kim , Hyo-San Lee , Sang-Won Bae , Bo-Un Yoon , Kun-Tack Lee
IPC分类号： H01L27/115
CPC分类号： H01L27/11578 , H01L27/11556 , H01L27/11582
摘要： In a vertical-type non-volatile memory device, an insulation layer pattern is provided on a substrate, the insulation layer pattern having a linear shape. Single-crystalline semiconductor patterns are provided on the substrate to make contact with both sidewalls of the insulation layer pattern, the single-crystalline semiconductor patterns having a pillar shape that extends in a vertical direction relative to the substrate. A tunnel oxide layer is provided on the single-crystalline semiconductor pattern. A lower electrode layer pattern is provided on the tunnel oxide layer and on the substrate. A plurality of insulation interlayer patterns is provided on the lower electrode layer pattern, the insulation interlayer patterns being spaced apart from one another by a predetermined distance along the single-crystalline semiconductor pattern. A charge-trapping layer and a blocking dielectric layer are sequentially formed on the tunnel oxide layer between the insulation interlayer patterns. A plurality of control gate patterns is provided on the blocking dielectric layer between the insulation interlayer patterns. An upper electrode layer pattern is provided on the tunnel oxide layer and on the uppermost insulation interlayer pattern.
摘要翻译：在垂直型非易失性存储器件中，在衬底上设置绝缘层图案，绝缘层图案具有直线形状。单晶半导体图案设置在基板上以与绝缘层图案的两个侧壁接触，单晶半导体图案具有相对于基板在垂直方向上延伸的柱状。隧道氧化物层设置在单晶半导体图案上。在隧道氧化物层和衬底上设置下电极层图案。在下电极层图案上设置多个绝缘层间图案，绝缘层间图案沿着单晶半导体图案彼此隔开预定距离。在绝缘层间图案之间的隧道氧化物层上依次形成电荷捕获层和阻挡介质层。在绝缘夹层图案之间的阻挡介质层上设置多个控制栅极图案。在隧道氧化物层和最上层的绝缘层间图案上设置上电极层图案。

9. 发明授权

US08110499B2 Method of forming a contact structure 有权
标题翻译：形成接触结构的方法
公开(公告)号：US08110499B2
公开(公告)日：2012-02-07
申请号：US12437390
申请日：2009-05-07
申请人： Dae-Hyuk Kang , Young-Hoo Kim , Chang-Ki Hong , Kun-Tack Lee , Jae-Dong Lee , Dae-Hong Eom , Jeong-Nam Han
发明人： Dae-Hyuk Kang , Young-Hoo Kim , Chang-Ki Hong , Kun-Tack Lee , Jae-Dong Lee , Dae-Hong Eom , Jeong-Nam Han
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/76814 , H01L21/76846 , H01L21/76855 , H01L23/485 , H01L27/24 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： An insulation layer may be formed on an object having a contact region. The insulation layer may be partially etched to form an opening exposing the contact region. A material layer including silicon and oxygen may be formed on the exposed contact region. A metal layer may be formed on the material layer including silicon and oxygen. The material layer including silicon and oxygen may be reacted with the metal layer to form a metal oxide silicide layer at least on the contact region. A conductive layer may be formed on the metal oxide silicide layer to fill up the opening.
摘要翻译：可以在具有接触区域的物体上形成绝缘层。绝缘层可以被部分蚀刻以形成暴露接触区域的开口。可以在暴露的接触区域上形成包括硅和氧的材料层。可以在包括硅和氧的材料层上形成金属层。包括硅和氧的材料层可以与金属层反应，以至少在接触区域上形成金属氧化物硅化物层。可以在金属氧化物硅化物层上形成导电层以填充开口。

10. 发明申请

US20090280641A1 METHOD OF FORMING A CONTACT STRUCTURE 有权
标题翻译：形成接触结构的方法
公开(公告)号：US20090280641A1
公开(公告)日：2009-11-12
申请号：US12437390
申请日：2009-05-07
申请人： Dae-Hyuk Kang , Young-Hoo Kim , Chang-Ki Hong , Kun-Tack Lee , Jae-Dong Lee , Dae-Hong Eom , Jeong-Nam Han
发明人： Dae-Hyuk Kang , Young-Hoo Kim , Chang-Ki Hong , Kun-Tack Lee , Jae-Dong Lee , Dae-Hong Eom , Jeong-Nam Han
IPC分类号： H01L21/3205
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/76814 , H01L21/76846 , H01L21/76855 , H01L23/485 , H01L27/24 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： An insulation layer may be formed on an object having a contact region. The insulation layer may be partially etched to form an opening exposing the contact region. A material layer including silicon and oxygen may be formed on the exposed contact region. A metal layer may be formed on the material layer including silicon and oxygen. The material layer including silicon and oxygen may be reacted with the metal layer to form a metal oxide silicide layer at least on the contact region. A conductive layer may be formed on the metal oxide silicide layer to fill up the opening.
摘要翻译：可以在具有接触区域的物体上形成绝缘层。绝缘层可以被部分蚀刻以形成暴露接触区域的开口。可以在暴露的接触区域上形成包括硅和氧的材料层。可以在包括硅和氧的材料层上形成金属层。包括硅和氧的材料层可以与金属层反应，以至少在接触区域上形成金属氧化物硅化物层。可以在金属氧化物硅化物层上形成导电层以填充开口。

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