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1. 发明授权

US6124203A Method for forming conformal barrier layers 有权
标题翻译：形成保形层的方法
公开(公告)号：US6124203A
公开(公告)日：2000-09-26
申请号：US206669
申请日：1998-12-07
申请人： Young-Chang Joo , Dirk Brown , Simon S. Chan
发明人： Young-Chang Joo , Dirk Brown , Simon S. Chan
IPC分类号： H01L21/768 , H01L21/283
CPC分类号： H01L21/76876 , H01L21/76865 , H01L21/76873
摘要： The present invention provides a method for forming barrier layers in a channel or via opening by using a plasma etching technique to etch back the barrier layer which reduces the electrical resistance of the barrier layer, maintains its barrier effectiveness and enhances the subsequent filling of the channel or via opening by conductive materials.
摘要翻译：本发明提供了一种通过使用等离子体蚀刻技术在通道或通孔开口中形成阻挡层的方法，以蚀刻阻挡层，降低阻挡层的电阻，保持其屏障效能并增强后续的通道填充或通过导电材料打开。

2. 发明授权

US6121141A Method of forming a void free copper interconnects 有权
标题翻译：形成无空隙铜互连的方法
公开(公告)号：US6121141A
公开(公告)日：2000-09-19
申请号：US198362
申请日：1998-11-24
申请人： Christy Mei-Chu Woo , Dirk Brown , Young-Chang Joo , Imran Hashim
发明人： Christy Mei-Chu Woo , Dirk Brown , Young-Chang Joo , Imran Hashim
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76882
摘要： Void free Cu or Cu alloy interconnects are formed by annealing at superatmospheric pressure after metallization. Embodiments include filling a damascene opening in a dielectric layer with Cu or a Cu alloy and heat treating in a chamber at a pressure of about 2 atmospheres to about 750 atmospheres.
摘要翻译：通过在金属化后的超大气压下退火形成无空隙的Cu或Cu合金互连。实施例包括用Cu或Cu合金填充电介质层中的镶嵌开口，并在室内以约2个大气压至约750个大气压的压力进行热处理。

3. 发明授权

US06228768B1 Storage-annealing plated CU interconnects 有权
标题翻译：存储退火电镀CU互连
公开(公告)号：US06228768B1
公开(公告)日：2001-05-08
申请号：US09184009
申请日：1998-11-02
申请人： Christy Mei-Chu Woo , Young-Chang Joo
发明人： Christy Mei-Chu Woo , Young-Chang Joo
IPC分类号： H01L21302
CPC分类号： H01L21/67109 , H01L21/288 , H01L21/2885 , H01L21/67769 , H01L21/76877
摘要： Cu metalized wafers are stored at elevated temperatures to substantially complete recrystalization, thereby enabling subsequent CMP with a high degree of wafer to wafer uniformity. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill one or more damascene openings in a plurality of wafers, placing the wafers in one or more cassettes, and storage-annealing the cassettes on shelves of a cabinet maintained at about 50° C. to about 200° C. in nitrogen for about 2 minutes to about 3 days.
摘要翻译： Cu金属化晶片在升高的温度下储存以实质上完全重结晶，从而使后续CMP具有高度的晶片与晶片的均匀性。实施例包括电镀或无电镀Cu或Cu合金以填充多个晶片中的一个或多个镶嵌开口，将晶片放置在一个或多个盒中，以及将盒保存在保持在约50℃的柜的架上至约200℃在氮气中约2分钟至约3天。

4. 发明申请

US20130037946A1 SEMICONDUCTOR CHIP INCLUDING BUMP HAVING BARRIER LAYER, AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体芯片，包括带有障碍层的保护膜及其制造方法
公开(公告)号：US20130037946A1
公开(公告)日：2013-02-14
申请号：US13642713
申请日：2011-04-21
申请人： Sung-Dong Kim , Hoo-Jeong Lee , Eun-Kyung Kim , Young-Chang Joo , Gu-Sung Kim
发明人： Sung-Dong Kim , Hoo-Jeong Lee , Eun-Kyung Kim , Young-Chang Joo , Gu-Sung Kim
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/4853 , H01L23/481 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0346 , H01L2224/03462 , H01L2224/0391 , H01L2224/03912 , H01L2224/0401 , H01L2224/05009 , H01L2224/05567 , H01L2224/05568 , H01L2224/05655 , H01L2224/05666 , H01L2224/06181 , H01L2224/11009 , H01L2224/11464 , H01L2224/13025 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13166 , H01L2224/13171 , H01L2224/13181 , H01L2224/14181 , H01L2224/16148 , H01L2224/16238 , H01L2224/81193 , H01L2224/81203 , H01L2224/8181 , H01L2224/8182 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06572 , H01L2924/00014 , H01L2924/0002 , H01L2924/01029 , H01L2924/01327 , H01L2924/12042 , H01L2924/1431 , H01L2924/1434 , H01L2924/01007 , H01L2924/01028 , H01L2924/01023 , H01L2924/01074 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor chip includes a first substrate including a first surface and a second surface, a through-via plug passing through the first substrate, and a first conduction layer connected to an end of the through-via plug on the first surface, and a first bump including a first barrier layer on the first conduction layer, and a first solder layer for connecting the first substrate and a second substrate on the first barrier layer, and the first barrier layer includes a barrier material for preventing diffusion of a conductive material of the first conduction layer into the first solder layer.
摘要翻译：半导体芯片包括：第一基板，包括第一表面和第二表面;穿过第一基板的通孔塞;以及连接到第一表面上的通孔塞末端的第一导电层，包括第一导电层上的第一阻挡层的凸块和用于在第一阻挡层上连接第一基板和第二基板的第一焊料层，并且第一阻挡层包括用于防止导电材料的扩散的阻挡材料第一导电层进入第一焊料层。

5. 发明授权

US06242349B1 Method of forming copper/copper alloy interconnection with reduced electromigration 有权
标题翻译：形成铜/铜合金互连的方法，减少电迁移
公开(公告)号：US06242349B1
公开(公告)日：2001-06-05
申请号：US09207680
申请日：1998-12-09
申请人： Takeshi Nogami , Sergey Lopatin , Young-Chang Joo
发明人： Takeshi Nogami , Sergey Lopatin , Young-Chang Joo
IPC分类号： H01L2144
CPC分类号： H01L21/76874 , H01L21/76843 , H01L21/76864 , H01L21/76873 , H05K1/0306 , H05K3/388
摘要： The electromigration of a Cu or Cu alloy interconnection member is reduced by annealing the seed layer before electroplating or electroless plating the Cu or Cu alloy interconnection member on the seed layer. Embodiments include depositing a Cu or Cu alloy seed layer, annealing at about 100° C. to about 400° C. to increase the grain size of the seed layer and impart a (111)-dominant crystallographic option before plating the Cu or Cu alloy interconnect member thereon the seed layer
摘要翻译：通过在种子层上电镀或无电镀Cu或Cu合金互连构件之前退火种子层，可以减少Cu或Cu合金互连构件的电迁移。实施方案包括沉积Cu或Cu合金种子层，在约100℃至约400℃退火以增加种子层的晶粒尺寸并在镀覆Cu或Cu合金之前赋予（111） - 显性晶体选择互连部件上的籽晶层

6. 发明授权

US6053034A Method for measuring fracture toughness of thin films 失效
$Method for measuring fracture toughness of thin films$
标题翻译：测量薄膜断裂韧性的方法
公开(公告)号：US6053034A
公开(公告)日：2000-04-25
申请号：US168570
申请日：1998-10-09
申请人： Ting Y. Tsui , Young-Chang Joo
发明人： Ting Y. Tsui , Young-Chang Joo
IPC分类号： G01N3/00 , G01N3/02 , G01N3/42 , G01Q60/24 , G01N3/48
CPC分类号： G01Q60/366 , B82Y35/00 , G01N3/42 , G01N2203/0064 , G01N2203/0067 , G01N2203/027 , G01N2203/0282 , G01N2203/0286 , Y10S977/70 , Y10S977/856 , Y10S977/90
摘要： A nanoindentation apparatus is used to measure the in-plane fracture toughness of a thin film formed on a substrate. One or more notches are formed in the thin film. An indenter is applied to the thin film near the notch or notches and a load is applied to the indenter to force it into the thin film. Because the substrate is softer than the thin film, the indenter does not penetrate the thin film, but "sinks in" to the soft substrate. The sink in effect enhances the tensile strain and stress at the notch. In one embodiment, both the penetration of the indenter into the thin film and substrate and the load on the indenter are measured. When the thin film fractures at the notch or notches, the indenter sharply sinks into the substrate. The thin film fracture toughness is then calculated based on the value of the load and penetration at the point of fracture using either finite element analysis or an analytical model. In a second embodiment, the cross-section of the notch or notches is measured after removing the indenter which has formed an indentation in the thin film. The indenter acts as a crack extension force. The thin film fracture toughness is then calculated based upon the geometry of a crack tip at the tip of the notch and using finite element analysis, or an analytical model, such as a Crack Tip Opening Displacement (CTOD) method.
摘要翻译：纳米压痕装置用于测量在基板上形成的薄膜的面内断裂韧性。在薄膜中形成一个或多个凹口。将压头施加到缺口附近的薄膜或凹口，并将负载施加到压头以将其压入薄膜中。由于衬底比薄膜柔软，所以压头不穿透薄膜，而是“沉入”到柔性衬底。水槽有效地增强了缺口处的拉伸应变和应力。在一个实施例中，测量压头到薄膜和基底的穿透以及压头上的载荷。当薄膜在切口或凹口处断裂时，压头急剧下沉到基板中。然后使用有限元分析或分析模型，基于负荷点和断裂点的穿透值计算薄膜断裂韧度。在第二实施例中，在去除在薄膜中形成凹陷的压头之后，测量切口或切口的横截面。压头作为裂纹扩展力。然后基于缺口尖端处的裂纹尖端的几何形状和使用有限元分析或诸如裂纹尖端开口位移（CTOD）方法的分析模型来计算薄膜断裂韧度。

7. 发明授权

US06633083B2 Barrier layer integrity test 失效
标题翻译：阻隔层完整性测试
公开(公告)号：US06633083B2
公开(公告)日：2003-10-14
申请号：US09514413
申请日：2000-02-28
申请人： Christy Mei-Chu Woo , Young-Chang Joo , Todd Lukanc
发明人： Christy Mei-Chu Woo , Young-Chang Joo , Todd Lukanc
IPC分类号： H01L3106
CPC分类号： H01L22/34
摘要： A structure and method for determining barrier layer integrity for multi-level copper metallization structures in integrated circuit manufacturing. Novel testing structures prevent any conducting residues of the copper CMP from diffusing into the dielectric layer. Barrier layer integrity is tested by performing CV or IV measurements between the copper lines and the silicon wafer.
摘要翻译：一种用于确定集成电路制造中多级铜金属化结构的阻挡层完整性的结构和方法。新的测试结构防止铜CMP的任何导电残余物扩散到电介质层中。通过在铜线和硅晶片之间执行CV或IV测量来测试阻挡层的完整性

8. 发明授权

US06348701B1 Method for determining metal concentration in a field area 失效
标题翻译：确定场区金属浓度的方法
公开(公告)号：US06348701B1
公开(公告)日：2002-02-19
申请号：US09421455
申请日：1999-10-19
申请人： Young-Chang Joo , Amit P. Marathe
发明人： Young-Chang Joo , Amit P. Marathe
IPC分类号： H01L2358
CPC分类号： H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： The concentration of metal atoms in a field area between two trench structures is determined by applying a voltage on one of the trench structures and grounding the other. The resultant current flow between the trench structures is measured and used as an indicator of metal concentration in the field area.
摘要翻译：两个沟槽结构之间的场区域中的金属原子的浓度通过在一个沟槽结构上施加电压并将另一个接地而确定。测量沟槽结构之间的所得电流，并将其用作场区域中的金属浓度的指标。

9. 发明授权

US06339958B1 Adhesion strength testing using a depth-sensing indentation technique 失效
标题翻译：使用深度感测压痕技术的粘附强度测试
公开(公告)号：US06339958B1
公开(公告)日：2002-01-22
申请号：US09208843
申请日：1998-12-10
申请人： Ting Y. Tsui , Young-Chang Joo
发明人： Ting Y. Tsui , Young-Chang Joo
IPC分类号： G01N324
CPC分类号： G01N19/04 , G01N3/42 , G01N2203/0091 , G01N2203/0234 , G01N2203/0278 , G01Q60/366
摘要： A nanoindentation apparatus is used to measure adhesion strength of a hard, thin film to a soft substrate. A variably increasing load is applied to the indenter tip. The indenter tip penetrates into the thin film at a first penetration rate and causes the thin film to sink into the substrate thus causing a tensile stress at the film substrate interface. At a critical value of the applied load, the stress at the interface exceeds the delamination value, and the thin film partially delaminates from the substrate. This causes the indenter tip to sink into the softer substrate at a sudden second, higher penetration rate. A sensor detects the applied load and the indenter tip penetration depth at this point. A computer flags the critical value of the applied load that corresponds to the increased penetration depth rate at the point of delamination of the film. The computer then calculates the critical stress required for delamination and the adhesion strength between the film and the substrate from the critical value of the applied load. The depth sensing indentation technique measurement may be carried out on a thin film integrated test element so as not to damage the rest of the thin film. The method allows non-destructive in-situ adhesion strength measurements for thin films and microelectronic devices.
摘要翻译：使用纳米压痕装置测量硬质薄膜与柔性基材的粘合强度。可变增加的负载施加到压头。压头尖以第一穿透速率渗入薄膜中，并使薄膜沉入基片中，从而在薄膜基底界面处产生拉伸应力。在施加负载的临界值时，界面处的应力超过分层值，薄膜与基板部分分层。这使得压头尖端以突然的第二次较高的穿透速率下沉到较软的基底中。此时传感器检测施加的载荷和压头尖端的穿透深度。计算机标记所施加的载荷的临界值，其对应于胶片分层点处的增加的穿透深度速率。然后，计算机从所施加的负载的临界值计算分层所需的临界应力和膜与基板之间的粘附强度。深度感测压痕技术测量可以在薄膜集成测试元件上进行，以免损坏薄膜的其余部分。该方法允许薄膜和微电子器件的非破坏性原位粘附强度测量。

10. 发明授权

US06242924B1 Method for electronically measuring size of internal void in electrically conductive lead 失效
标题翻译：用于电子测量导电铅内部空隙尺寸的方法
公开(公告)号：US06242924B1
公开(公告)日：2001-06-05
申请号：US09236844
申请日：1999-01-25
申请人： Tsui Ting Yiu , Yow Juang W. Liu , Young-Chang Joo , Sunil N. Shabde
发明人： Tsui Ting Yiu , Yow Juang W. Liu , Young-Chang Joo , Sunil N. Shabde
IPC分类号： H01H3102
CPC分类号： G01N27/20
摘要： The size of an internal void in an electrically conductive lead is measured by determining its electrical resistance at a plurality of A.C. frequencies, ranging from D.C. to a frequency on the order of 50 to 100 GHz at which the majority of current flows along the skin of the lead. The test data is compared with reference data for an electrically conductive reference lead having characteristics which are essentially similar to the test lead. The difference between the two sets of data increases with the size of an internal void in the test lead. The difference will be greatest at D.C. because the current will flow through substantially the entire cross-section of the lead and the cross-sectional area will be reduced by the internal void. The test data will approach the reference data as the frequency increases because the majority of the current will flow through the skin of the test lead and will be less affected by the internal void. The surface roughness of a lead caused by surface voids is measured by determining its electrical resistance at a frequency high enough that the majority of the current flows through the skin of the lead. The distance at which the surface current flows, and thereby the resistance of the lead, increase with the surface roughness.
摘要翻译：通过确定其在多个AC频率处的电阻来测量导电引线中的内部空隙的尺寸，其范围从DC到大约50至100GHz的频率，其中大部分电流沿着皮肤带头。将测试数据与具有与测试引线基本相似的特性的导电参考引线的参考数据进行比较。两组数据之间的差异随测试引线内部空隙的大小而增加。差异在直流电中将最大，因为电流将大部分流过导线的整个横截面，横截面积将由内部空隙减小。随着频率增加，测试数据将接近参考数据，因为大部分电流将流过测试导线的皮肤，并且将受到内部空隙的影响较小。由表面空隙引起的铅的表面粗糙度通过以足够高的频率确定其电阻来测量，使得大部分电流流过铅的皮肤。表面电流流动的距离，从而引线的电阻随着表面粗糙度的增加而增加。

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