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    • 5. 发明申请
    • Liquid crystal display device and method of manufacturing the same
    • 液晶显示装置及其制造方法
    • US20070097306A1
    • 2007-05-03
    • US11472022
    • 2006-06-20
    • Sung JungYoung LeeYoung KimJong Park
    • Sung JungYoung LeeYoung KimJong Park
    • G02F1/1343
    • G02F1/1345G02F2001/133388G02F2201/121
    • An LCD and a method of manufacturing the same are provided. The LCD includes first and second substrates defined by a display region and a non-display region, and spaced a predetermined interval apart from each other. The LCD further comprises a liquid crystal layer interposed between the first and second substrates, a conductive part formed on at least one side of the first substrate corresponding to the non-display region. The conductive part has a first dummy pattern formed of metal identical to that of a gate line in the display region. The LCD then comprises a common electrode formed on the second substrate, and a conductive thread pattern that electrically connects the common electrode and the conductive part, and attaches the first and second substrates.
    • 提供LCD及其制造方法。 LCD包括由显示区域和非显示区域限定的第一和第二基板,并且彼此隔开预定间隔。 液晶显示装置还包括介于第一和第二基板之间的液晶层,形成在对应于非显示区域的第一基板的至少一侧上的导电部分。 导电部件具有由与显示区域中的栅极线相同的金属形成的第一虚设图案。 然后,LCD包括形成在第二基板上的公共电极和电连接公共电极和导电部分并且连接第一和第二基板的导电线图案。
    • 9. 发明申请
    • Trench isolation method in flash memory device
    • 闪存设备中的沟槽隔离方法
    • US20050142745A1
    • 2005-06-30
    • US11019302
    • 2004-12-23
    • Sung JungJum Kim
    • Sung JungJum Kim
    • H01L21/76H01L21/762H01L21/8247H01L27/115H01L21/336
    • H01L27/11521H01L21/76224H01L27/115
    • The present invention provides a trench isolation method in a flash memory device, by which stability and reliability of the device are enhanced in a manner of forming a pad oxide layer thick in the vicinity of an edge of a trench isolation layer. The present invention includes forming a mask layer pattern on a semiconductor substrate to expose a device isolation area but to cover an active area thereof, the mask layer pattern comprising a first insulating layer pattern and a second insulating layer pattern stacked thereon, forming a trench in the semiconductor substrate corresponding to the device isolation area, removing an exposed portion of the first insulating layer pattern enough to expose a portion of the semiconductor substrate in the active area adjacent to the trench, forming a sidewall oxide layer on an inside of the trench and the exposed portion of the semiconductor substrate, filling up the trench with a third insulating layer to cover the sidewall oxide layer, and removing the mask layer pattern.
    • 本发明提供了一种闪速存储器件中的沟槽隔离方法,通过这种方法,在沟槽隔离层的边缘附近形成厚的衬垫氧化物层,增强了器件的稳定性和可靠性。 本发明包括在半导体衬底上形成掩模层图案以暴露器件隔离区域而覆盖其有效区域,掩模层图案包括第一绝缘层图案和叠置在其上的第二绝缘层图案,形成沟槽 所述半导体衬底对应于所述器件隔离区域,去除所述第一绝缘层图案的暴露部分以足以暴露所述半导体衬底在与所述沟槽相邻的有源区域中的一部分,在所述沟槽的内部形成侧壁氧化物层,以及 半导体衬底的暴露部分,用第三绝缘层填充沟槽以覆盖侧壁氧化物层,以及去除掩模层图案。
    • 10. 发明申请
    • High voltage semiconductor device and fabricating method thereof
    • 高压半导体器件及其制造方法
    • US20050139916A1
    • 2005-06-30
    • US11020276
    • 2004-12-27
    • Jum KimSung Jung
    • Jum KimSung Jung
    • H01L29/78H01L29/417H01L29/76H01L29/94H01L31/062H01L31/113
    • H01L29/41775
    • A high voltage semiconductor device and fabricating method thereof, enable a high breakdown voltage to be provided from a surface area without forming a dual spacer layer. The semiconductor device includes a semiconductor substrate having source/drain regions separated from each other by a channel region in-between, a gate insulating layer pattern on the channel region, a gate conductor layer pattern on the gate insulating layer, a sidewall insulating layer provided on a sidewall of the gate conductor layer pattern, a salicide suppress layer pattern covering partial, but not entire, surfaces of the source/drain regions, and covering the sidewall insulating layer, and the gate conductor layer pattern, and a metal salicide layer on remaining portions surfaces of the source/drain regions that are not covered with the salicide suppress layer pattern.
    • 高压半导体器件及其制造方法能够从表面区域提供高的击穿电压而不形成双间隔层。 半导体器件包括具有源极/漏极区域的半导体衬底,沟道区域之间的沟道区域彼此分离,沟道区域上的栅极绝缘层图案,栅极绝缘层上的栅极导体层图案,提供的侧壁绝缘层 在栅极导体层图案的侧壁上,覆盖源极/漏极区域的部分但不是整个表面并且覆盖侧壁绝缘层和栅极导体层图案以及金属硅化物层的自对准硅化物抑制层图案 未被自对准硅化物抑制层图案覆盖的源/漏区的剩余部分表面。