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1. 发明授权

US08027210B2 Data input apparatus with improved setup/hold window 失效
标题翻译：具有改进的建立/保持窗口的数据输入设备
公开(公告)号：US08027210B2
公开(公告)日：2011-09-27
申请号：US12199046
申请日：2008-08-27
申请人： Kie Bong Ku , Kwang Jun Cho
发明人： Kie Bong Ku , Kwang Jun Cho
IPC分类号： G11C7/00
CPC分类号： G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/225 , G11C8/06 , G11C8/18
摘要： In the data input apparatus, a data delay unit outputs data input from outside the data input apparatice. The data delay unit varies the degree of delay in response to a test mode signal. A data alignment signal generating unit receives a first signal synchronized with an external clock signal and a second signal synchronized with a data strobe signal, and the data alignment signal generating unit outputs one of the first signal and the second signal as a data alignment signal in response to the test mode signal. A data alignment unit is synchronized with the data alignment signal to align the data delayed in the data delay unit. The data input apparatus improves the setup/hold window when a semiconductor memory device is in the test mode.
摘要翻译：在数据输入装置中，数据延迟单元输出从数据输入装置外部输入的数据。数据延迟单元改变响应于测试模式信号的延迟程度。数据对准信号发生单元接收与外部时钟信号同步的第一信号和与数据选通信号同步的第二信号，并且数据对准信号生成单元将第一信号和第二信号中的一个作为数据对准信号输出响应测试模式信号。数据对准单元与数据对准信号同步，以对准在数据延迟单元中延迟的数据。当半导体存储器件处于测试模式时，数据输入设备改进了建立/保持窗口。

2. 发明申请

US20070242531A1 WRITE APPARATUS FOR DDR SDRAM SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译： DDR SDRAM半导体存储器件的写入装置
公开(公告)号：US20070242531A1
公开(公告)日：2007-10-18
申请号：US11687285
申请日：2007-03-16
申请人： Kie Bong Ku , Kwang Jun Cho
发明人： Kie Bong Ku , Kwang Jun Cho
IPC分类号： G11C7/10
CPC分类号： G11C7/1039 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/1096
摘要： A writing apparatus of a semiconductor memory device includes a pulse generator, a latch unit and an output latch unit. The pulse generator outputs a first pulse every rising edge of a data strobe pulse and a second pulse every falling edge of the data strobe pulse, respectively. The latch unit latches data input every rising edge of the first pulse, latches data input every rising edge of the second pulse and the latched data, respectively, and allocates the latched data to first and second data lines. The output latch unit latches data, which are firstly allocated to the first and second data lines, in response to a first control signal, and latches data, which are secondly allocated to the first and second data lines, in response to a second control signal.
摘要翻译：半导体存储器件的写入装置包括脉冲发生器，锁存单元和输出锁存单元。脉冲发生器分别在数据选通脉冲的每个下降沿沿数据选通脉冲的每个上升沿和第二脉冲输出第一脉冲。锁存单元在第一脉冲的每个上升沿锁存数据输入，分别锁存在第二脉冲的上升沿和锁存数据上的数据输入，并将锁存的数据分配给第一和第二数据线。输出锁存单元响应于第一控制信号锁存首先分配给第一和第二数据线的数据，并且响应于第二控制信号锁存第二分配给第一和第二数据线的数据。

3. 发明授权

US07671646B2 Delay locked loop 有权
标题翻译：延迟锁定环路
公开(公告)号：US07671646B2
公开(公告)日：2010-03-02
申请号：US12421434
申请日：2009-04-09
申请人： Kwang Jun Cho , Kie Bong Ku
发明人： Kwang Jun Cho , Kie Bong Ku
IPC分类号： H03L7/06
CPC分类号： H03K5/1565
摘要： The digital duty cycle correction circuit according to the present invention includes a first conversion circuit for buffering an internal clock output from a delay locked loop (DLL), converting the buffered internal clock into first and second clocks through first and second terminals, delaying the second clock according to voltage supplied to the second terminal through a capacitor, converting the delayed second clock into a first signal, and converting the first clock into a third clock, which rises at a falling edge of the first clock and falls at a rising edge of the first signal; and a second conversion circuit for converting the third clock into an output clock, which rises at a falling edge of the third clock and falls at a rising edge of the third clock.
摘要翻译：根据本发明的数字占空比校正电路包括用于缓冲来自延迟锁定环（DLL）的内部时钟输出的第一转换电路，通过第一和第二终端将缓冲的内部时钟转换成第一和第二时钟，延迟第二时钟，根据通过电容器提供给第二终端的电压，将延迟的第二时钟转换为第一信号，并将第一时钟转换为第三时钟，第三时钟在第一时钟的下降沿上升，并且下降到第一个信号; 以及第二转换电路，用于将第三时钟转换为在第三时钟的下降沿上升并在第三时钟的上升沿下降的输出时钟。

4. 发明授权

US07548100B2 Delay locked loop 有权
标题翻译：延迟锁定环路
公开(公告)号：US07548100B2
公开(公告)日：2009-06-16
申请号：US11687396
申请日：2007-03-16
申请人： Kwang Jun Cho , Kie Bong Ku
发明人： Kwang Jun Cho , Kie Bong Ku
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： The digital duty cycle correction circuit according to the present invention includes a first conversion circuit for buffering an internal clock output from a delay locked loop (DLL), converting the buffered internal clock into first and second clocks through first and second terminals, delaying the second clock according to voltage supplied to the second terminal through a capacitor, converting the delayed second clock into a first signal, and converting the first clock into a third clock, which rises at a falling edge of the first clock and falls at a rising edge of the first signal; and a second conversion circuit for converting the third clock into an output clock, which rises at a falling edge of the third clock and falls at a rising edge of the third clock.
摘要翻译：根据本发明的数字占空比校正电路包括用于缓冲来自延迟锁定环（DLL）的内部时钟输出的第一转换电路，通过第一和第二终端将缓冲的内部时钟转换成第一和第二时钟，延迟第二时钟，根据通过电容器提供给第二终端的电压，将延迟的第二时钟转换为第一信号，并将第一时钟转换为第三时钟，第三时钟在第一时钟的下降沿上升，并且下降到第一个信号; 以及第二转换电路，用于将第三时钟转换为在第三时钟的下降沿上升并在第三时钟的上升沿下降的输出时钟。

5. 发明授权

US07463534B2 Write apparatus for DDR SDRAM semiconductor memory device 有权
标题翻译： DDR SDRAM半导体存储器件的写装置
公开(公告)号：US07463534B2
公开(公告)日：2008-12-09
申请号：US11687285
申请日：2007-03-16
申请人： Kie Bong Ku , Kwang Jun Cho
发明人： Kie Bong Ku , Kwang Jun Cho
IPC分类号： G11C7/10
CPC分类号： G11C7/1039 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/1096
摘要： A writing apparatus of a semiconductor memory device includes a pulse generator, a latch unit and an output latch unit. The pulse generator outputs a first pulse every rising edge of a data strobe pulse and a second pulse every falling edge of the data strobe pulse, respectively. The latch unit latches data input every rising edge of the first pulse, latches data input every rising edge of the second pulse and the latched data, respectively, and allocates the latched data to first and second data lines. The output latch unit latches data, which are firstly allocated to the first and second data lines, in response to a first control signal, and latches data, which are secondly allocated to the first and second data lines, in response to a second control signal.
摘要翻译：半导体存储器件的写入装置包括脉冲发生器，锁存单元和输出锁存单元。脉冲发生器分别在数据选通脉冲的每个下降沿沿数据选通脉冲的每个上升沿和第二脉冲输出第一脉冲。锁存单元在第一脉冲的每个上升沿锁存数据输入，分别锁存在第二脉冲的上升沿和锁存数据上的数据输入，并将锁存的数据分配给第一和第二数据线。输出锁存单元响应于第一控制信号锁存首先分配给第一和第二数据线的数据，并且响应于第二控制信号锁存第二分配给第一和第二数据线的数据。

6. 发明授权

US07928786B2 Clock buffer circuit of semiconductor device configured to generate an internal clock signal 有权
标题翻译：半导体器件的时钟缓冲电路被配置为产生内部时钟信号
公开(公告)号：US07928786B2
公开(公告)日：2011-04-19
申请号：US12657208
申请日：2010-01-14
申请人： Kwang Jun Cho
发明人： Kwang Jun Cho
IPC分类号： H03K3/017
CPC分类号： G11C7/22 , G11C7/222 , G11C7/225 , H03K5/1565
摘要： A clock buffer circuit of a semiconductor device is disclosed which receives an external clock signal and generates an internal clock signal with no duty distortion. The clock buffer circuit includes a first clock buffer for receiving and buffering a normal-phase clock signal, a second clock buffer for receiving and buffering a reverse-phase clock signal, and an internal clock generator for generating an internal clock signal in response to output signals from the first and second clock buffers.
摘要翻译：公开了一种接收外部时钟信号并产生无占空比失真的内部时钟信号的半导体器件的时钟缓冲电路。时钟缓冲电路包括用于接收和缓冲正相时钟信号的第一时钟缓冲器，用于接收和缓冲反相时钟信号的第二时钟缓冲器，以及响应于输出产生内部时钟信号的内部时钟发生器来自第一和第二时钟缓冲器的信号。

7. 发明申请

US20080315927A1 FREQUENCY ADJUSTING APPARATUS AND DLL CIRCUIT INCLUDING THE SAME 审中-公开
标题翻译：频率调整装置和DLL电路，包括它们
公开(公告)号：US20080315927A1
公开(公告)日：2008-12-25
申请号：US11966300
申请日：2007-12-28
申请人： Kwang Jun Cho , Jun Hyun Chun
发明人： Kwang Jun Cho , Jun Hyun Chun
IPC分类号： H03L7/06
CPC分类号： H03L7/0814
摘要： A frequency adjusting apparatus includes a frequency control signal generating unit that generates a multi-bit frequency control signal, which is changed in level bit by bit, in response to a reference clock signal, and a frequency adjusting unit that adjusts the frequency of the reference clock signal in response to the multi-bit frequency control signal.
摘要翻译：一种频率调整装置，包括：频率控制信号生成部，其响应于基准时钟信号，生成逐位变化的多位频率控制信号;以及频率调整部，其调整基准的频率响应于多位频率控制信号的时钟信号。

8. 发明授权

US06970393B1 Pulse generating circuit for self-refresh 失效
标题翻译：用于自刷新的脉冲发生电路
公开(公告)号：US06970393B1
公开(公告)日：2005-11-29
申请号：US10879201
申请日：2004-06-30
申请人： Kwang Jun Cho , You Sung Kim
发明人： Kwang Jun Cho , You Sung Kim
IPC分类号： G11C7/00 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/40626
摘要： A pulse generating circuit for self refresh including a voltage comparison unit having a plurality of selectable capacitor charged by a feedback voltage variably supplied through a first node depending on temperature change, for comparing the charge voltage with a reference voltage to output a signal corresponding to the comparison result, a delay circuit connected to the output of the voltage comparison unit, a control unit for receiving the output of the delay circuit, and a temperature sensor connected to the output of the control circuit and providing feedback signal to the voltage comparison unit.
摘要翻译：一种用于自刷新的脉冲发生电路，包括电压比较单元，该电压比较单元具有多个可选择的电容器，该多个可选择的电容器由根据温度变化通过第一节点可变地提供的反馈电压充电，用于将充电电压与参考电压进行比较，以输出对应于比较结果，连接到电压比较单元的输出的延迟电路，用于接收延迟电路的输出的控制单元和连接到控制电路的输出的温度传感器，并向电压比较单元提供反馈信号。

9. 发明授权

US08253459B2 Frequency adjusting apparatus and DLL circuit including the same 有权
标题翻译：调频装置和DLL电路一样
公开(公告)号：US08253459B2
公开(公告)日：2012-08-28
申请号：US13083247
申请日：2011-04-08
申请人： Kwang Jun Cho , Jun Hyun Chun
发明人： Kwang Jun Cho , Jun Hyun Chun
IPC分类号： H03L7/06
CPC分类号： H03L7/0814
摘要： A frequency adjusting apparatus includes a frequency control signal generating unit that generates a multi-bit frequency control signal, which is changed in level bit by bit, in response to a reference clock signal, and a frequency adjusting unit that adjusts the frequency of the reference clock signal in response to the multi-bit frequency control signal.
摘要翻译：一种频率调整装置，包括：频率控制信号生成部，其响应于基准时钟信号，生成逐位变化的多位频率控制信号;以及频率调整部，其调整基准的频率响应于多位频率控制信号的时钟信号。

10. 发明授权

US07423468B2 Duty correction circuit of digital type for optimal layout area and current consumption 有权
标题翻译：数字型负责校正电路，实现最佳布局面积和电流消耗
公开(公告)号：US07423468B2
公开(公告)日：2008-09-09
申请号：US11652832
申请日：2007-01-12
申请人： Kwang Jun Cho
发明人： Kwang Jun Cho
IPC分类号： H03K3/017
CPC分类号： H03L7/0814
摘要： The present invention relates to a duty correction circuit that corrects a distorted duty of a clock signal using a delay unit and a delay controller, thereby reducing the layout area and current consumption. The duty correction circuit includes a repeater that generates a clock signal having the same phase as that of an input clock signal with a distorted duty, and a clock signal having an inverted phase of the phase; a delay line delaying the phase of the clock signal having the inverted phase and generating a feedback clock signal; a phase comparator comparing the phase of the clock signal having the same phase with the phase of the feedback clock signal and generating a delay control signal according to the phase difference between the phases of the clock signal having the same phase and the feedback clock signal; a delay controller controlling the amount of delay of the delay line according to the delay control signal; and a phase mixer performing half-phase blending on the clock signal having the same phase and the feedback clock signal and outputting a clock signal having a corrected duty.
摘要翻译：本发明涉及一种使用延迟单元和延迟控制器校正时钟信号的失真占空比的占空比校正电路，从而减少布局面积和电流消耗。该占空比校正电路包括一个中继器，它产生与具有失真占空比的输入时钟信号具有相同相位的时钟信号，以及一个具有该相位的相位相位的时钟信号; 延迟线延迟具有反相的时钟信号的相位并产生反馈时钟信号; 相位比较器，将具有相同相位的时钟信号的相位与反馈时钟信号的相位进行比较，并根据具有相同相位的时钟信号的相位与反馈时钟信号之间的相位差产生延迟控制信号; 延迟控制器，根据延迟控制信号控制延迟线的延迟量; 以及相位混合器对具有相同相位的时钟信号和反馈时钟信号执行半相混合，并输出具有校正占空比的时钟信号。

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