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1. 发明申请

US20110089138A1 METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD 审中-公开
标题翻译：制造印刷电路板的方法
公开(公告)号：US20110089138A1
公开(公告)日：2011-04-21
申请号：US12634649
申请日：2009-12-09
申请人： Young Gwan Ko , Ryoichi Watanabe , Sang Soo Lee , Hee Bum Shin , Se Won Park , Chil Woo Kwon
发明人： Young Gwan Ko , Ryoichi Watanabe , Sang Soo Lee , Hee Bum Shin , Se Won Park , Chil Woo Kwon
IPC分类号： B44C1/22
CPC分类号： H05K3/465 , H05K3/107 , H05K2201/10204
摘要： Disclosed is a method of manufacturing a printed circuit board, including (A) forming a first circuit layer on a base substrate and forming a first insulating layer thereon, (B) forming trenches including dummy trenches and wiring trenches on the first insulating layer and plating the trenches, thus providing a trench circuit layer including a dummy circuit pattern and a wiring circuit pattern, (C) removing the dummy circuit pattern of the trench circuit layer, and (D) forming a second insulating layer on the trench circuit layer from which the dummy circuit pattern was removed. The method reduces deviation of plating thickness and thus realizes the design density of a trench circuit layer.
摘要翻译：公开了一种制造印刷电路板的方法，包括（A）在基底基板上形成第一电路层并在其上形成第一绝缘层，（B）在第一绝缘层和电镀上形成包括虚设沟槽和布线沟槽的沟槽沟槽，从而提供包括虚拟电路图案和布线电路图案的沟槽电路层，（C）去除沟槽电路层的虚设电路图案，（D）在沟槽电路层上形成第二绝缘层，去除虚拟电路图案。该方法减小了镀层厚度的偏差，从而实现了沟槽电路层的设计密度。

2. 发明申请

US20110079421A1 PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：印刷电路板及其制造方法
公开(公告)号：US20110079421A1
公开(公告)日：2011-04-07
申请号：US12634520
申请日：2009-12-09
申请人： Young Gwan KO , Ryoichi Watanabe , Sang Soo Lee , Se Won Park
发明人： Young Gwan KO , Ryoichi Watanabe , Sang Soo Lee , Se Won Park
IPC分类号： H05K1/11 , B05D5/12 , C25D5/00 , C23F1/00
CPC分类号： H05K3/465 , H05K3/045 , H05K3/06 , H05K3/064 , H05K3/4602 , H05K3/4644 , H05K2201/0352 , H05K2201/09536 , H05K2203/0353
摘要： Disclosed herein is a printed circuit board, including: a base substrate; insulation layers which are formed on both sides of the base substrate and in which trenches are formed; and circuit layers including circuit patterns and vias formed in the trenches using a plating process. The printed circuit board is advantageous in that trenches are formed in both sides of a base substrate, so that a fine circuit pattern can be simultaneously formed on both sides thereof, thereby simplifying the manufacturing process thereof.
摘要翻译：本文公开了一种印刷电路板，包括：基底; 绝缘层，其形成在基底基板的两侧，并且形成沟槽; 以及电路层，其包括使用电镀工艺在沟槽中形成的电路图案和通孔。印刷电路板的优点在于，在基底基板的两侧形成沟槽，从而可以在其两侧同时形成精细电路图案，从而简化了其制造工艺。

3. 发明授权

US08883647B2 Method of manufacturing of trench substrate 有权
标题翻译：沟槽衬底的制造方法
公开(公告)号：US08883647B2
公开(公告)日：2014-11-11
申请号：US13310319
申请日：2011-12-02
申请人： Young Gwan Ko , Ryoichi Watanabe , Sang Soo Lee
发明人： Young Gwan Ko , Ryoichi Watanabe , Sang Soo Lee
IPC分类号： H01L21/311 , H01L23/498 , H01L21/48 , H05K3/46 , H05K3/04 , H05K3/06 , H01L21/321
CPC分类号： H01L21/486 , H01L21/32115 , H01L21/4846 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L2924/0002 , H05K3/045 , H05K3/06 , H05K3/465 , H05K2201/09036 , H05K2201/09781 , H05K2203/0723 , H01L2924/00
摘要： Disclosed herein are a trench substrate and a method of manufacturing the same. The trench substrate includes a base substrate, an insulating layer formed on one side or both sides of the base substrate and including trenches formed in a circuit region and a dummy region positioned at a peripheral edge of the trench substrate, and a circuit layer formed in the trenches of the circuit region through a plating process and including a circuit pattern and vias. Thanks to formation of the trenches in the dummy region and the cutting region, deviation in thickness of a plating layer formed on the insulating layer in a plating process is improved upon.
摘要翻译：这里公开了沟槽衬底及其制造方法。沟槽基板包括基底基板，形成在基底基板的一侧或两侧上的绝缘层，并且包括形成在电路区域中的沟槽和位于沟槽基板的周边边缘的虚设区域，以及电路层，通过电镀工艺的电路区域的沟槽，并且包括电路图案和通孔。由于在虚拟区域和切割区域中形成沟槽，因此在电镀工艺中在绝缘层上形成的镀层的厚度偏差得到改善。

4. 发明授权

US08072052B2 Trench substrate 有权
标题翻译：沟槽衬底
公开(公告)号：US08072052B2
公开(公告)日：2011-12-06
申请号：US12463945
申请日：2009-05-11
申请人： Young Gwan Ko , Ryoichi Watanabe , Sang Soo Lee
发明人： Young Gwan Ko , Ryoichi Watanabe , Sang Soo Lee
IPC分类号： H01L23/495
CPC分类号： H01L21/486 , H01L21/32115 , H01L21/4846 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L2924/0002 , H05K3/045 , H05K3/06 , H05K3/465 , H05K2201/09036 , H05K2201/09781 , H05K2203/0723 , H01L2924/00
摘要： Disclosed herein are a trench substrate and a method of manufacturing the same. The trench substrate includes a base substrate, an insulating layer formed on one side or both sides of the base substrate and including trenches formed in a circuit region and a dummy region positioned at a peripheral edge of the trench substrate, and a circuit layer formed in the trenches of the circuit region through a plating process and including a circuit pattern and vias. Thanks to formation of the trenches in the dummy region and the cutting region, deviation in thickness of a plating layer formed on the insulating layer in a plating process is improved upon.
摘要翻译：这里公开了沟槽衬底及其制造方法。沟槽基板包括基底基板，形成在基底基板的一侧或两侧上的绝缘层，并且包括形成在电路区域中的沟槽和位于沟槽基板的周边边缘的虚设区域，以及电路层，通过电镀工艺的电路区域的沟槽，并且包括电路图案和通孔。由于在虚拟区域和切割区域中形成沟槽，因此在电镀工艺中在绝缘层上形成的镀层的厚度偏差得到改善。

5. 发明申请

US20100264549A1 Trench Substrate and Method Of Manufacturing The Same 有权
标题翻译：沟槽基板及其制造方法
公开(公告)号：US20100264549A1
公开(公告)日：2010-10-21
申请号：US12463945
申请日：2009-05-11
申请人： Young Gwan KO , Ryoichi Watanabe , Sang Soo Lee
发明人： Young Gwan KO , Ryoichi Watanabe , Sang Soo Lee
IPC分类号： H01L23/48 , H01L21/78 , H01L21/768
CPC分类号： H01L21/486 , H01L21/32115 , H01L21/4846 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L2924/0002 , H05K3/045 , H05K3/06 , H05K3/465 , H05K2201/09036 , H05K2201/09781 , H05K2203/0723 , H01L2924/00
摘要： Disclosed herein are a trench substrate and a method of manufacturing the same. The trench substrate includes a base substrate, an insulating layer formed on one side or both sides of the base substrate and including trenches formed in a circuit region and a dummy region positioned at a peripheral edge of the trench substrate, and a circuit layer formed in the trenches of the circuit region through a plating process and including a circuit pattern and vias. Thanks to formation of the trenches in the dummy region and the cutting region, deviation in thickness of a plating layer formed on the insulating layer in a plating process is improved upon.
摘要翻译：这里公开了沟槽衬底及其制造方法。沟槽基板包括基底基板，形成在基底基板的一侧或两侧上的绝缘层，并且包括形成在电路区域中的沟槽和位于沟槽基板的周边边缘的虚设区域，以及电路层，通过电镀工艺的电路区域的沟槽，并且包括电路图案和通孔。由于在虚拟区域和切割区域中形成沟槽，因此在电镀工艺中在绝缘层上形成的镀层的厚度偏差得到改善。

6. 发明授权

US08574444B2 Fabricating method for multilayer printed circuit board 失效
标题翻译：多层印刷电路板的制造方法
公开(公告)号：US08574444B2
公开(公告)日：2013-11-05
申请号：US13585301
申请日：2012-08-14
申请人： Ryoichi Watanabe
发明人： Ryoichi Watanabe
IPC分类号： H05K3/00
CPC分类号： H05K3/0014 , H05K3/045 , H05K3/107 , H05K3/465 , H05K3/4682 , H05K2201/0376 , H05K2203/0156 , H05K2203/0264 , H05K2203/0537 , H05K2203/0769 , H05K2203/308
摘要： A method of fabricating a multilayer printed circuit board includes forming a first circuit-forming pattern and a via-forming pattern on a first carrier, and forming a first insulation layer; repeatedly forming inner circuit patterns and inner insulation layers over the first insulation layer by forming circuit-forming patterns and imprinting, and forming inner vias connecting the inner circuit patterns positioned on different insulation layers; forming a second circuit-forming pattern on a second carrier and inserting the first circuit-forming pattern and the second circuit-forming pattern respectively into the first insulation layer and a second insulation layer; removing the first carrier and the second carrier; forming circuit-forming grooves by removing the first circuit-forming pattern and the second circuit-forming pattern, and forming via-forming indentations connected with the circuit-forming grooves; and forming outer circuit patterns and outer vias by filling the circuit-forming grooves and the via-forming indentations with a conductive material.
摘要翻译：一种制造多层印刷电路板的方法包括在第一载体上形成第一电路形成图案和通路形成图案，并形成第一绝缘层; 通过形成电路形成图案和压印，在第一绝缘层上反复形成内部电路图案和内部绝缘层，并形成连接位于不同绝缘层上的内部电路图案的内部通孔; 在第二载体上形成第二电路形成图案，并将第一电路形成图案和第二电路形成图案分别插入第一绝缘层和第二绝缘层中; 移除所述第一载体和所述第二载体; 通过去除第一电路形成图案和第二电路形成图案形成电路形成槽，以及形成与电路形成槽连接的通孔形成凹陷; 以及通过用导电材料填充电路形成槽和通孔形成凹陷来形成外部电路图案和外部通孔。

7. 发明授权

US07675681B2 Display device 有权
标题翻译：显示设备
公开(公告)号：US07675681B2
公开(公告)日：2010-03-09
申请号：US11971964
申请日：2008-01-10
申请人： Masahiko Tomikawa , Ryoichi Watanabe , Takashi Sasabayashi
发明人： Masahiko Tomikawa , Ryoichi Watanabe , Takashi Sasabayashi
IPC分类号： G02B27/10 , G02B9/00
CPC分类号： G02B27/2214
摘要： A display device includes a lens array unit, a display unit which is configured such that a first substrate is attached to a second substrate that is disposed between the first substrate and the lens array unit, the display unit having a display area composed of matrix-arrayed pixels, a gap control layer which forms a predetermined gap between the display unit and the lens array unit, and a support member which fixes the display unit and the lens array unit on an outside of the display area of the display unit.
摘要翻译：一种显示装置，包括透镜阵列单元，显示单元，被配置为使得第一基板附着到设置在第一基板和透镜阵列单元之间的第二基板，显示单元具有由矩阵状单元组成的显示区域，排列的像素，在显示单元和透镜阵列单元之间形成预定间隙的间隙控制层，以及将显示单元和透镜阵列单元固定在显示单元的显示区域的外部的支撑构件。

8. 发明申请

US20090014411A1 Fabricating method for multilayer printed circuit board 失效
标题翻译：多层印刷电路板的制造方法
公开(公告)号：US20090014411A1
公开(公告)日：2009-01-15
申请号：US12076431
申请日：2008-03-18
申请人： Ryoichi Watanabe
发明人： Ryoichi Watanabe
IPC分类号： B05D5/12 , H01B13/00
CPC分类号： H05K3/0014 , H05K3/045 , H05K3/107 , H05K3/465 , H05K3/4682 , H05K2201/0376 , H05K2203/0156 , H05K2203/0264 , H05K2203/0537 , H05K2203/0769 , H05K2203/308
摘要： A fabrication method for a multilayer printed circuit board includes: forming a first circuit-forming pattern and a first insulation layer, into which the first circuit-forming pattern is inserted, on a first carrier; forming inner circuit patterns and inner insulation layers over the first insulation layer, and forming inner vias connecting the inner circuit patterns positioned on different insulation layers; forming a second circuit-forming pattern on a second carrier and inserting the second circuit-forming pattern into a second insulation layer on an outermost side; removing the first carrier and the second carrier; forming circuit-forming grooves by removing the first circuit-forming pattern and the second circuit-forming pattern, and forming via-forming indentations connected with the circuit-forming grooves; and forming outer circuit patterns and outer vias by filling the circuit-forming grooves and the via-forming indentations with a conductive material. This can provide a thin printed circuit board having high reliability and fine-lined circuits.
摘要翻译：一种多层印刷电路板的制造方法包括：在第一载体上形成第一电路形成图案和第一电路形成图案插入其中的第一绝缘层; 在所述第一绝缘层上形成内部电路图案和内部绝缘层，以及形成连接位于不同绝缘层上的内部电路图案的内部通孔; 在第二载体上形成第二电路形成图案，并将第二电路形成图案插入最外侧的第二绝缘层; 移除所述第一载体和所述第二载体; 通过去除第一电路形成图案和第二电路形成图案形成电路形成槽，以及形成与电路形成槽连接的通孔形成凹陷; 以及通过用导电材料填充电路形成槽和通孔形成凹陷来形成外部电路图案和外部通孔。这可以提供具有高可靠性和细线电路的薄印刷电路板。

9. 发明授权

US5947175A Multi-piece rim 失效
标题翻译：多件式边缘
公开(公告)号：US5947175A
公开(公告)日：1999-09-07
申请号：US988406
申请日：1997-12-10
申请人： Ryoichi Watanabe , Kenji Yoshii , Ichiro Takeuchi
发明人： Ryoichi Watanabe , Kenji Yoshii , Ichiro Takeuchi
IPC分类号： B60B21/00 , B05D1/36 , B05D5/00 , B05D7/24 , B60B25/04 , B60B25/18
CPC分类号： B60B25/22 , B60B25/04 , B60B25/18
摘要： A multi-piece rim includes a lock ring and a gutter band having a lock ring groove. The lock ring groove includes a bottom surface, axially inboard and outboard curved surfaces connected to opposite ends of the bottom surface, and axially inboard and outboard side surfaces connected to the axially inboard and outboard curved surfaces. A lock ring escaping groove is formed at a transition point from the axially outboard curved surface to the axially outboard side surface and a surface portion adjacent to the transition point. The lock ring escaping groove is recessed in a direction away from the lock ring.
摘要翻译：多件式边缘包括锁定环和具有锁定环槽的沟槽带。锁定环槽包括底面，轴向内侧和外侧弯曲表面，其连接到底表面的相对端，以及轴向内侧和外侧侧表面，其连接到轴向内侧和外侧弯曲表面。在从轴向外侧弯曲表面到轴向外侧表面的过渡点和与过渡点相邻的表面部分处形成锁定环逃逸槽。锁定环脱出槽沿远离锁定环的方向凹陷。

10. 发明授权

US07537668B2 Method of fabricating high density printed circuit board 失效
标题翻译：制造高密度印刷电路板的方法
公开(公告)号：US07537668B2
公开(公告)日：2009-05-26
申请号：US11146779
申请日：2005-06-06
申请人： Ryoichi Watanabe
发明人： Ryoichi Watanabe
IPC分类号： B32B37/12 , B32B38/10 , C23C20/00 , H05K1/16 , B32B37/16 , C23C24/02
CPC分类号： H05K3/205 , H05K2203/0156 , H05K2203/016 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T156/1064 , Y10T156/1082
摘要： A method of fabricating a high density printed circuit board by applying a strippable adhesive layer on a reinforced substrate (rigid substrate or carrier film) used as a base substrate, forming a metal foil on the adhesive layer by means of plating, lamination or sputtering, and forming a high density circuit on the metal foil serving as a seed layer by means of pattern plating. Specifically, the method of the current invention includes the steps of attaching adhesive means to one surface of a reinforced substrate (rigid substrate or carrier film), forming a seed layer on the adhesive means and forming a circuit pattern on the seed layer, laminating an insulating layer on the circuit pattern and removing the reinforced substrate (rigid substrate or carrier film), and removing the seed layer.
摘要翻译：一种通过在用作基底基板的增强基板（刚性基板或载体膜）上涂覆可剥离粘合剂层来制造高密度印刷电路板的方法，通过电镀，层压或溅射在粘合剂层上形成金属箔，并且通过图案电镀在用作种子层的金属箔上形成高密度电路。具体而言，本发明的方法包括以下步骤：将胶粘剂粘合到加强基材（刚性基材或载体膜）的一个表面上，在粘合剂装置上形成晶种层，并在种子层上形成电路图案，绝缘层，并去除加强基板（刚性基板或载体膜），并移除种子层。

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