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1. 发明授权

US09099242B2 Laminated chip electronic component, board for mounting the same, and packing unit thereof 有权
标题翻译：层叠芯片电子部件，用于安装其的基板及其包装单元
公开(公告)号：US09099242B2
公开(公告)日：2015-08-04
申请号：US13588696
申请日：2012-08-17
申请人： Young Ghyu Ahn , Sang Soo Park , Min Cheol Park , Se Hwa Jeong
发明人： Young Ghyu Ahn , Sang Soo Park , Min Cheol Park , Se Hwa Jeong
IPC分类号： H05K1/16 , H01G4/005 , H05K1/02 , H01G4/30
CPC分类号： H01G4/005 , H01G4/30 , H05K1/0271 , H05K1/111 , H05K3/3442 , H05K2201/09427 , H05K2201/10015 , H05K2201/10636 , H05K2201/2045 , Y02P70/611
摘要： A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; and upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer.
摘要翻译：层叠芯片电子部件包括：陶瓷体，其包括内部电极和电介质层; 形成为在长度方向上覆盖陶瓷体的两端部的外部电极; 其中内部电极以相对的方式设置在其间插入电介质层的有源层以形成电容; 以及在有源层的厚度方向的上部和下部形成的上部和下部覆盖层，所述下部覆盖层的厚度大于上部覆盖层的厚度。

2. 发明申请

US20130319741A1 LAMINATED CHIP ELECTRONIC COMPONENT, BOARD FOR MOUNTING THE SAME, AND PACKING UNIT THEREOF 有权
标题翻译：层压电子元件，用于安装的组件及其包装单元
公开(公告)号：US20130319741A1
公开(公告)日：2013-12-05
申请号：US13588696
申请日：2012-08-17
申请人： Young Ghyu AHN , Sang Soo Park , Min Cheol Park , Se Hwa Jeong
发明人： Young Ghyu AHN , Sang Soo Park , Min Cheol Park , Se Hwa Jeong
IPC分类号： H01G4/12 , H05K7/00 , H05K1/18
CPC分类号： H01G4/005 , H01G4/30 , H05K1/0271 , H05K1/111 , H05K3/3442 , H05K2201/09427 , H05K2201/10015 , H05K2201/10636 , H05K2201/2045 , Y02P70/611
摘要： A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; and upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer.
摘要翻译：层叠芯片电子部件包括：陶瓷体，其包括内部电极和电介质层; 形成为在长度方向上覆盖陶瓷体的两端部的外部电极; 其中内部电极以相对的方式设置在其间插入电介质层的有源层以形成电容; 以及在有源层的厚度方向的上部和下部形成的上部和下部覆盖层，所述下部覆盖层的厚度大于上部覆盖层的厚度。

3. 发明授权

US08351180B1 Multilayer ceramic capacitor 有权
标题翻译：多层陶瓷电容器
公开(公告)号：US08351180B1
公开(公告)日：2013-01-08
申请号：US13531237
申请日：2012-06-22
申请人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
发明人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
IPC分类号： H01G4/06
CPC分类号： H01G4/12 , H01G4/012 , H01G4/30
摘要： There is provided a multilayer ceramic capacitor, including: a multilayer body in which a plurality of dielectric layers are stacked in a thickness direction; and inner electrode layers formed within the multilayer body and including first and second inner electrodes disposed to be opposed to each other; wherein a ratio (MA1/CA1) of MA1 to CA1 is between 0.07 and 0.20, wherein CA1 represents an area of the multilayer body in a cross section of the multilayer body taken in a length and thickness direction, and MA1 represents an area of a first margin part in the cross section of the multilayer body taken in the length and thickness direction, the first margin part being a portion of the multilayer body, other than a first capacitance forming part thereof in which the first and second inner electrodes overlap in the thickness direction.
摘要翻译：提供了一种多层陶瓷电容器，包括：多层体，其中多个电介质层在厚度方向上堆叠; 以及形成在所述多层体内并且包括彼此相对设置的第一和第二内部电极的内部电极层; 其中MA1与CA1的比率（MA1 / CA1）在0.07和0.20之间，其中CA1表示在长度和厚度方向上取下的多层体的横截面中的多层体的面积，MA1表示第一边缘部分是沿着长度和厚度方向截取的第一边缘部分，第一边缘部分是多层体的一部分，除了第一电容形成部分之外，第一和第二内部电极在其中重叠厚度方向。

4. 发明申请

US20130321981A1 LAMINATED CHIP ELECTRONIC COMPONENT, BOARD FOR MOUNTING THE SAME, AND PACKING UNIT THEREOF 审中-公开
公开(公告)号：US20130321981A1
公开(公告)日：2013-12-05
申请号：US13588876
申请日：2012-08-17
申请人： Young Ghyu AHN , Min Cheol Park , Doo Young Kim , Sang Soo Park
发明人： Young Ghyu AHN , Min Cheol Park , Doo Young Kim , Sang Soo Park
IPC分类号： H05K7/00 , H01L41/00 , H01C7/13 , H01G4/12 , H01C7/10
CPC分类号： H01G4/30 , B65B9/04 , B65B15/04 , H01G2/065 , H01G4/012 , H01G4/12 , H05K1/181 , H05K2201/10015
摘要： A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; first and second external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer; and additional electrode layers disposed irrespective of a formation of capacitance within the lower cover layer.

5. 发明授权

US08373964B2 Multi-layered ceramic capacitor 有权
标题翻译：多层陶瓷电容
公开(公告)号：US08373964B2
公开(公告)日：2013-02-12
申请号：US13064153
申请日：2011-03-08
申请人： Young Ghyu Ahn , Dong Seok Park , Sang Soo Park , Min Cheol Park , Byoung Hwa Lee
发明人： Young Ghyu Ahn , Dong Seok Park , Sang Soo Park , Min Cheol Park , Byoung Hwa Lee
IPC分类号： H01G4/30 , H01G4/06 , H01G4/228 , H01G4/005
CPC分类号： H01G4/30 , H01G4/005 , H01G4/12
摘要： There is provided a multi-layered ceramic capacitor with reduced internal resistance by forming internal electrode groups including internal electrodes having different lengths. The multi-layered ceramic capacitor of the present invention includes a sintered ceramic body part in which cover layers are provided on both surfaces thereof as an outermost layer and a plurality of ceramic layers are stacked therebetween, first and second external electrodes each formed on an outer surface of the sintered ceramic body part, a plurality of first and second internal electrode groups adjacent to each other in a stacking direction of the plurality of ceramic layers, having the ceramic layer therebetween, and including 2N or 2N+1 (N is an integer number larger than 1) internal electrodes electrically connected to the first and second external electrodes, wherein the 2N or 2N+1 (N is an integer number larger than 1) internal electrodes are disposed to face at least one internal electrode of other adjacent internal electrode groups. A length of each internal electrode has a pyramid shape.
摘要翻译：通过形成具有不同长度的内部电极的内部电极组，提供具有降低的内部电阻的多层陶瓷电容器。本发明的多层陶瓷电容器包括烧结陶瓷体部分，其两面上设有覆盖层作为最外层，并且多个陶瓷层堆叠在其间，第一和第二外部电极各自形成在外部烧结陶瓷体部的表面，在多个陶瓷层的堆叠方向上彼此相邻的多个第一和第二内部电极组，其间具有陶瓷层，并且包括2N或2N + 1（N是整数大于1的数字）电连接到第一和第二外部电极的内部电极，其中设置2N或2N + 1（N为大于1的整数）的内部电极，以面对其他相邻内部电极的至少一个内部电极团体每个内部电极的长度具有金字塔形状。

6. 发明申请

US20110317327A1 Multi-layered ceramic capacitor 有权
标题翻译：多层陶瓷电容
公开(公告)号：US20110317327A1
公开(公告)日：2011-12-29
申请号：US13064153
申请日：2011-03-08
申请人： Young Ghyu Ahn , Dong Seok Park , Sang Soo Park , Min Cheol Park , Byoung Hwa Lee
发明人： Young Ghyu Ahn , Dong Seok Park , Sang Soo Park , Min Cheol Park , Byoung Hwa Lee
IPC分类号： H01G4/30
CPC分类号： H01G4/30 , H01G4/005 , H01G4/12
摘要： There is provided a multi-layered ceramic capacitor with reduced internal resistance by forming internal electrode groups including internal electrodes having different lengths. The multi-layered ceramic capacitor of the present invention includes a sintered ceramic body part in which cover layers are provided on both surfaces thereof as an outermost layer and a plurality of ceramic layers are stacked therebetween, first and second external electrodes each formed on an outer surface of the sintered ceramic body part, a plurality of first and second internal electrode groups adjacent to each other in a stacking direction of the plurality of ceramic layers, having the ceramic layer therebetween, and including 2N or 2N+1 (N is an integer number larger than 1) internal electrodes electrically connected to the first and second external electrodes, wherein the 2N or 2N+1 (N is an integer number larger than 1) internal electrodes are disposed to face at least one internal electrode of other adjacent internal electrode groups. A length of each internal electrode has a pyramid shape.
摘要翻译：通过形成具有不同长度的内部电极的内部电极组，提供具有降低的内部电阻的多层陶瓷电容器。本发明的多层陶瓷电容器包括烧结陶瓷体部分，其两面上设有覆盖层作为最外层，并且多个陶瓷层堆叠在其间，第一和第二外部电极各自形成在外部烧结陶瓷体部的表面，在多个陶瓷层的堆叠方向上彼此相邻的多个第一和第二内部电极组，其间具有陶瓷层，并且包括2N或2N + 1（N是整数大于1的数字）电连接到第一和第二外部电极的内部电极，其中设置2N或2N + 1（N为大于1的整数）的内部电极，以面对其他相邻内部电极的至少一个内部电极团体每个内部电极的长度具有金字塔形状。

7. 发明授权

US08681475B2 Mounting structure of circuit board having multi-layered ceramic capacitor thereon 有权
标题翻译：具有多层陶瓷电容器的电路板的安装结构
公开(公告)号：US08681475B2
公开(公告)日：2014-03-25
申请号：US13590270
申请日：2012-08-21
申请人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
发明人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
IPC分类号： H01G4/06
CPC分类号： H01G4/12 , H01G4/228 , H01G4/30
摘要： Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, the multi-layered ceramic capacitor including dielectric sheets laminated thereon and external terminal electrodes formed at both ends thereof, the dielectric sheets having internal electrodes formed thereon, and the external terminal electrodes being connected in parallel with the internal electrode, wherein the internal electrodes are disposed to be in parallel with the circuit board, the external terminal electrodes are bonded to lands of the circuit board by a conductive material, and a bonding height (Ts) of the conductive material is lower than a sum of a gap (Ta) between the circuit board and a bottom surface of the multi-layered ceramic capacitor and a thickness (Tc) of a cover layer on a lower portion of the multi-layered ceramic capacitor, whereby vibration noise can be greatly reduced.
摘要翻译：这里公开了一种其上具有多层陶瓷电容器的电路板的安装结构，其中层叠有电介质片的多层陶瓷电容器和形成在其两端的外部端子电极，其上形成有内部电极的电介质片，以及外部端子电极与内部电极并联连接，其中内部电极被设置为与电路板平行，外部端子电极通过导电材料接合到电路板的焊盘，并且接合高度 Ts）低于多层陶瓷电容器的电路板和底面之间的间隙（Ta）和多层陶瓷电容器的下表面的覆盖层的厚度（Tc）之和，层状陶瓷电容器，从而可以大大降低振动噪声。

8. 发明申请

US20120298407A1 MOUNTING STRUCTURE OF CIRCUIT BOARD HAVING MULTI-LAYERED CERAMIC CAPACITOR THEREON 有权
标题翻译：具有多层陶瓷电容器的电路板的安装结构
公开(公告)号：US20120298407A1
公开(公告)日：2012-11-29
申请号：US13481348
申请日：2012-05-25
申请人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
发明人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
IPC分类号： H05K1/16
CPC分类号： H05K1/111 , H01G4/12 , H01G4/30 , H05K3/3442 , H05K2201/10015 , H05K2201/2045 , Y02P70/611 , Y02P70/613
摘要： Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon. The mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, in which a dielectric layer on which inner electrodes are disposed is stacked and external electrode terminals connecting the inner electrodes in parallel are disposed on both ends thereof, wherein the inner electrodes of the multi-layered ceramic capacitor and the circuit board are disposed so as to be a horizontal direction to connect the external electrode terminals with a land on the circuit board by a conductive material and a ratio of a bonding area ASOLEDER of the conductive material to the area AMLCC of the external electrode terminals AMLCC is set to be less than 1.4, thereby remarkably reducing the vibration noise.
摘要翻译：这里公开了一种其上具有多层陶瓷电容器的电路板的安装结构。其上设置有多层陶瓷电容器的电路板的安装结构，其中布置有内部电极的电介质层，并且将其内部电极并联连接的外部电极端子设置在其两端，其中内部电极将多层陶瓷电容器和电路板设置成水平方向，以通过导电材料将导电材料的外部电极端子与电路板上的焊盘接合，并且将导电材料的接合面积ASOLEDER与外部电极端子AMLCC的面积AMLCC被设定为小于1.4，从而显着地降低了振动噪声。

9. 发明申请

US20120152604A1 MOUNTING STRUCTURE OF CIRCUIT BOARD HAVING THEREON MULTI-LAYERED CERAMIC CAPACITOR, METHOD THEREOF, LAND PATTERN OF CIRCUIT BOARD FOR THE SAME, PACKING UNIT FOR MULTI-LAYERED CERAMIC CAPACITOR TAPED HORIZONTALLY AND ALIGNING METHOD THEREOF 审中-公开
标题翻译：具有多层陶瓷电容器的电路板的安装结构，其方法，电路板的土地图案，多层陶瓷电容器的包装单元和水平方法
公开(公告)号：US20120152604A1
公开(公告)日：2012-06-21
申请号：US13331619
申请日：2011-12-20
申请人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
发明人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
IPC分类号： H05K1/18 , H05K3/00 , H01G4/30
CPC分类号： H01G2/065 , H01G4/232 , H01G4/30 , H05K3/3442 , H05K13/022 , H05K2201/10015 , H05K2203/166 , Y02P70/613 , Y10T29/49124
摘要： The present invention provides a method of mounting a circuit board having thereon a multi-layered ceramic capacitor and a land pattern of a circuit board for the same. The method of mounting a circuit board having thereon a multi-layered ceramic capacitor on which a plurality of dielectric sheet having internal electrodes formed thereon are stacked and the external terminal electrodes connected to the internal electrodes in parallel are formed on both ends thereof includes conductively connecting lands of a circuit board to the external terminal electrodes in such a way that internal electrode layers of the multi-layered ceramic capacitor and the circuit board are arranged in a horizontal direction, wherein a height TS of conductive material to conductively connect the external terminal electrodes to the lands is less than ⅓ of a thickness TMLCC of the multi-layered ceramic capacitor.
摘要翻译：本发明提供了一种安装电路板的方法，其上具有多层陶瓷电容器和用于其的电路板的焊盘图案。在其上堆叠有多层陶瓷电容器的电路板的方法，其上形成有形成有内部电极的多个电介质层，并且在其两端形成有与内部电极并联连接的外部端子电极的方法包括导电连接电路板的接地部分以外部端子电极的方式使多层陶瓷电容器和电路板的内部电极层沿水平方向排列，其中导电材料的高度TS导电连接外部端子电极到土地的厚度小于多层陶瓷电容器的厚度TMLCC的1/3。

10. 发明授权

US08638543B2 Laminated chip electronic component, board for mounting the same, and packing unit thereof 有权
标题翻译：层叠芯片电子部件，用于安装其的基板及其包装单元
公开(公告)号：US08638543B2
公开(公告)日：2014-01-28
申请号：US13588876
申请日：2012-08-17
申请人： Young Ghyu Ahn , Min Cheol Park , Doo Young Kim , Sang Soo Park
发明人： Young Ghyu Ahn , Min Cheol Park , Doo Young Kim , Sang Soo Park
IPC分类号： H01G4/06 , H01G4/005
CPC分类号： H01G4/30 , B65B9/04 , B65B15/04 , H01G2/065 , H01G4/012 , H01G4/12 , H05K1/181 , H05K2201/10015
摘要： A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; first and second external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer; and additional electrode layers disposed irrespective of a formation of capacitance within the lower cover layer.
摘要翻译：层叠芯片电子部件包括：陶瓷体，其包括内部电极和电介质层; 形成为在长度方向上覆盖陶瓷体的两端部的第一外部电极和第二外部电极; 其中内部电极以相对的方式设置在其间插入电介质层的有源层以形成电容; 上下层形成在有源层的厚度方向的上部和下部上，下覆盖层的厚度大于上覆盖层的厚度; 以及与下覆盖层内的电容的形成无关地设置的附加电极层。

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