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1. 发明申请

US20120298407A1 MOUNTING STRUCTURE OF CIRCUIT BOARD HAVING MULTI-LAYERED CERAMIC CAPACITOR THEREON 有权
标题翻译：具有多层陶瓷电容器的电路板的安装结构
公开(公告)号：US20120298407A1
公开(公告)日：2012-11-29
申请号：US13481348
申请日：2012-05-25
申请人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
发明人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
IPC分类号： H05K1/16
CPC分类号： H05K1/111 , H01G4/12 , H01G4/30 , H05K3/3442 , H05K2201/10015 , H05K2201/2045 , Y02P70/611 , Y02P70/613
摘要： Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon. The mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, in which a dielectric layer on which inner electrodes are disposed is stacked and external electrode terminals connecting the inner electrodes in parallel are disposed on both ends thereof, wherein the inner electrodes of the multi-layered ceramic capacitor and the circuit board are disposed so as to be a horizontal direction to connect the external electrode terminals with a land on the circuit board by a conductive material and a ratio of a bonding area ASOLEDER of the conductive material to the area AMLCC of the external electrode terminals AMLCC is set to be less than 1.4, thereby remarkably reducing the vibration noise.
摘要翻译：这里公开了一种其上具有多层陶瓷电容器的电路板的安装结构。其上设置有多层陶瓷电容器的电路板的安装结构，其中布置有内部电极的电介质层，并且将其内部电极并联连接的外部电极端子设置在其两端，其中内部电极将多层陶瓷电容器和电路板设置成水平方向，以通过导电材料将导电材料的外部电极端子与电路板上的焊盘接合，并且将导电材料的接合面积ASOLEDER与外部电极端子AMLCC的面积AMLCC被设定为小于1.4，从而显着地降低了振动噪声。

2. 发明申请

US20120275081A1 MULTI-LAYERED CAPACITOR AND MANUFACTURING METHOD THEREOF 有权
标题翻译：多层电容器及其制造方法
公开(公告)号：US20120275081A1
公开(公告)日：2012-11-01
申请号：US13447692
申请日：2012-04-16
申请人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
发明人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
IPC分类号： H01G4/30
CPC分类号： H01G4/232 , H01G4/12 , H01G4/30 , H01G4/35
摘要： A multi-layered capacitor includes a capacitor element in which a plurality of dielectric layers are multi-layered, and which comprises a first inner electrode and a second inner electrode that are alternately formed on neighboring dielectric layers of the plurality of dielectric layers, a first external electrode and a second external electrode which are formed on an outside surface of the capacitor element to be electrically connected to the first inner electrode and the second inner electrode, respectively, and a deformation suppressing electrode which is formed on the outside surface of the capacitor element and separated from the first external electrode and the second external electrode to be electrically isolated from the first inner electrode and the second inner electrode.
摘要翻译：多层电容器包括电容器元件，其中多个电介质层是多层的，并且包括交替地形成在多个电介质层的相邻电介质层上的第一内电极和第二内电极，第一外部电极和第二外部电极，分别形成在电容器元件的外表面上以与第一内部电极和第二内部电极电连接;变形抑制电极，形成在电容器的外表面上并且与第一外部电极和第二外部电极分离以与第一内部电极和第二内部电极电隔离。

3. 发明申请

US20130050894A1 MOUNTING STRUCTURE OF CIRCUIT BOARD HAVING MULTI-LAYERED CERAMIC CAPACITOR THEREON 有权
标题翻译：具有多层陶瓷电容器的电路板的安装结构
公开(公告)号：US20130050894A1
公开(公告)日：2013-02-28
申请号：US13590270
申请日：2012-08-21
申请人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
发明人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
IPC分类号： H01G4/228 , H01G4/12
CPC分类号： H01G4/12 , H01G4/228 , H01G4/30
摘要： Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, the multi-layered ceramic capacitor including dielectric sheets laminated thereon and external terminal electrodes formed at both ends thereof, the dielectric sheets having internal electrodes formed thereon, and the external terminal electrodes being connected in parallel with the internal electrode, wherein the internal electrodes are disposed to be in parallel with the circuit board, the external terminal electrodes are bonded to lands of the circuit board by a conductive material, and a bonding height (Ts) of the conductive material is lower than a sum of a gap (Ta) between the circuit board and a bottom surface of the multi-layered ceramic capacitor and a thickness (Tc) of a cover layer on a lower portion of the multi-layered ceramic capacitor, whereby vibration noise can be greatly reduced.
摘要翻译：这里公开了一种其上具有多层陶瓷电容器的电路板的安装结构，其中层叠有电介质片的多层陶瓷电容器和形成在其两端的外部端子电极，其上形成有内部电极的电介质片，以及外部端子电极与内部电极并联连接，其中内部电极被设置为与电路板平行，外部端子电极通过导电材料接合到电路板的焊盘，并且接合高度 Ts）低于多层陶瓷电容器的电路板和底面之间的间隙（Ta）和多层陶瓷电容器的下表面的覆盖层的厚度（Tc）之和，层状陶瓷电容器，从而可以大大降低振动噪声。

4. 发明申请

US20120327556A1 MULTILAYER CERAMIC CAPACITOR 有权
标题翻译：多层陶瓷电容器
公开(公告)号：US20120327556A1
公开(公告)日：2012-12-27
申请号：US13531237
申请日：2012-06-22
申请人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
发明人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
IPC分类号： H01G4/12
CPC分类号： H01G4/12 , H01G4/012 , H01G4/30
摘要： There is provided a multilayer ceramic capacitor, including: a multilayer body in which a plurality of dielectric layers are stacked in a thickness direction; and inner electrode layers formed within the multilayer body and including first and second inner electrodes disposed to be opposed to each other; wherein a ratio (MA1/CA1) of MA1 to CA1 is between 0.07 and 0.20, wherein CA1 represents an area of the multilayer body in a cross section of the multilayer body taken in a length and thickness direction, and MA1 represents an area of a first margin part in the cross section of the multilayer body taken in the length and thickness direction, the first margin part being a portion of the multilayer body, other than a first capacitance forming part thereof in which the first and second inner electrodes overlap in the thickness direction.
摘要翻译：提供了一种多层陶瓷电容器，包括：多层体，其中多个电介质层在厚度方向上堆叠; 以及形成在所述多层体内并且包括彼此相对设置的第一和第二内部电极的内部电极层; 其中MA1与CA1的比率（MA1 / CA1）在0.07和0.20之间，其中CA1表示在长度和厚度方向上取下的多层体的横截面中的多层体的面积，MA1表示第一边缘部分是沿着长度和厚度方向截取的第一边缘部分，第一边缘部分是多层体的一部分，除了第一电容形成部分之外，第一和第二内部电极在其中重叠厚度方向。

5. 发明申请

US20120268875A1 MOUNTING STRUCTURE OF CIRCUIT BOARD HAVING THEREON MULTI-LAYERED CERAMIC CAPACITOR, METHOD THEREOF, LAND PATTERN OF CIRCUIT BOARD FOR THE SAME, PACKING UNIT FOR MULTI-LAYERED CERAMIC CAPACITOR TAPED HORIZONTALLY AND ALIGNING METHOD THEREOF 审中-公开
标题翻译：具有多层陶瓷电容器的电路板的安装结构，其方法，电路板的土地图案，多层陶瓷电容器的包装单元和水平方法
公开(公告)号：US20120268875A1
公开(公告)日：2012-10-25
申请号：US13540055
申请日：2012-07-02
申请人： Young Ghyu AHN , Byoung Hwa LEE , Min Cheol PARK , Sang Soo PARK , Dong Seok PARK
发明人： Young Ghyu AHN , Byoung Hwa LEE , Min Cheol PARK , Sang Soo PARK , Dong Seok PARK
IPC分类号： H05K7/00 , B67C3/22
CPC分类号： H01G2/065 , H01G4/232 , H01G4/30 , H05K3/3442 , H05K13/022 , H05K2201/10015 , H05K2203/166 , Y02P70/613 , Y10T29/49124
摘要： A packing unit for a plurality of multi-layered ceramic capacitors including: a plurality of multi-layered ceramic capacitors having a thickness TMLCC equal or similar to a width WMLCC; and a packing sheet including a plurality of storing spaces, the capacitors being stored in the storing spaces and internal electrodes of each capacitor being substantially parallel with a bottom of the storing space. A related method includes: transferring a plurality of multi-layered ceramic capacitors having a thickness TMLCC equal or similar to a width WMLCC through a transferring unit; supplying magnetic field to a side of the capacitor so that the internal electrodes of the capacitor are substantially parallel with a bottom of the transferring unit; and storing the multi-layered ceramic capacitor in a storing space of a packing sheet so that the internal electrodes of the capacitor are substantially parallel with a bottom of the storing space.
摘要翻译：一种用于多层陶瓷电容器的包装单元，包括：多个多层陶瓷电容器，其厚度TMLCC等于或类似于宽度WMLCC; 以及包括多个存储空间的包装纸，所述电容器存储在所述存储空间中，并且每个电容器的内部电极基本上与所述存储空间的底部平行。相关方法包括：通过传送单元将具有与宽度WMLCC相等或类似的厚度TMLCC的多个多层陶瓷电容器传送; 向电容器的一侧供给磁场，使得电容器的内部电极基本上平行于转印单元的底部; 以及将所述多层陶瓷电容器存储在包装薄片的收纳空间中，使得所述电容器的内部电极基本上与所述收容空间的底部平行。

6. 发明申请

US20120327555A1 CHIP TYPE LAMINATED CAPACITOR 有权
标题翻译：芯片型层压电容器
公开(公告)号：US20120327555A1
公开(公告)日：2012-12-27
申请号：US13529766
申请日：2012-06-21
申请人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Young Hoon Song , Mi Hee Lee
发明人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Young Hoon Song , Mi Hee Lee
IPC分类号： H01G4/12
CPC分类号： H01G4/01 , H01G4/12 , H01G4/232 , H01G4/30
摘要： There is provided a chip type laminated capacitor, including: a ceramic body including a dielectric layer having a thickness equal to 10 or more times an average particle diameter of a grain included therein and being 3 □m or less; first and second outer electrodes formed on both ends of the ceramic body in a length direction; first and second band parts formed to extend inwardly of the ceramic body in the length direction on a length-width (L-W) plane from the first and second outer electrodes and having different lengths; and third and fourth band parts formed to extend inwardly of the ceramic body in the length direction on a length-thickness (L-T) plane from the first and second outer electrodes and having different lengths.
摘要翻译：提供了一种片式叠层电容器，其包括：陶瓷体，其包括厚度等于其中包含的晶粒的平均粒径的10倍以上且为3μm以下的电介质层; 第一外电极和第二外电极，其在长度方向上形成在陶瓷体的两端; 第一和第二带部分形成为在第一和第二外部电极的长度（L-W）平面上沿长度方向在陶瓷体的内部延伸并具有不同的长度; 以及第三和第四带部分，其形成为在长度方向上在距第一和第二外部电极的长度 - 厚度（L-T）平面上延伸到陶瓷体的内侧并具有不同的长度。

7. 发明申请

US20120327557A1 CHIP TYPE LAMINATED CAPACITOR 有权
标题翻译：芯片型层压电容器
公开(公告)号：US20120327557A1
公开(公告)日：2012-12-27
申请号：US13531242
申请日：2012-06-22
申请人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Young Hoon Song , Mi Hee Lee
发明人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Young Hoon Song , Mi Hee Lee
IPC分类号： H01G4/12
CPC分类号： H01G4/1272 , H01G2/065 , H01G4/005 , H01G4/12 , H01G4/228 , H01G4/232 , H01G4/30
摘要： There is provided a chip type laminated capacitor including: a ceramic body formed by laminating a dielectric layer having a thickness equal to 10 or more times an average particle diameter of a grain included therein and being 3 μm or less; first and second outer electrodes; a first inner electrode having one end forming a first margin together with one end surface of the ceramic body at which the second outer electrode is formed and the other end leading to the first outer electrode; and a second inner electrode having one end forming a second margin together with the other end surface of the ceramic body at which the first outer electrode is formed and the other end leading to the second outer electrode, wherein the first and second margins have different widths under a condition that they are 200 μm or less.
摘要翻译：提供一种芯片型层叠电容器，其包括：陶瓷体，其通过层叠厚度等于其中包含的晶粒的平均粒径的10倍以上且为3μm以下的电介质层而形成; 第一和第二外部电极; 第一内部电极，其一端与形成有第二外部电极的陶瓷体的一个端面一起形成第一边缘，而另一端通向第一外部电极; 以及第二内部电极，其一端与形成有第一外部电极的陶瓷体的另一个端面一起形成第二边缘，另一端通向第二外部电极，其中第一和第二边缘具有不同的宽度在200μm以下的条件下。

8. 发明申请

US20130321981A1 LAMINATED CHIP ELECTRONIC COMPONENT, BOARD FOR MOUNTING THE SAME, AND PACKING UNIT THEREOF 审中-公开
公开(公告)号：US20130321981A1
公开(公告)日：2013-12-05
申请号：US13588876
申请日：2012-08-17
申请人： Young Ghyu AHN , Min Cheol Park , Doo Young Kim , Sang Soo Park
发明人： Young Ghyu AHN , Min Cheol Park , Doo Young Kim , Sang Soo Park
IPC分类号： H05K7/00 , H01L41/00 , H01C7/13 , H01G4/12 , H01C7/10
CPC分类号： H01G4/30 , B65B9/04 , B65B15/04 , H01G2/065 , H01G4/012 , H01G4/12 , H05K1/181 , H05K2201/10015
摘要： A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; first and second external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer; and additional electrode layers disposed irrespective of a formation of capacitance within the lower cover layer.

9. 发明申请

US20120092090A1 COUPLING STRUCTURE FOR MULTI-LAYERED CHIP FILTER, AND MULTI-LAYERED CHIP FILTER WITH THE STRUCTURE 有权
标题翻译：多层芯片滤波器的耦合结构和结构的多层芯片滤波器
公开(公告)号：US20120092090A1
公开(公告)日：2012-04-19
申请号：US13109647
申请日：2011-05-17
申请人： Young Ghyu AHN , Dong Seok PARK , Sang Soo PARK , Sung Jin PARK , Young Sun PARK , Bong Sup LIM
发明人： Young Ghyu AHN , Dong Seok PARK , Sang Soo PARK , Sung Jin PARK , Young Sun PARK , Bong Sup LIM
IPC分类号： H01P1/203
CPC分类号： H01P1/20345 , H01P5/02
摘要： Disclosed herein are a coupling structure for a multi-layered chip filter capable of overcoming a limitation of an existing coupling by improving a coupling structure and a multi-layered chip filter with the structure.The coupling structure according to an exemplary embodiment of the present invention includes: at least two overlap portion patterns each overlapped with a pattern formed on a resonator layer stacked therewith to form at least two overlap areas spaced from each other; and a connecting portion pattern formed by connecting at least three linear lines having a predetermined length to each other to connect the at least two overlap portion patterns to each other.
摘要翻译：这里公开了一种用于通过改进耦合结构来克服现有耦合的限制的多层芯片滤波器的耦合结构和具有该结构的多层芯片滤波器。根据本发明的示例性实施例的耦合结构包括：至少两个重叠部分图案，每个重叠部分图案与形成在其上堆叠的谐振器层上的图案重叠以形成彼此间隔开的至少两个重叠区域; 以及通过将具有预定长度的至少三条线性线彼此连接而形成的连接部分图案，以将至少两个重叠部分图案彼此连接。

10. 发明申请

US20130319741A1 LAMINATED CHIP ELECTRONIC COMPONENT, BOARD FOR MOUNTING THE SAME, AND PACKING UNIT THEREOF 有权
标题翻译：层压电子元件，用于安装的组件及其包装单元
公开(公告)号：US20130319741A1
公开(公告)日：2013-12-05
申请号：US13588696
申请日：2012-08-17
申请人： Young Ghyu AHN , Sang Soo Park , Min Cheol Park , Se Hwa Jeong
发明人： Young Ghyu AHN , Sang Soo Park , Min Cheol Park , Se Hwa Jeong
IPC分类号： H01G4/12 , H05K7/00 , H05K1/18
CPC分类号： H01G4/005 , H01G4/30 , H05K1/0271 , H05K1/111 , H05K3/3442 , H05K2201/09427 , H05K2201/10015 , H05K2201/10636 , H05K2201/2045 , Y02P70/611
摘要： A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; and upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer.
摘要翻译：层叠芯片电子部件包括：陶瓷体，其包括内部电极和电介质层; 形成为在长度方向上覆盖陶瓷体的两端部的外部电极; 其中内部电极以相对的方式设置在其间插入电介质层的有源层以形成电容; 以及在有源层的厚度方向的上部和下部形成的上部和下部覆盖层，所述下部覆盖层的厚度大于上部覆盖层的厚度。

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