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    • 7. 发明授权
    • Active power dissipation detection based on erroneus clock gating equations
    • 基于错误时钟门控方程的有功功耗检测
    • US09495490B2
    • 2016-11-15
    • US13550207
    • 2012-07-16
    • Christopher M AbernathyMaarten J. BoersmaMarkus KaltenbachUlrike Schmidt
    • Christopher M AbernathyMaarten J. BoersmaMarkus KaltenbachUlrike Schmidt
    • G06F17/50
    • G06F17/5022G06F2217/78
    • A method detects active power dissipation in an integrated circuit. The method includes receiving a hardware design for the integrated circuit having one or more clock domains, wherein the hardware design comprises a local clock buffer for a clock domain, wherein the local clock buffer is configured to receive a clock signal and an actuation signal. The method includes adding instrumentation logic to the design for the clock domain, wherein the instrumentation logic is configured to compare a first value of the actuation signal determined at a beginning point of a test period to a second value of the actuation signal determined at a time when the clock domain is in an idle condition. The method includes detecting the clock domain includes unintended active power dissipation, in response to the first value of the actuation signal not being equal to the second value of the actuation signal.
    • 一种方法可以检测集成电路中的有功功率。 该方法包括接收具有一个或多个时钟域的集成电路的硬件设计,其中硬件设计包括用于时钟域的本地时钟缓冲器,其中本地时钟缓冲器被配置为接收时钟信号和致动信号。 该方法包括将仪器逻辑添加到时钟域的设计中,其中仪器逻辑被配置为将在测试周期的起始点确定的致动信号的第一值与每次确定的致动信号的第二值进行比较 当时钟域处于空闲状态时。 响应于致动信号的第一值不等于致动信号的第二值,该方法包括检测时钟域包括非预期的有功功耗。