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1. 发明申请

US20090112554A1 Test Bench, Method, and Computer Program Product for Performing a Test Case on an Integrated Circuit 失效
标题翻译：用于在集成电路上执行测试用例的测试台，方法和计算机程序产品
公开(公告)号：US20090112554A1
公开(公告)日：2009-04-30
申请号：US12247529
申请日：2008-10-08
申请人： Joerg Walter , Lothar Felten , Christopher Smith , Ulrike Schmidt
发明人： Joerg Walter , Lothar Felten , Christopher Smith , Ulrike Schmidt
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/318314 , G06F11/261
摘要： The disclosure relates to a test bench, method, and computer program product for performing a test case on an integrated circuit. The test bench may comprise a simulation environment representing an environment for implementing the integrated circuit and a reference model of the integrated circuit, wherein the reference model may be prepared for running within the simulation environment. The test bench may further comprise a device for running a simulation on the reference model within the simulation environment. The reference model may be based on an original reference model provided for a formal verification.
摘要翻译：本公开涉及用于在集成电路上执行测试用例的测试台，方法和计算机程序产品。测试台可以包括表示用于实现集成电路的环境的模拟环境和集成电路的参考模型，其中参考模型可以准备用于在模拟环境内运行。测试台还可以包括用于在模拟环境内对参考模型运行模拟的装置。参考模型可以基于为正式验证提供的原始参考模型。

2. 发明授权

US08140315B2 Test bench, method, and computer program product for performing a test case on an integrated circuit 失效
标题翻译：用于在集成电路上执行测试用例的测试台，方法和计算机程序产品
公开(公告)号：US08140315B2
公开(公告)日：2012-03-20
申请号：US12247529
申请日：2008-10-08
申请人： Joerg Walter , Lothar Felten , Christopher Smith , Ulrike Schmidt
发明人： Joerg Walter , Lothar Felten , Christopher Smith , Ulrike Schmidt
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/318314 , G06F11/261
摘要： The disclosure relates to a test bench, method, and computer program product for performing a test case on an integrated circuit. The test bench may comprise a simulation environment representing an environment for implementing the integrated circuit and a reference model of the integrated circuit, wherein the reference model may be prepared for running within the simulation environment. The test bench may further comprise a device for running a simulation on the reference model within the simulation environment. The reference model may be based on an original reference model provided for a formal verification.
摘要翻译：本公开涉及用于在集成电路上执行测试用例的测试台，方法和计算机程序产品。测试台可以包括表示用于实现集成电路的环境的模拟环境和集成电路的参考模型，其中参考模型可以准备用于在模拟环境内运行。测试台还可以包括用于在模拟环境内对参考模型运行模拟的装置。参考模型可以基于为正式验证提供的原始参考模型。

3. 发明申请

US20090182545A1 Simulating an Operation of a Digital Circuit 有权
标题翻译：模拟数字电路的操作
公开(公告)号：US20090182545A1
公开(公告)日：2009-07-16
申请号：US12351201
申请日：2009-01-09
申请人： Joerg Walter , Lothar Felten , Volker Urban , Norbert Schumacher , Marcel Naggatz
发明人： Joerg Walter , Lothar Felten , Volker Urban , Norbert Schumacher , Marcel Naggatz
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for simulating an operation of a digital circuit (01) is described. The method utilizes cycle simulation, wherein in a cycle based simulation model (34) of the digital circuit (01) components (02, 03, 04, 05) of the digital circuit (01) are clocked synchronously every cycle (19) of a functional clock (Clk). According to the invention, real digital circuit (01), i.e. chip or combinatorial logic (01), timing information is included in the cycle simulation by inserting delay latches (15, 16, 17) into the cycle based simulation model (34) of the digital circuit (01), wherein a non-functional clock (Sim clock) is used to clock the delay latches (15, 16, 17), so that each delay latch (15, 16, 17) delays the propagation of a signal (I, J, K) by a cycle (20) of the non-functional clock (Sim clock).
摘要翻译：描述用于模拟数字电路（01）的操作的方法。该方法利用循环模拟，其中在数字电路（01）的基于循环的仿真模型（34）中，数字电路（01）的组件（02,03,04,05）在一个周期（19）功能时钟（Clk）。根据本发明，通过将延迟锁存器（15,16,17）插入到基于循环的仿真模型（34）中，实际数字电路（01）即芯片或组合逻辑（01））定时信息被包括在循环模拟中数字电路（01），其中使用非功能时钟（Sim时钟）对延迟锁存器（15,16,17）进行时钟，使得每个延迟锁存器（15,16,17）延迟信号的传播（I，J，K）通过非功能时钟（Sim时钟）的周期（20）。

4. 发明授权

US08346527B2 Simulating an operation of a digital circuit 有权
标题翻译：模拟数字电路的操作
公开(公告)号：US08346527B2
公开(公告)日：2013-01-01
申请号：US12351201
申请日：2009-01-09
申请人： Joerg Walter , Lothar Felten , Volker Urban , Norbert Schumacher , Marcel Naggatz
发明人： Joerg Walter , Lothar Felten , Volker Urban , Norbert Schumacher , Marcel Naggatz
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for simulating an operation of a digital circuit (01) is described. The method utilizes cycle simulation, wherein in a cycle based simulation model (34) of the digital circuit (01) components (02, 03, 04, 05) of the digital circuit (01) are clocked synchronously every cycle (19) of a functional clock (Clk). According to the invention, real digital circuit (01), i.e. chip or combinatorial logic (01), timing information is included in the cycle simulation by inserting delay latches (15, 16, 17) into the cycle based simulation model (34) of the digital circuit (01), wherein a non-functional clock (Sim clock) is used to clock the delay latches (15, 16, 17), so that each delay latch (15, 16, 17) delays the propagation of a signal (I, J, K) by a cycle (20) of the non-functional clock (Sim clock).
摘要翻译：描述用于模拟数字电路（01）的操作的方法。该方法利用循环模拟，其中在数字电路（01）的基于循环的仿真模型（34）中，数字电路（01）的组件（02,03,04,05）在一个周期（19）功能时钟（Clk）。根据本发明，通过将延迟锁存器（15,16,17）插入到基于循环的仿真模型（34）中，实际数字电路（01）即芯片或组合逻辑（01））定时信息被包括在循环模拟中数字电路（01），其中使用非功能时钟（Sim时钟）对延迟锁存器（15,16,17）进行时钟，使得每个延迟锁存器（15,16,17）延迟信号的传播（I，J，K）通过非功能时钟（Sim时钟）的周期（20）。

5. 发明授权

US08117574B2 Implementing a serialization construct within an environment of parallel data flow graphs 有权
标题翻译：在并行数据流图的环境中实现序列化构造
公开(公告)号：US08117574B2
公开(公告)日：2012-02-14
申请号：US12330890
申请日：2008-12-09
申请人： Joerg Deutschle , Harald Gerst , Joerg Walter
发明人： Joerg Deutschle , Harald Gerst , Joerg Walter
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F11/3684 , G01R31/31813 , G01R31/318371
摘要： A serialization construct is implemented within an environment of a number of parallel data flow graphs. A quiesce node is appended to every active data flow graph. The quiesce node prevents a token from passing to a next data flow graph within a chain before an execution of the active data flow graph has been finished. A serial data flow graph is implemented to provided for a serial execution while no other data flow graph is active. A serialize node is appended to a starting point of a serial data flow graph. A serialize end node is appended to an endpoint of the serial data flow graph. The serialize node is activated to start a serial operation. The serialize end node is activated after the serial operation has been terminated.
摘要翻译：序列化构造在多个并行数据流图的环境中实现。静态节点附加到每个活动数据流图。停顿节点在活动数据流图的执行完成之前防止令牌传递到链中的下一个数据流图。实现串行数据流图，以提供串行执行，而没有其他数据流图是活动的。序列化节点附加到串行数据流图的起始点。序列化结束节点附加到串行数据流图的端点。串行化节点被激活以开始串行操作。序列化结束节点在串行操作终止后被激活。

6. 发明申请

US20090172484A1 Method for Implementing a Serialization Construct Within an Environment of Parallel Data Flow Graphs 有权
标题翻译：在并行数据流图的环境下实现序列化构造的方法
公开(公告)号：US20090172484A1
公开(公告)日：2009-07-02
申请号：US12330890
申请日：2008-12-09
申请人： Joerg Deutschle , Harald Gerst , Joerg Walter
发明人： Joerg Deutschle , Harald Gerst , Joerg Walter
IPC分类号： G01R31/28
CPC分类号： G06F11/3684 , G01R31/31813 , G01R31/318371
摘要： A serialization construct is implemented within an environment of a number of parallel data flow graphs. A quiesce node is appended to every active data flow graph. The quiesce node prevents a token from passing to a next data flow graph within a chain before an execution of the active data flow graph has been finished. A serial data flow graph is implemented to provided for a serial execution while no other data flow graph is active. A serialize node is appended to a starting point of a serial data flow graph. A serialize end node is appended to an endpoint of the serial data flow graph. The serialize node is activated to start a serial operation. The serialize end node is activated after the serial operation has been terminated.
摘要翻译：序列化构造在多个并行数据流图的环境中实现。静态节点附加到每个活动数据流图。停顿节点在活动数据流图的执行完成之前防止令牌传递到链中的下一个数据流图。实现串行数据流图，以提供串行执行，而没有其他数据流图是活动的。序列化节点附加到串行数据流图的起始点。序列化结束节点附加到串行数据流图的端点。串行化节点被激活以开始串行操作。序列化结束节点在串行操作终止后被激活。

7. 发明申请

US20070055911A1 A Method and System for Automatically Generating a Test-Case 审中-公开
标题翻译：一种用于自动生成测试用例的方法和系统
公开(公告)号：US20070055911A1
公开(公告)日：2007-03-08
申请号：US11460365
申请日：2006-07-27
申请人： Harald Boehm , Erwin Pfeffer , Joerg Walter
发明人： Harald Boehm , Erwin Pfeffer , Joerg Walter
IPC分类号： G06F11/00
CPC分类号： G06F11/261
摘要： The present invention relates to an automated method and system for transforming a hardware test-case within a system level into at least one unit test-case for a functional unit within a unit level, wherein the functional unit is a component of said hardware. The method comprises the steps of emulating a model of the hardware in the system level, applying the hardware test-case for the system level, recognizing and selecting an information relevant for the functional unit, transforming the information into commands for the functional unit and outputting the unit test-case for the functional unit.
摘要翻译：本发明涉及一种自动化方法和系统，用于将系统级内的硬件测试用例变换为单元级别内的功能单元的至少一个单元测试用例，其中所述功能单元是所述硬件的组件。该方法包括以下步骤：仿真系统级的硬件模型，应用系统级的硬件测试用例，识别和选择与功能单元相关的信息，将信息转换为功能单元的命令，并输出功能单元的单元测试用例。

8. 发明授权

US08056037B2 Method for validating logical function and timing behavior of a digital circuit decision 有权
标题翻译：用于验证数字电路决策的逻辑功能和时序特性的方法
公开(公告)号：US08056037B2
公开(公告)日：2011-11-08
申请号：US12233169
申请日：2008-09-18
申请人： Juergen Koehl , Walter Pietschmann , Juergen Saalmueller , Norbert Schumacher , Volker Urban , Joerg Walter
发明人： Juergen Koehl , Walter Pietschmann , Juergen Saalmueller , Norbert Schumacher , Volker Urban , Joerg Walter
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： The present invention relates to a method for validating the correct logical function and timing behavior of a digital circuit design within a cycle-based verification environment. The method comprises the steps of providing a VHDL description of the digital circuit design, performing a logic synthesis, wherein the VHDL description is turned into a design implementation in terms of logic gates, and creating a netlist including the elements of the digital circuit design and the connections between said elements. The method comprises the further steps of providing a transformation script with at least one transparent storage element, wherein said transparent storage element represents a path delay within the digital circuit design, creating a new netlist with the at least one transparent storage elements, running a verification, and checking if the new netlist is clean from a logical and timing point of view.
摘要翻译：本发明涉及一种在基于周期的验证环境中验证数字电路设计的正确逻辑功能和定时特性的方法。该方法包括以下步骤：提供数字电路设计的VHDL描述，执行逻辑合成，其中将VHDL描述转变为逻辑门的设计实现，以及创建包括数字电路设计的元件的网表，以及所述元件之间的连接。该方法包括以下步骤：向至少一个透明存储元件提供变换脚本，其中所述透明存储元件表示所述数字电路设计内的路径延迟，用所述至少一个透明存储元件创建新的网表，运行验证，并从逻辑和定时的角度检查新的网表是否干净。

9. 发明申请

US20090083684A1 Method for Violating the Logical Function and Timing Behavior of a Digital Circuit Decision 有权
标题翻译：违反数字电路决策的逻辑功能和定时行为的方法
公开(公告)号：US20090083684A1
公开(公告)日：2009-03-26
申请号：US12233169
申请日：2008-09-18
申请人： Juergen Koehl , Walter Pietschmann , Juergen Saalmueller , Norbert Schumacher , Volker Urban , Joerg Walter
发明人： Juergen Koehl , Walter Pietschmann , Juergen Saalmueller , Norbert Schumacher , Volker Urban , Joerg Walter
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： The present invention relates to a method for validating the correct logical function and timing behavior of a digital circuit design within a cycle-based verification environment. Said method comprises the steps of providing (10) a VHDL description of the digital circuit design, performing (12) a logic synthesis, wherein the VHDL description is turned into a design implementation in terms of logic gates, and creating (14) a netlist including the elements of the digital circuit design and the connections between said elements. Said method comprises the further steps of providing (28) a transformation script with at least one transparent storage element (40; 54), wherein said transparent storage element (40; 54) represents a path delay within the digital circuit design, creating (30) a new netlist with the at least one transparent storage elements (40; 54), running (20) a verification, and checking, if the new netlist is clean from a logical and timing point of view.
摘要翻译：本发明涉及一种在基于周期的验证环境中验证数字电路设计的正确逻辑功能和定时特性的方法。所述方法包括以下步骤：提供（10）数字电路设计的VHDL描述，执行（12）逻辑合成，其中VHDL描述在逻辑门方面变成设计实现，并且创建（14）网表包括数字电路设计的元件和所述元件之间的连接。所述方法包括以下步骤：提供具有至少一个透明存储元件（40; 54）的转换脚本（28），其中所述透明存储元件（40; 54）表示数字电路设计内的路径延迟，创建（30 ）具有至少一个透明存储元件（40; 54）的新网表，运行（20）验证，并且如果所述新网表从逻辑和定时观点清洁，则检查。

10. 发明申请

US20060195732A1 Method and system for executing test cases for a device under verification 审中-公开
标题翻译：为验证设备执行测试用例的方法和系统
公开(公告)号：US20060195732A1
公开(公告)日：2006-08-31
申请号：US11055839
申请日：2005-02-11
申请人： Joerg Deutschle , Harald Gerst , Joerg Walter
发明人： Joerg Deutschle , Harald Gerst , Joerg Walter
IPC分类号： G01R31/28
CPC分类号： G06F11/3688
摘要： The present invention relates to a method and system for executing test cases for a device by mapping sequences of instructions and/or operation into a data flow graph, which data flow graph includes a plurality of nodes (20) and a plurality of arcs (22) connecting the nodes (20). The method comprises a step of mapping at least one instruction or operation into the corresponding node (20) of the data flow graph, a further step of mapping sequential dependencies of said instruction and/or operation into the corresponding arcs (22) between the nodes (20), and another step of mapping parallel streams of the instructions and/or operations into the corresponding arcs (22), wherein each arc (22) originates from a single node (20) and ends in a single node (20). There are randomly generated as well as deterministic sequences of instructions and/or operations mapped into the data flow graph.
摘要翻译：本发明涉及通过将指令序列和/或操作映射到数据流图中来执行设备的测试用例的方法和系统，该数据流图包括多个节点（20）和多个弧（22 ）连接节点（20）。该方法包括将至少一个指令或操作映射到数据流图的对应节点（20）的步骤，将所述指令和/或操作的顺序依赖性映射到节点之间的相应弧（22）的另一步骤（20），以及将所述指令和/或操作的并行流映射到对应的弧（22）中的另一步骤，其中每个弧（22）源于单个节点（20）并且结束在单个节点（20）中。随机生成以及映射到数据流图中的指令和/或操作的确定性序列。

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