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    • 4. 发明申请
    • SEMICONDUCTOR INTEGRATED CIRCUIT
    • 半导体集成电路
    • US20090273870A1
    • 2009-11-05
    • US12501007
    • 2009-07-10
    • Hiroyasu IshizukaKazuo Tanaka
    • Hiroyasu IshizukaKazuo Tanaka
    • H02H9/00G11C13/04
    • H01L27/0251H01L2924/0002H01L2924/00
    • The present invention is provided to suppress occurrence of an erroneous operation in a protection circuit due to a relatively small power source fluctuation such as a power source noise. The protection circuit has a first resistor and a capacitor connected in series between a power source line and a ground line, an inverter whose input is connected between the first resistor and the capacitor, and a MOS transistor whose gate electrode receives an output of the inverter and whose drain electrode and source electrode are connected to the power source line and the ground line. When a high voltage fluctuation occurs in the power source line, a level change at a connection point between the first resistor and the capacitor is delayed according to a time constant. By the delay, the MOS transistor that receives an output of the inverter is temporarily turned on and discharges a high voltage to the ground line. Since an output of the inverter is pulled down to the ground line via a second resistor, even if an output of the inverter fluctuates undesirably, fluctuations in a gate input of the MOS transistor are suppressed.
    • 本发明是为了抑制电源噪声等电源波动较小的问题而抑制保护电路发生错误的动作。 保护电路具有串联连接在电源线和地线之间的第一电阻器和电容器,输入端连接在第一电阻器和电容器之间的反相器,以及栅极接收反相器的输出的MOS晶体管 并且其漏电极和源电极连接到电源线和接地线。 当电源线发生高电压波动时,第一电阻和电容器之间的连接点处的电平变化根据时间常数被延迟。 通过延迟,接收逆变器的输出的MOS晶体管暂时导通,并将高电压放电到地线。 由于逆变器的输出通过第二电阻被下拉到接地线,所以即使反相器的输出波动不期望,也抑制了MOS晶体管的栅极输入的波动。
    • 5. 发明申请
    • Semiconductor device
    • 半导体器件
    • US20060077601A1
    • 2006-04-13
    • US11222780
    • 2005-09-12
    • Hiroyuki IkedaKazuo TanakaHiroyasu IshizukaKoichiro Takakuwa
    • Hiroyuki IkedaKazuo TanakaHiroyasu IshizukaKoichiro Takakuwa
    • H02H9/00
    • H01L27/0251
    • The invention intends to provide a semiconductor device capable of preventing an electrostatic breakdown especially by the CDM, of the electrostatic breakdowns generated between plural power supply systems, with a few number of protection circuits. The semiconductor device includes a first circuit block that operates with a first power supply voltage and a first reference voltage, and a second circuit block that operates with a second power supply voltage and a second reference voltage. Further, the semiconductor device includes a first clamp circuit that clamps a potential between the first power supply voltage and the second reference voltage, a second clamp circuit that clamps a potential between the second power supply voltage and the first reference voltage, and a third clamp circuit that clamps a potential between the first reference voltage and the second reference voltage.
    • 本发明旨在提供一种半导体器件,其能够防止特别是CDM的静电击穿在多个电源系统之间产生的静电击穿与少数保护电路。 半导体器件包括以第一电源电压和第一参考电压工作的第一电路块,以及以第二电源电压和第二参考电压工作的第二电路块。 此外,半导体器件包括钳位第一电源电压和第二参考电压之间的电位的第一钳位电路,钳位第二电源电压和第一参考电压之间的电位的第二钳位电路和第三钳位电路 电路,钳位第一参考电压和第二参考电压之间的电位。
    • 6. 发明授权
    • Semiconductor integrated circuit
    • 半导体集成电路
    • US07593201B2
    • 2009-09-22
    • US11253635
    • 2005-10-20
    • Hiroyasu IshizukaKazuo Tanaka
    • Hiroyasu IshizukaKazuo Tanaka
    • H02H3/22
    • H01L27/0251H01L2924/0002H01L2924/00
    • A protection circuit with suppressed erroneous operation due to power source fluctuation has a first resistor and a capacitor connected in series between a power source line and a ground line, an inverter with an input connected between the first resistor and the capacitor, and a MOS transistor with a gate electrode that receives an output of the inverter and with a drain electrode and source electrode connected to the power source line and the ground line. When a high voltage fluctuation occurs in the power source line, a level change at a connection point between the first resistor and the capacitor is delayed according to a time constant. By the delay, the MOS transistor that receives an output of the inverter is temporarily turned on and discharges a high voltage to the ground line.
    • 由于电源波动导致的具有抑制的错误操作的保护电路具有串联连接在电源线和地线之间的第一电阻器和电容器,连接在第一电阻器和电容器之间的输入的反相器和MOS晶体管 其中栅电极接收反相器的输出,并且漏电极和源电极连接到电源线和接地线。 当电源线发生高电压波动时,第一电阻和电容器之间的连接点处的电平变化根据时间常数被延迟。 通过延迟,接收逆变器的输出的MOS晶体管暂时导通,并将高电压放电到地线。
    • 8. 发明授权
    • Braking force retaining unit
    • 制动力保持单元
    • US07125085B2
    • 2006-10-24
    • US11232027
    • 2005-09-21
    • Seiji OhsakiHiroyasu Ishizuka
    • Seiji OhsakiHiroyasu Ishizuka
    • B60T8/36
    • B60T7/122B60T2201/06
    • A braking force retaining unit has a cut-off valve and a control unit. The cut-off valve retains predetermined brake hydraulic pressure at the wheel cylinders until a predetermined releasing condition is established, even after the depression of a brake pedal is released when a vehicle is stopped. When the predetermined releasing condition is established, the retained brake hydraulic pressure is released, when the depression of the brake pedal is released, the control unit controls the cut-off valve so as to retain the brake hydraulic pressure while reducing the retained brake hydraulic pressure at a first reduction rate. When the predetermined releasing condition is established, the control unit controls the cut-off valve so as to allow the retained brake hydraulic pressure to be reduced at a second reduction rate which is faster than the first reduction rate.
    • 制动力保持单元具有截止阀和控制单元。 截止阀在车轮缸处保持预定的制动液压,直到建立了预定的释放条件,即使当车辆停止时制动踏板的下压被释放之后。 当预定的释放条件成立时,释放保持的制动液压,当释放制动踏板的下压时,控制单元控制截止阀,以便保持制动液压,同时降低制动液压保持力 以第一次削减率。 当预定的释放条件建立时,控制单元控制截止阀,以便以比第一减速率快的第二减速率来减小保持的制动液压。
    • 10. 发明授权
    • Semiconductor integrated circuit
    • 半导体集成电路
    • US07924539B2
    • 2011-04-12
    • US12501007
    • 2009-07-10
    • Hiroyasu IshizukaKazuo Tanaka
    • Hiroyasu IshizukaKazuo Tanaka
    • H02H3/22
    • H01L27/0251H01L2924/0002H01L2924/00
    • A protection circuit with suppressed erroneous operation due to power source fluctuation has a first resistor and a capacitor connected in series between a power source line and a ground line, an inverter with an input connected between the first resistor and the capacitor, and a MOS transistor with a gate electrode that receives an output of the inverter and with a drain electrode and source electrode connected to the power source line and the ground line. When high voltage fluctuation occurs in the power source line, a level change at a connection point between the first resistor and the capacitor is delayed according to a time constant. By the delay, the MOS transistor that receives an output of the inverter is temporarily turned on and discharges a high voltage to the ground line.
    • 由于电源波动导致的具有抑制的错误操作的保护电路具有串联连接在电源线和地线之间的第一电阻器和电容器,连接在第一电阻器和电容器之间的输入的反相器和MOS晶体管 其中栅电极接收反相器的输出,并且漏电极和源电极连接到电源线和接地线。 当电源线发生高电压波动时,第一电阻和电容器之间的连接点的电平变化根据时间常数被延迟。 通过延迟,接收逆变器的输出的MOS晶体管暂时导通,并将高电压放电到地线。