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1. 发明授权

US08483643B2 Harmonic rejection mixer 有权
标题翻译：谐波抑制混频器
公开(公告)号：US08483643B2
公开(公告)日：2013-07-09
申请号：US13143789
申请日：2010-01-29
申请人： Yoshito Shimizu , Noriaki Saito , Kiyomichi Araki , Takafumi Nasu
发明人： Yoshito Shimizu , Noriaki Saito , Kiyomichi Araki , Takafumi Nasu
IPC分类号： H04B1/10 , H04B1/26 , H02M11/00
CPC分类号： H03D7/165 , H03D2200/0086
摘要： Disclosed is a harmonic rejection mixer that makes it possible to suppress high-frequency response, while keeping the number of gm elements from increasing. In a harmonic rejection mixer that regulates the waveform of an output signal by mixing outputs of multiple mixers that are connected in parallel with the latter stage of multiple gm elements, some of the gm elements are shared by I phase and Q phase by using a control signal with a duty ratio of less than 50% to drive at least some of the mixers, and then using the period in which the I-phase mixers are inactive to activate the Q-phase mixers.
摘要翻译：公开了一种谐波抑制混频器，其能够抑制高频响应，同时保持gm元件的数量不增加。在通过混合与多个gm元件的后级并联连接的多个混频器的输出来调节输出信号的波形的谐波抑制混频器中，一些gm元件由I相和Q相共享，通过使用控制信号，占空比小于50％，以驱动至少一些混频器，然后使用I相混频器无效的周期来激活Q相混频器。

2. 发明申请

US20120049926A1 HARMONIC REJECTION MIXER 有权
标题翻译：谐波抑制混合器
公开(公告)号：US20120049926A1
公开(公告)日：2012-03-01
申请号：US13143789
申请日：2010-01-29
申请人： Yoshito Shimizu , Noriaki Saito , Kiyomichi Araki , Takafumi Nasu
发明人： Yoshito Shimizu , Noriaki Saito , Kiyomichi Araki , Takafumi Nasu
IPC分类号： G06G7/12
CPC分类号： H03D7/165 , H03D2200/0086
摘要： Disclosed is a harmonic rejection mixer that makes it possible to suppress high-frequency response, while keeping the number of gm elements from increasing. In a harmonic rejection mixer that regulates the waveform of an output signal by mixing outputs of multiple mixers that are connected in parallel with the latter stage of multiple gm elements, some of the gm elements are shared by I phase and Q phase by using a control signal with a duty ratio of less than 50% to drive at least some of the mixers, and then using the period in which the I-phase mixers are inactive to activate the Q-phase mixers.
摘要翻译：公开了一种谐波抑制混频器，其能够抑制高频响应，同时保持gm元件的数量不增加。在通过混合与多个gm元件的后级并联连接的多个混频器的输出来调节输出信号的波形的谐波抑制混频器中，一些gm元件由I相和Q相共享，通过使用控制信号，占空比小于50％，以驱动至少一些混频器，然后使用I相混频器无效的周期来激活Q相混频器。

3. 发明授权

US08145175B2 Sampling filter apparatus 有权
标题翻译：取样过滤装置
公开(公告)号：US08145175B2
公开(公告)日：2012-03-27
申请号：US12680326
申请日：2008-09-25
申请人： Kentaro Miyano , Yoshifumi Hosokawa , Katsuaki Abe , Noriaki Saito , Kiyomichi Araki
发明人： Kentaro Miyano , Yoshifumi Hosokawa , Katsuaki Abe , Noriaki Saito , Kiyomichi Araki
IPC分类号： H04B1/10
CPC分类号： H03H19/004 , H03H15/00
摘要： The sampling filter apparatus 100 includes the first sampling switch 130, the second sampling switch 131, the first integrator 1500 for integrating the charge input from the first sampling switch, the second integrator 1501 for integrating the charge input from the second sampling switch, a plurality of integrators connected to both of the first integrator and the second integrator via a charging switch, respectively, the control section 140, a plurality of charging switches, and a plurality of discharge switches. A charge input from the sampling switch 130, a charge accumulated in the capacitor 1500 and a charge accumulated in a capacitor 1510 are shared by the capacitor 1500, the capacitor 1510 and the capacitor 1530, and the charge accumulated in the capacitor 1530 is output.
摘要翻译：采样滤波器装置100包括第一采样开关130，第二采样开关131，用于对从第一采样开关输入的电荷进行积分的第一积分器1500，用于对从第二采样开关输入的电荷进行积分的第二积分器1501，分别通过充电开关连接到第一积分器和第二积分器两者的积分器，控制部分140，多个充电开关和多个放电开关。从采样开关130输入的电荷，积累在电容器1500中的电荷和电容器1510中累积的电荷被电容器1500，电容器1510和电容器1530共用，并且输出积累在电容器1530中的电荷。

4. 发明授权

US08229987B2 Discrete time direct sampling circuit and receiver 有权
标题翻译：离散时间直接采样电路和接收器
公开(公告)号：US08229987B2
公开(公告)日：2012-07-24
申请号：US12281668
申请日：2007-03-05
申请人： Yoshifumi Hosokawa , Katsuaki Abe , Noriaki Saito , Kiyomichi Araki , Yohei Morishita
发明人： Yoshifumi Hosokawa , Katsuaki Abe , Noriaki Saito , Kiyomichi Araki , Yohei Morishita
IPC分类号： G06F17/17 , G06G7/28 , H03M1/00
CPC分类号： H03H15/023 , H03D7/125 , H03D7/16 , H03J2200/10
摘要： A direct sampling circuit and a receiver which carry out discrete time analog processing with a high degree of design freedom and are provided with a filter property which is achievable to comply with the receipt of a broad band signal. A plurality of discrete time analog processing circuits (101) are connected in parallel with each other, a gm value and a capacitance of a capacitor in each circuit system are set independently based on a prescribed condition, and an output signal obtained from each circuit system is synthesized by means of a buffer capacitor (102), so that an equivalently high-dimensional IIR filter can be put into practice.
摘要翻译：一种直接采样电路和接收器，其以高度的设计自由度进行离散时间模拟处理，并具有能够符合宽带信号接收的滤波器特性。多个离散时间模拟处理电路（101）彼此并联连接，每个电路系统中的电容器的gm值和电容被独立地基于规定条件设置，并且从每个电路系统获得的输出信号通过缓冲电容器（102）合成，从而可以实现等效的高维IIR滤波器。

5. 发明申请

US20120230452A1 WIRELESS RECEIVING APPARATUS 有权
标题翻译：无线接收设备
公开(公告)号：US20120230452A1
公开(公告)日：2012-09-13
申请号：US13511276
申请日：2010-09-06
申请人： Kiyomichi Araki , Noriaki Saito , Tadashi Morita
发明人： Kiyomichi Araki , Noriaki Saito , Tadashi Morita
IPC分类号： H04L27/06
CPC分类号： H01Q21/28 , H01Q1/521 , H04B7/0413 , H04B7/0822
摘要： Disclosed is a wireless receiving apparatus, whereby inter-antenna interference can be reduced without inducing an increase of a mounting area due to an increase of the number of antennas, and the number of RFIC input terminals, circuit scale and power consumption can be reduced. In the wireless receiving apparatus (100), when a receiving antenna (110-1) and a down-converter (130) are connected with a multiplexer (120) therebetween, a capacity control unit (190-2) controls the capacity value of the capacity-variable parasitic element (180-2) connected to the receiving antenna (110-2) such that the communication capacity of the receiving antenna (110-1) is maximum. Furthermore, when the receiving antenna (110-2) and the down-converter (130) are connected with the multiplexer (120) therebetween, the capacity control unit (190-1) controls the capacity value of the capacity-variable parasitic element (180-1) connected to the receiving antenna (110-1) such that the communication capacity of the receiving antenna (110-2) is maximum.
摘要翻译：公开了一种无线接收装置，由于天线数量的增加，可以降低天线间干扰，而不会引起安装面积的增加，并且可以减少RFIC输入端子的数量，电路规模和功耗。在无线接收装置（100）中，当接收天线（110-1）和下变频器（130）与多路复用器（120）之间连接时，容量控制单元（190-2）控制容量值连接到接收天线（110-2）的容量可变寄生元件（180-2），使得接收天线（110-1）的通信容量最大。此外，当接收天线（110-2）和下变频器（130）与其之间的多路复用器（120）连接时，容量控制单元（190-1）控制容量可变寄生元件（ 180-1）连接到接收天线（110-1），使得接收天线（110-2）的通信容量最大。

6. 发明授权

US08693599B2 Wireless receiving apparatus 有权
标题翻译：无线接收装置
公开(公告)号：US08693599B2
公开(公告)日：2014-04-08
申请号：US13511276
申请日：2010-09-06
申请人： Kiyomichi Araki , Noriaki Saito , Tadashi Morita
发明人： Kiyomichi Araki , Noriaki Saito , Tadashi Morita
IPC分类号： H04L27/06
CPC分类号： H01Q21/28 , H01Q1/521 , H04B7/0413 , H04B7/0822
摘要： Disclosed is a wireless receiving apparatus, whereby inter-antenna interference can be reduced without inducing an increase of a mounting area due to an increase of the number of antennas, and the number of RFIC input terminals, circuit scale and power consumption can be reduced. In the wireless receiving apparatus (100), when a receiving antenna (110-1) and a down-converter (130) are connected with a multiplexer (120) therebetween, a capacity control unit (190-2) controls the capacity value of the capacity-variable parasitic element (180-2) connected to the receiving antenna (110-2) such that the communication capacity of the receiving antenna (110-1) is maximum. Furthermore, when the receiving antenna (110-2) and the down-converter (130) are connected with the multiplexer (120) therebetween, the capacity control unit (190-1) controls the capacity value of the capacity-variable parasitic element (180-1) connected to the receiving antenna (110-1) such that the communication capacity of the receiving antenna (110-2) is maximum.
摘要翻译：公开了一种无线接收装置，由于天线数量的增加，可以降低天线间干扰，而不会引起安装面积的增加，并且可以减少RFIC输入端子的数量，电路规模和功耗。在无线接收装置（100）中，当接收天线（110-1）和下变频器（130）与多路复用器（120）之间连接时，容量控制单元（190-2）控制容量值连接到接收天线（110-2）的容量可变寄生元件（180-2），使得接收天线（110-1）的通信容量最大。此外，当接收天线（110-2）和下变频器（130）与其之间的多路复用器（120）连接时，容量控制单元（190-1）控制容量可变寄生元件（ 180-1）连接到接收天线（110-1），使得接收天线（110-2）的通信容量最大。

7. 发明申请

US20100201424A1 SAMPLING FILTER APPARATUS 有权
标题翻译：采样过滤器
公开(公告)号：US20100201424A1
公开(公告)日：2010-08-12
申请号：US12680326
申请日：2008-09-25
申请人： Kentaro Miyano , Yoshifumi Hosokawa , Katsuaki Abe , Noriaki Saito , Kiyomichi Araki
发明人： Kentaro Miyano , Yoshifumi Hosokawa , Katsuaki Abe , Noriaki Saito , Kiyomichi Araki
IPC分类号： H03K5/08
CPC分类号： H03H19/004 , H03H15/00
摘要： The sampling filter apparatus 100 includes the first sampling switch 130, the second sampling switch 131, the first integrator 1500 for integrating the charge input from the first sampling switch, the second integrator 1501 for integrating the charge input from the second sampling switch, a plurality of integrators connected to both of the first integrator and the second integrator via a charging switch, respectively, the control section 140, a plurality of charging switches, and a plurality of discharge switches. A charge input from the sampling switch 130, a charge accumulated in the capacitor 1500 and a charge accumulated in a capacitor 1510 are shared by the capacitor 1500, the capacitor 1510 and the capacitor 1530, and the charge accumulated in the capacitor 1530 is output.
摘要翻译：采样滤波器装置100包括第一采样开关130，第二采样开关131，用于对从第一采样开关输入的电荷进行积分的第一积分器1500，用于对从第二采样开关输入的电荷进行积分的第二积分器1501，分别通过充电开关连接到第一积分器和第二积分器两者的积分器，控制部分140，多个充电开关和多个放电开关。从采样开关130输入的电荷，积累在电容器1500中的电荷和电容器1510中累积的电荷被电容器1500，电容器1510和电容器1530共用，并且输出积累在电容器1530中的电荷。

8. 发明申请

US20090009155A1 Discrete Time Direct Sampling Circuit and Receiver 有权
标题翻译：离散时间直接采样电路和接收机
公开(公告)号：US20090009155A1
公开(公告)日：2009-01-08
申请号：US12281668
申请日：2007-03-05
申请人： Yoshifumi Hosokawa , Katsuaki Abe , Noriaki Saito , Kiyomichi Araki , Yohei Morishita
发明人： Yoshifumi Hosokawa , Katsuaki Abe , Noriaki Saito , Kiyomichi Araki , Yohei Morishita
IPC分类号： G01R13/34 , H04B1/30
CPC分类号： H03H15/023 , H03D7/125 , H03D7/16 , H03J2200/10
摘要： A direct sampling circuit and a receiver which carry out discrete time analog processing with a high degree of design freedom and are provided with a filter property which is achievable to comply with the receipt of a broad band signal. A plurality of discrete time analog processing circuits (101) are connected in parallel with each other, a gm value and a capacitance of a capacitor in each circuit system are set independently based on a prescribed condition, and an output signal obtained from each circuit system is synthesized by means of a buffer capacitor (102), so that an equivalently high-dimensional IIR filter can be put into practice.
摘要翻译：一种直接采样电路和接收器，其以高度的设计自由度进行离散时间模拟处理，并具有能够符合宽带信号接收的滤波器特性。多个离散时间模拟处理电路（101）彼此并联连接，每个电路系统中的电容器的gm值和电容被独立地基于规定条件设置，并且从每个电路系统获得的输出信号通过缓冲电容器（102）合成，从而可以实现等效的高维IIR滤波器。

9. 发明授权

US08081943B2 Reception apparatus and reception method 有权
标题翻译：接收方式和接收方式
公开(公告)号：US08081943B2
公开(公告)日：2011-12-20
申请号：US12276047
申请日：2008-11-21
申请人： Yoshito Shimizu , Takeaki Watanabe , Noriaki Saito
发明人： Yoshito Shimizu , Takeaki Watanabe , Noriaki Saito
IPC分类号： H04B1/06 , H04B7/00
CPC分类号： H04B1/30
摘要： A receiving apparatus includes an amplification section that amplifies a received signal and a frequency conversion section that converts a frequency of the received signal, from a radio frequency to a baseband, the baseband having a lower frequency than the radio frequency. A gain control section amplifies, by a predetermined gain, the signal that has been subjected to the frequency conversion to the baseband. A voltage calibration section performs calibration on an offset voltage generated in the signal subjected to frequency conversion to the baseband. A time constant control section sets a first time constant during a reception operation and sets a second time constant, which is reduced with respect to the first time constant, during the calibration. A filter section passes a received signal of a predetermined band, with the first time constant or the second time constant, an operation control section stops operation of the amplification section during the calibration, controls the amplification section to operate during the reception operation, and controls the operation of the amplification section so as to reduce a residual offset voltage caused by switching the operation of the amplification section.
摘要翻译：接收装置包括放大接收信号的放大部分和频率转换部分，该频率转换部分将接收信号的频率从射频转换成基带，频率低于射频。增益控制部分将经过频率转换的信号以预定的增益放大到基带。电压校准部对经过频率转换为基带的信号中产生的偏移电压进行校准。时间常数控制部分在接收操作期间设置第一时间常数，并且在校准期间设置相对于第一时间常数减小的第二时间常数。滤波器部分以第一时间常数或第二时间常数通过预定频带的接收信号，操作控制部分在校准期间停止放大部分的操作，控制放大部分在接收操作期间操作，并且控制放大部分的操作，以便减少由于放大部分的操作而导致的残留偏移电压。

10. 发明申请

US20110176640A1 SAMPLING CIRCUIT AND RECEIVER UTILIZING THE SAME 有权
标题翻译：采样电路和接收器使用它
公开(公告)号：US20110176640A1
公开(公告)日：2011-07-21
申请号：US13121244
申请日：2009-12-04
申请人： Yohei Morishita , Noriaki Saito , Yoshito Shimizu
发明人： Yohei Morishita , Noriaki Saito , Yoshito Shimizu
IPC分类号： H04L25/06 , G11C27/02
CPC分类号： H03H19/004 , H03H15/00 , H04B1/28
摘要： Disclosed are a sampling circuit and a receiver that have a high level of filter design flexibility and excellent image rejection characteristics. Signals with phases that differ by 90° are sampled using an IQ generating circuit (101) and are weighted by each of multiple parallel-connected discrete-time circuits (102-1-102-n), and the result of addition by an output adding circuit (103) is ultimately output. Alternatively, a configuration in which the multiple parallel-connected discrete-time circuits (102-1-102-n) and the output adding circuit (103) are cascade-connected is adopted, so that frequency characteristics having an attenuation pole to one side can be achieved and excellent image rejection characteristics can be obtained.
摘要翻译：公开了具有高水平的滤波器设计灵活性和优异的图像抑制特性的采样电路和接收器。使用IQ生成电路（101）对具有相差90°的相位的信号进行采样，并由多个并联连接的离散时间电路（102-1-102-n）中的每一个进行加权，并且通过输出最终输出加法电路（103）。或者，采用其中并联连接的多个离散时间电路（102-1-102-n）和输出加法电路（103）串联的配置，使得具有到一侧具有衰减极点的频率特性并且可以获得优异的图像抑制特性。

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