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1. 发明申请

US20120230452A1 WIRELESS RECEIVING APPARATUS 有权
标题翻译：无线接收设备
公开(公告)号：US20120230452A1
公开(公告)日：2012-09-13
申请号：US13511276
申请日：2010-09-06
申请人： Kiyomichi Araki , Noriaki Saito , Tadashi Morita
发明人： Kiyomichi Araki , Noriaki Saito , Tadashi Morita
IPC分类号： H04L27/06
CPC分类号： H01Q21/28 , H01Q1/521 , H04B7/0413 , H04B7/0822
摘要： Disclosed is a wireless receiving apparatus, whereby inter-antenna interference can be reduced without inducing an increase of a mounting area due to an increase of the number of antennas, and the number of RFIC input terminals, circuit scale and power consumption can be reduced. In the wireless receiving apparatus (100), when a receiving antenna (110-1) and a down-converter (130) are connected with a multiplexer (120) therebetween, a capacity control unit (190-2) controls the capacity value of the capacity-variable parasitic element (180-2) connected to the receiving antenna (110-2) such that the communication capacity of the receiving antenna (110-1) is maximum. Furthermore, when the receiving antenna (110-2) and the down-converter (130) are connected with the multiplexer (120) therebetween, the capacity control unit (190-1) controls the capacity value of the capacity-variable parasitic element (180-1) connected to the receiving antenna (110-1) such that the communication capacity of the receiving antenna (110-2) is maximum.
摘要翻译：公开了一种无线接收装置，由于天线数量的增加，可以降低天线间干扰，而不会引起安装面积的增加，并且可以减少RFIC输入端子的数量，电路规模和功耗。在无线接收装置（100）中，当接收天线（110-1）和下变频器（130）与多路复用器（120）之间连接时，容量控制单元（190-2）控制容量值连接到接收天线（110-2）的容量可变寄生元件（180-2），使得接收天线（110-1）的通信容量最大。此外，当接收天线（110-2）和下变频器（130）与其之间的多路复用器（120）连接时，容量控制单元（190-1）控制容量可变寄生元件（ 180-1）连接到接收天线（110-1），使得接收天线（110-2）的通信容量最大。

2. 发明授权

US08693599B2 Wireless receiving apparatus 有权
标题翻译：无线接收装置
公开(公告)号：US08693599B2
公开(公告)日：2014-04-08
申请号：US13511276
申请日：2010-09-06
申请人： Kiyomichi Araki , Noriaki Saito , Tadashi Morita
发明人： Kiyomichi Araki , Noriaki Saito , Tadashi Morita
IPC分类号： H04L27/06
CPC分类号： H01Q21/28 , H01Q1/521 , H04B7/0413 , H04B7/0822
摘要： Disclosed is a wireless receiving apparatus, whereby inter-antenna interference can be reduced without inducing an increase of a mounting area due to an increase of the number of antennas, and the number of RFIC input terminals, circuit scale and power consumption can be reduced. In the wireless receiving apparatus (100), when a receiving antenna (110-1) and a down-converter (130) are connected with a multiplexer (120) therebetween, a capacity control unit (190-2) controls the capacity value of the capacity-variable parasitic element (180-2) connected to the receiving antenna (110-2) such that the communication capacity of the receiving antenna (110-1) is maximum. Furthermore, when the receiving antenna (110-2) and the down-converter (130) are connected with the multiplexer (120) therebetween, the capacity control unit (190-1) controls the capacity value of the capacity-variable parasitic element (180-1) connected to the receiving antenna (110-1) such that the communication capacity of the receiving antenna (110-2) is maximum.
摘要翻译：公开了一种无线接收装置，由于天线数量的增加，可以降低天线间干扰，而不会引起安装面积的增加，并且可以减少RFIC输入端子的数量，电路规模和功耗。在无线接收装置（100）中，当接收天线（110-1）和下变频器（130）与多路复用器（120）之间连接时，容量控制单元（190-2）控制容量值连接到接收天线（110-2）的容量可变寄生元件（180-2），使得接收天线（110-1）的通信容量最大。此外，当接收天线（110-2）和下变频器（130）与其之间的多路复用器（120）连接时，容量控制单元（190-1）控制容量可变寄生元件（ 180-1）连接到接收天线（110-1），使得接收天线（110-2）的通信容量最大。

3. 发明授权

US08229987B2 Discrete time direct sampling circuit and receiver 有权
标题翻译：离散时间直接采样电路和接收器
公开(公告)号：US08229987B2
公开(公告)日：2012-07-24
申请号：US12281668
申请日：2007-03-05
申请人： Yoshifumi Hosokawa , Katsuaki Abe , Noriaki Saito , Kiyomichi Araki , Yohei Morishita
发明人： Yoshifumi Hosokawa , Katsuaki Abe , Noriaki Saito , Kiyomichi Araki , Yohei Morishita
IPC分类号： G06F17/17 , G06G7/28 , H03M1/00
CPC分类号： H03H15/023 , H03D7/125 , H03D7/16 , H03J2200/10
摘要： A direct sampling circuit and a receiver which carry out discrete time analog processing with a high degree of design freedom and are provided with a filter property which is achievable to comply with the receipt of a broad band signal. A plurality of discrete time analog processing circuits (101) are connected in parallel with each other, a gm value and a capacitance of a capacitor in each circuit system are set independently based on a prescribed condition, and an output signal obtained from each circuit system is synthesized by means of a buffer capacitor (102), so that an equivalently high-dimensional IIR filter can be put into practice.
摘要翻译：一种直接采样电路和接收器，其以高度的设计自由度进行离散时间模拟处理，并具有能够符合宽带信号接收的滤波器特性。多个离散时间模拟处理电路（101）彼此并联连接，每个电路系统中的电容器的gm值和电容被独立地基于规定条件设置，并且从每个电路系统获得的输出信号通过缓冲电容器（102）合成，从而可以实现等效的高维IIR滤波器。

4. 发明授权

US08145175B2 Sampling filter apparatus 有权
标题翻译：取样过滤装置
公开(公告)号：US08145175B2
公开(公告)日：2012-03-27
申请号：US12680326
申请日：2008-09-25
申请人： Kentaro Miyano , Yoshifumi Hosokawa , Katsuaki Abe , Noriaki Saito , Kiyomichi Araki
发明人： Kentaro Miyano , Yoshifumi Hosokawa , Katsuaki Abe , Noriaki Saito , Kiyomichi Araki
IPC分类号： H04B1/10
CPC分类号： H03H19/004 , H03H15/00
摘要： The sampling filter apparatus 100 includes the first sampling switch 130, the second sampling switch 131, the first integrator 1500 for integrating the charge input from the first sampling switch, the second integrator 1501 for integrating the charge input from the second sampling switch, a plurality of integrators connected to both of the first integrator and the second integrator via a charging switch, respectively, the control section 140, a plurality of charging switches, and a plurality of discharge switches. A charge input from the sampling switch 130, a charge accumulated in the capacitor 1500 and a charge accumulated in a capacitor 1510 are shared by the capacitor 1500, the capacitor 1510 and the capacitor 1530, and the charge accumulated in the capacitor 1530 is output.
摘要翻译：采样滤波器装置100包括第一采样开关130，第二采样开关131，用于对从第一采样开关输入的电荷进行积分的第一积分器1500，用于对从第二采样开关输入的电荷进行积分的第二积分器1501，分别通过充电开关连接到第一积分器和第二积分器两者的积分器，控制部分140，多个充电开关和多个放电开关。从采样开关130输入的电荷，积累在电容器1500中的电荷和电容器1510中累积的电荷被电容器1500，电容器1510和电容器1530共用，并且输出积累在电容器1530中的电荷。

5. 发明申请

US20120049926A1 HARMONIC REJECTION MIXER 有权
标题翻译：谐波抑制混合器
公开(公告)号：US20120049926A1
公开(公告)日：2012-03-01
申请号：US13143789
申请日：2010-01-29
申请人： Yoshito Shimizu , Noriaki Saito , Kiyomichi Araki , Takafumi Nasu
发明人： Yoshito Shimizu , Noriaki Saito , Kiyomichi Araki , Takafumi Nasu
IPC分类号： G06G7/12
CPC分类号： H03D7/165 , H03D2200/0086
摘要： Disclosed is a harmonic rejection mixer that makes it possible to suppress high-frequency response, while keeping the number of gm elements from increasing. In a harmonic rejection mixer that regulates the waveform of an output signal by mixing outputs of multiple mixers that are connected in parallel with the latter stage of multiple gm elements, some of the gm elements are shared by I phase and Q phase by using a control signal with a duty ratio of less than 50% to drive at least some of the mixers, and then using the period in which the I-phase mixers are inactive to activate the Q-phase mixers.
摘要翻译：公开了一种谐波抑制混频器，其能够抑制高频响应，同时保持gm元件的数量不增加。在通过混合与多个gm元件的后级并联连接的多个混频器的输出来调节输出信号的波形的谐波抑制混频器中，一些gm元件由I相和Q相共享，通过使用控制信号，占空比小于50％，以驱动至少一些混频器，然后使用I相混频器无效的周期来激活Q相混频器。

6. 发明授权

US08483643B2 Harmonic rejection mixer 有权
标题翻译：谐波抑制混频器
公开(公告)号：US08483643B2
公开(公告)日：2013-07-09
申请号：US13143789
申请日：2010-01-29
申请人： Yoshito Shimizu , Noriaki Saito , Kiyomichi Araki , Takafumi Nasu
发明人： Yoshito Shimizu , Noriaki Saito , Kiyomichi Araki , Takafumi Nasu
IPC分类号： H04B1/10 , H04B1/26 , H02M11/00
CPC分类号： H03D7/165 , H03D2200/0086
摘要： Disclosed is a harmonic rejection mixer that makes it possible to suppress high-frequency response, while keeping the number of gm elements from increasing. In a harmonic rejection mixer that regulates the waveform of an output signal by mixing outputs of multiple mixers that are connected in parallel with the latter stage of multiple gm elements, some of the gm elements are shared by I phase and Q phase by using a control signal with a duty ratio of less than 50% to drive at least some of the mixers, and then using the period in which the I-phase mixers are inactive to activate the Q-phase mixers.
摘要翻译：公开了一种谐波抑制混频器，其能够抑制高频响应，同时保持gm元件的数量不增加。在通过混合与多个gm元件的后级并联连接的多个混频器的输出来调节输出信号的波形的谐波抑制混频器中，一些gm元件由I相和Q相共享，通过使用控制信号，占空比小于50％，以驱动至少一些混频器，然后使用I相混频器无效的周期来激活Q相混频器。

7. 发明申请

US20100201424A1 SAMPLING FILTER APPARATUS 有权
标题翻译：采样过滤器
公开(公告)号：US20100201424A1
公开(公告)日：2010-08-12
申请号：US12680326
申请日：2008-09-25
申请人： Kentaro Miyano , Yoshifumi Hosokawa , Katsuaki Abe , Noriaki Saito , Kiyomichi Araki
发明人： Kentaro Miyano , Yoshifumi Hosokawa , Katsuaki Abe , Noriaki Saito , Kiyomichi Araki
IPC分类号： H03K5/08
CPC分类号： H03H19/004 , H03H15/00
摘要： The sampling filter apparatus 100 includes the first sampling switch 130, the second sampling switch 131, the first integrator 1500 for integrating the charge input from the first sampling switch, the second integrator 1501 for integrating the charge input from the second sampling switch, a plurality of integrators connected to both of the first integrator and the second integrator via a charging switch, respectively, the control section 140, a plurality of charging switches, and a plurality of discharge switches. A charge input from the sampling switch 130, a charge accumulated in the capacitor 1500 and a charge accumulated in a capacitor 1510 are shared by the capacitor 1500, the capacitor 1510 and the capacitor 1530, and the charge accumulated in the capacitor 1530 is output.
摘要翻译：采样滤波器装置100包括第一采样开关130，第二采样开关131，用于对从第一采样开关输入的电荷进行积分的第一积分器1500，用于对从第二采样开关输入的电荷进行积分的第二积分器1501，分别通过充电开关连接到第一积分器和第二积分器两者的积分器，控制部分140，多个充电开关和多个放电开关。从采样开关130输入的电荷，积累在电容器1500中的电荷和电容器1510中累积的电荷被电容器1500，电容器1510和电容器1530共用，并且输出积累在电容器1530中的电荷。

8. 发明申请

US20090009155A1 Discrete Time Direct Sampling Circuit and Receiver 有权
标题翻译：离散时间直接采样电路和接收机
公开(公告)号：US20090009155A1
公开(公告)日：2009-01-08
申请号：US12281668
申请日：2007-03-05
申请人： Yoshifumi Hosokawa , Katsuaki Abe , Noriaki Saito , Kiyomichi Araki , Yohei Morishita
发明人： Yoshifumi Hosokawa , Katsuaki Abe , Noriaki Saito , Kiyomichi Araki , Yohei Morishita
IPC分类号： G01R13/34 , H04B1/30
CPC分类号： H03H15/023 , H03D7/125 , H03D7/16 , H03J2200/10
摘要： A direct sampling circuit and a receiver which carry out discrete time analog processing with a high degree of design freedom and are provided with a filter property which is achievable to comply with the receipt of a broad band signal. A plurality of discrete time analog processing circuits (101) are connected in parallel with each other, a gm value and a capacitance of a capacitor in each circuit system are set independently based on a prescribed condition, and an output signal obtained from each circuit system is synthesized by means of a buffer capacitor (102), so that an equivalently high-dimensional IIR filter can be put into practice.
摘要翻译：一种直接采样电路和接收器，其以高度的设计自由度进行离散时间模拟处理，并具有能够符合宽带信号接收的滤波器特性。多个离散时间模拟处理电路（101）彼此并联连接，每个电路系统中的电容器的gm值和电容被独立地基于规定条件设置，并且从每个电路系统获得的输出信号通过缓冲电容器（102）合成，从而可以实现等效的高维IIR滤波器。

9. 发明申请

US20100308816A1 PHYSICAL QUANTITY DETECTION DEVICE 审中-公开
标题翻译：物理量检测装置
公开(公告)号：US20100308816A1
公开(公告)日：2010-12-09
申请号：US12740209
申请日：2008-10-29
申请人： Tomoaki Ueda , Masanori Abe , Takashi Nakagawa , Masaru Tada , Tetsuya Mizumoto , Hiroshi Handa , Adarsh Sandhu , Kiyomichi Araki
发明人： Tomoaki Ueda , Masanori Abe , Takashi Nakagawa , Masaru Tada , Tetsuya Mizumoto , Hiroshi Handa , Adarsh Sandhu , Kiyomichi Araki
IPC分类号： G01R33/07
CPC分类号： G01R33/07
摘要： Provided is a highly sensitive sensor system that can improve the S/N ratio by use of an electronic circuit without complicating the sensor body or degrading temporal resolution. A broad spectrum sensor element outputs an electric signal corresponding to a detected physical quantity, the sensor driven by multiplying a carrier signal by m-sequence code. The spread spectrum signal, after phase adjustment, is used to demodulate the sensor output signal, which corresponds to the broad spread spectrum of the physical quantity. The electrical noise generated in the sensor is a broad spread spectrum and is suppressed by low-pass filtering so as to improve the S/N ratio.
摘要翻译：提供了一种高灵敏度的传感器系统，其可以通过使用电子电路来提高S / N比，而不会使传感器体复杂化或降低时间分辨率。广谱传感器元件输出对应于检测到的物理量的电信号，该传感器通过乘以载波信号由m序列码驱动。相位调整后的扩频信号用于解调对应于物理量的广泛扩频的传感器输出信号。在传感器中产生的电噪声是广泛的扩频，并通过低通滤波来抑制，以提高S / N比。

10. 发明授权

US08766834B2 Discrete time analog circuit and receiver using same 有权
标题翻译：离散时间模拟电路和接收机使用相同
公开(公告)号：US08766834B2
公开(公告)日：2014-07-01
申请号：US13808481
申请日：2011-07-27
申请人： Hiroka Shiozaki , Kiyomichi Araki , Yohei Morishita , Masaki Kanemaru
发明人： Hiroka Shiozaki , Kiyomichi Araki , Yohei Morishita , Masaki Kanemaru
IPC分类号： H03M1/00
CPC分类号： H03M1/18 , H03H15/00 , H03H19/004 , H03M1/50
摘要： The discrete time analog circuit (100) is provided with: a rotate capacitor circuit (150); an amplifier (141) that is connected to the input line or the output line of the rotate capacitor (150), and amplifies the input potential or input charge; a coefficient circuit (140) that is positioned in series with the amplifier (141), and has two history capacitors (143-1, 143-2) positioned parallel to each other; a first active capacitor among the two history capacitors (143-1, 143-2) that is connected to and charges the amplifier (141); and a clock generation circuit (110) that is connected to the input line or the output line without the involvement of the amplifier (141), and that sequentially changes the pairing of the rotate capacitor circuit (150) a second active capacitor, which shares a charge with the rotate capacitor circuit (150).
摘要翻译：离散时间模拟电路（100）具有：旋转电容电路（150）; 连接到所述旋转电容器（150）的输入线或输出线的放大器（141），并放大所述输入电位或输入电荷; 与放大器（141）串联定位的系数电路（140），并且具有彼此平行定位的两个历史电容器（143-1,143-2）; 在两个历史电容器（143-1,143-2）之间连接并对放大器（141）充电的第一有源电容器; 以及时钟发生电路（110），其连接到所述输入线或所述输出线而不涉及所述放大器（141），并且顺序地改变所述旋转电容器电路（150）的配对，所述第二有源电容器与旋转电容电路（150）的电荷。

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