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1. 发明授权

US5349218A Semiconductor integrated circuit device including memory cells having a structure effective in suppression of leak current 失效
标题翻译：包括具有抑制漏电流的结构的存储单元的半导体集成电路器件
公开(公告)号：US5349218A
公开(公告)日：1994-09-20
申请号：US875653
申请日：1992-04-29
申请人： Yoshitaka Tadaki , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Toru Kaga , Jun Murata , Osaomi Enomoto
发明人： Yoshitaka Tadaki , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Toru Kaga , Jun Murata , Osaomi Enomoto
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10829
摘要： A semiconductor integrated circuit device has a semiconductor memory cell array including word lines, data lines and a plurality of memory cells provided at cross points of the word and data lines. Each memory cell has a cell selection transistor and an information storage capacitor connected in series. The cell selection transistor in one cell includes first and second doped regions formed in a main surface of a semiconductor substrate, a first insulating film formed on the main surface between the first and second doped regions and a control electrode layer formed on the first insulating film between the first and second doped regions. The first doped region is connected with a data line, while the control electrode is connected with a word line. The information storage capacitor includes a second insulating film formed on the wall of one trench formed on the main surface of the substrate, an electrode layer formed on the second insulating film and serving as a first electrode of the capacitor, a dielectric film formed on the electrode layer and a conducting material provided to fill a space defined by the dielectric film in the trench and serving as a second electrode of the capacitor. The second doped region of the transistor terminates at the wall of the trench. A conducting layer is provided to extend both on the second doped region and the conducting material in the cell to electrically interconnect them for the series connection.
摘要翻译：半导体集成电路器件具有半导体存储单元阵列，该半导体存储单元阵列包括在字和数据线的交叉点处设置的字线，数据线和多个存储单元。每个存储单元具有串联连接的单元选择晶体管和信息存储电容器。一个单元中的单元选择晶体管包括形成在半导体衬底的主表面中的第一和第二掺杂区，形成在第一和第二掺杂区之间的主表面上的第一绝缘膜和形成在第一绝缘膜上的控制电极层在第一和第二掺杂区域之间。第一掺杂区域与数据线连接，而控制电极与字线连接。信息存储电容器包括形成在形成在基板的主表面上的一个沟槽的壁上的第二绝缘膜，形成在第二绝缘膜上并用作电容器的第一电极的电极层，形成在第二绝缘膜上的电介质膜电极层和设置成填充由沟槽中的电介质膜限定的空间并用作电容器的第二电极的导电材料。晶体管的第二掺杂区域终止于沟槽的壁。提供导电层以在第二掺杂区域和电池中的导电材料两者上延伸以将它们互连用于串联连接。

2. 发明授权

US4708768A Semiconductor device fabrication process 失效
标题翻译：半导体器件制造工艺
公开(公告)号：US4708768A
公开(公告)日：1987-11-24
申请号：US24238
申请日：1987-03-10
申请人： Osaomi Enomoto , Katsuo Komatsuzaki
发明人： Osaomi Enomoto , Katsuo Komatsuzaki
IPC分类号： H01L21/76 , C23C16/04 , H01L21/316 , H01L21/32 , H01L21/762 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/76216 , C23C16/042 , H01L21/32
摘要： A semiconductor device fabrication process comprising the following sequential steps:Sequential formation of an oxide layer and first layer of masking material resistant both to oxidation (particularly preventing the action of oxidants, such as water vapors and O.sub.2) and heat, on a principal plane of semiconductor substrate;Patternwise removal of these two layers in overlapping positions to form wells with the above semiconductor substrate exposed at bottom;Selective removal of the above oxide layer only around the wells thus formed to leave recesses;Deposition of the second layer of masking material resistant both oxidation and heat on the exposed surfaces of semiconductor substrate at the bottom of the above wells and in the recesses that are left after the above selective removal of oxide layer;Removal of the above second layer of masking material from the bottom of wells with the masking material left in the above recesses; andSelective oxidation of exposed surfaces of above semiconductor substrate under masking with the first and second layers of masking material that remain.
摘要翻译：一种半导体器件制造方法，包括以下顺序步骤：顺序形成氧化物层和掩蔽材料的第一层，其能够抵抗氧化（特别是防止氧化剂如水蒸汽和氧气的作用）和热，在主平面上半导体衬底; 在重叠位置上以图形方式去除这两层以形成具有暴露在底部的上述半导体衬底的阱; 选择性地去除上述氧化物层，仅在由此形成的孔留下凹槽; 在上述孔的底部和在上述选择性去除氧化物层之后留下的凹槽中，在半导体衬底的暴露表面上沉积第二层掩模材料，以抵抗氧化和加热; 从孔的底部去除上述第二层掩模材料，其中掩蔽材料留在上述凹槽中; 以及在保留的第一和第二掩蔽材料层掩蔽下的上述半导体衬底的暴露表面的选择性氧化。

3. 发明授权

US5629225A Method of making a cylindrical electrode 失效
标题翻译：制作圆柱形电极的方法
公开(公告)号：US5629225A
公开(公告)日：1997-05-13
申请号：US478635
申请日：1995-06-07
申请人： Takashi Iwakiri , Kiyomi Hirose , Hiroto Shinozuka , Osaomi Enomoto , Yasuhiro Okumoto
发明人： Takashi Iwakiri , Kiyomi Hirose , Hiroto Shinozuka , Osaomi Enomoto , Yasuhiro Okumoto
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/60 , H01L28/91
摘要： A manufacturing method for a dynamic RAM containing a screen-type structure cylindrical stack cell capacitor. An SiO.sub.2 layer 22 is formed on a polysilicon layer 11 (or a semiconductor substrate 1) to serve as a preform or spacer. A nitride layer 31 is stacked on this SiO.sub.2 layer, and nitride layer 31 and SiO.sub.2 layer 22 are worked into virtually the same pattern. Then the outside surface of SiO.sub.2 layer 22 is etched using nitride layer 31 as a mask, causing the nitride layer 31 to form a lateral projection structure 31A in the region removed by the etching. A polysilicon layer 23 is adhered to the top of silicon layer 11, which serves as a capacitor lower electrode, from the top of nitride layer 31 and SiO.sub.2 layer 22, including this projected portion. Polysilicon layer 23 is etched to leave a portion of polysilicon layer 23 on the outside surface of SiO.sub.2 layer 22 directly beneath the projecting portion 31A of nitride layer 31.
摘要翻译：一种用于包含屏幕型结构的圆柱形堆叠单元电容器的动态RAM的制造方法。 SiO 2层22形成在多晶硅层11（或半导体衬底1）上，用作预成型件或间隔件。氮化物层31层叠在该SiO 2层上，氮化物层31和SiO 2层22被加工成几乎相同的图案。然后，使用氮化物层31作为掩模来蚀刻SiO 2层22的外表面，使得氮化物层31在通过蚀刻去除的区域中形成横向突起结构31A。多晶硅层23从包括该突出部分的氮化物层31和SiO 2层22的顶部附着到用作电容器下电极的硅层11的顶部。蚀刻多晶硅层23，以在氮化物层31的突出部分31A正下方的SiO 2层22的外表面上留下多晶硅层23的一部分。

4. 发明授权

US5514628A Two-step sinter method utilized in conjunction with memory cell replacement by redundancies 失效
标题翻译：结合存储器单元更换冗余的两步烧结方法
公开(公告)号：US5514628A
公开(公告)日：1996-05-07
申请号：US451644
申请日：1995-05-26
申请人： Osaomi Enomoto , Yoichi Miyai , Yoshihiro Ogata , Yoshinobu Yoneoka
发明人： Osaomi Enomoto , Yoichi Miyai , Yoshihiro Ogata , Yoshinobu Yoneoka
IPC分类号： H01L21/324 , H01L27/118
CPC分类号： H01L21/324 , H01L27/118
摘要： A process is disclosed herein for increasing yield in a semiconductor circuity having redundant circuitry for replacing defective normal circuitry in the semiconductor integrated circuit. In the first step, an insufficient sinter operation (50) is carried out in a hydrogen atmosphere at a temperature of less than 350.degree. C. At this temperature, no significant change will be seen in the interface trap density. Thereafter, the integrated circuit is tested (54,56) and the defective normal circuitry then is replaced (58) with the redundant circuitry. The integrated circuit is then subjected to a sufficient sinter operation (64) which is an operation wherein the substrate is disposed at a temperature between 350.degree. C.-500.degree. C. for more than 30 minutes. This sufficient sinter operation is performed in a hydrogen atmosphere, allowing dangling bonds at the interface to be terminated with hydrogen. Preferable, the optimal temperature for the sufficient sinter is approximately 400.degree. C. The integrated circuit is then subjected to a reliability and burn-in procedure.
摘要翻译：本文公开了一种用于提高具有用于替换半导体集成电路中的有缺陷的正常电路的冗余电路的半导体电路中的产量的方法。在第一步骤中，在低于350℃的氢气气氛中进行不充分的烧结操作（50）。在该温度下，界面陷阱密度将不会发生明显的变化。此后，测试集成电路（54,56），然后用冗余电路替换有缺陷的正常电路（58）。然后对集成电路进行充分的烧结操作（64），其是将衬底置于350℃-5500℃的温度下超过30分钟的操作。这种充分的烧结操作在氢气氛中进行，允许界面处的悬挂键用氢终止。优选的是，足够的烧结体的最佳温度为约400℃。然后对集成电路进行可靠性和老化过程。

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