专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08563961B2 Semiconductor storage device and method for manufacturing same 有权
标题翻译：半导体存储装置及其制造方法
公开(公告)号：US08563961B2
公开(公告)日：2013-10-22
申请号：US13515435
申请日：2010-12-13
申请人： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikastsu Takaura
发明人： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikastsu Takaura
IPC分类号： H01L47/00
CPC分类号： H01L45/1666 , H01L27/224 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1206 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.
摘要翻译：公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。半导体存储装置具有：基板; 设置在基板上方的第一字线（2）第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N> = 1）个第一栅极间绝缘层（11-15）和N个第一半导体层（21p-24p）在基板的高度方向交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧表面上的第一可变电阻材料层（7）。第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。此外，使用多晶硅二极管（PD）作为选择元件。

2. 发明申请

US20120248399A1 SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120248399A1
公开(公告)日：2012-10-04
申请号：US13515435
申请日：2010-12-13
申请人： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikastsu Takaura
发明人： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikastsu Takaura
IPC分类号： H01L27/24
CPC分类号： H01L45/1666 , H01L27/224 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1206 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.
摘要翻译：公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。半导体存储装置具有：基板; 设置在基板上方的第一字线（2）第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N≥1）个第一栅极间绝缘层（11-15）和N个第一半导体层（21p-24p）在基板的高度方向上交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧表面上的第一可变电阻材料层（7）。第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。此外，使用多晶硅二极管（PD）作为选择元件。

3. 发明授权

US08169819B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08169819B2
公开(公告)日：2012-05-01
申请号：US12688886
申请日：2010-01-17
申请人： Akio Shima , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
发明人： Akio Shima , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
IPC分类号： G11C11/00 , H01L29/80
CPC分类号： H01L27/2481 , G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2454 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.
摘要翻译：提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以配置三维存储器单元格阵列。存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

4. 发明授权

US08427865B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08427865B2
公开(公告)日：2013-04-23
申请号：US13440225
申请日：2012-04-05
申请人： Akio Shima , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
发明人： Akio Shima , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
IPC分类号： G11C11/00 , H01L29/80
CPC分类号： H01L27/2481 , G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2454 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.
摘要翻译：提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以构成三维存储器单元格阵列。存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

5. 发明申请

US20100182828A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20100182828A1
公开(公告)日：2010-07-22
申请号：US12688886
申请日：2010-01-17
申请人： Akio SHIMA , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
发明人： Akio SHIMA , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
IPC分类号： G11C11/00 , H01L47/00 , G11C8/00
CPC分类号： H01L27/2481 , G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2454 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.
摘要翻译：提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以构成三维存储器单元格阵列。存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

6. 发明申请

US20120211718A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20120211718A1
公开(公告)日：2012-08-23
申请号：US13440225
申请日：2012-04-05
申请人： AKIO SHIMA , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
发明人： AKIO SHIMA , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
IPC分类号： H01L45/00
CPC分类号： H01L27/2481 , G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2454 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.
摘要翻译：提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以配置三维存储器单元格阵列。存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

7. 发明授权

US08830740B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08830740B2
公开(公告)日：2014-09-09
申请号：US13814104
申请日：2011-08-26
申请人： Yoshitaka Sasago , Hiroyuki Minemura , Takashi Kobayashi , Toshimichi Shintani , Satoru Hanzawa , Masaharu Kinoshita
发明人： Yoshitaka Sasago , Hiroyuki Minemura , Takashi Kobayashi , Toshimichi Shintani , Satoru Hanzawa , Masaharu Kinoshita
IPC分类号： G11C11/00 , H01L47/00 , G11C13/00
CPC分类号： G11C13/0004 , G11C2213/71 , G11C2213/72 , G11C2213/75 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/1233
摘要： The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line (2) and a bit line (3) and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out.
摘要翻译：本发明的目的是提高相变存储器的重写传输速率和可靠性。为了实现该目的，在串行（2）和位线（3）之间串联提供多个相变存储单元（SMC或USMC），并且具有并联连接的选择元件和存储元件彼此完全设置，之后，与数据模式对应的单元的一部分被重置。或者，执行相反的操作。

8. 发明申请

US20130141968A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20130141968A1
公开(公告)日：2013-06-06
申请号：US13814104
申请日：2011-08-26
申请人： Yoshitaka Sasago , Hiroyuki Minemura , Takashi Kobayashi , Toshimichi Shintani , Satoru Hanzawa , Masaharu Kinoshita
发明人： Yoshitaka Sasago , Hiroyuki Minemura , Takashi Kobayashi , Toshimichi Shintani , Satoru Hanzawa , Masaharu Kinoshita
IPC分类号： G11C13/00
CPC分类号： G11C13/0004 , G11C2213/71 , G11C2213/72 , G11C2213/75 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/1233
摘要： The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line (2) and a bit line (3) and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out.
摘要翻译：本发明的目的是提高相变存储器的重写传输速率和可靠性。为了实现该目的，在串行（2）和位线（3）之间串联提供多个相变存储单元（SMC或USMC），并且具有并联连接的选择元件和存储元件彼此完全设置，之后，与数据模式对应的单元的一部分被重置。或者，执行相反的操作。

9. 发明授权

US08132063B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08132063B2
公开(公告)日：2012-03-06
申请号：US13191442
申请日：2011-07-26
申请人： Motoyasu Terao , Satoru Hanzawa , Hitoshi Kume , Minoru Ogushi , Yoshitaka Sasago , Masaharu Kinoshita , Norikatsu Takaura
发明人： Motoyasu Terao , Satoru Hanzawa , Hitoshi Kume , Minoru Ogushi , Yoshitaka Sasago , Masaharu Kinoshita , Norikatsu Takaura
IPC分类号： G11C29/00
CPC分类号： G11C13/0064 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C29/028 , G11C29/50 , G11C29/50008 , G11C2013/0054 , G11C2213/72
摘要： To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.
摘要翻译：为了实现低功耗的快速且高度可靠的相变存储器系统，半导体器件包括：存储器件，其包括具有包括多个第一存储器单元的第一区域的第一存储器阵列和包括多个第一存储器单元的第二区域第二存储单元; 控制器，其耦合到所述存储器设备以向所述存储器设备发出命令; 以及用于存储多个试写条件的条件表。控制器基于存储在条件表中的多个试写条件，在多个第二存储单元中执行多次尝试写入，并且基于试写的结果来确定多个第一存储单元中的写入条件。存储器件基于从控制器指示的写入条件在多个第一存储器单元中执行写入。

10. 发明申请

US20110283039A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110283039A1
公开(公告)日：2011-11-17
申请号：US13191442
申请日：2011-07-26
申请人： MOTOYASU TERAO , Satoru Hanzawa , Hitoshi Kume , Minoru Ogushi , Yoshitaka Sasago , Masaharu Kinoshita , Norikatsu Takaura
发明人： MOTOYASU TERAO , Satoru Hanzawa , Hitoshi Kume , Minoru Ogushi , Yoshitaka Sasago , Masaharu Kinoshita , Norikatsu Takaura
IPC分类号： G06F12/06
CPC分类号： G11C13/0064 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C29/028 , G11C29/50 , G11C29/50008 , G11C2013/0054 , G11C2213/72
摘要： To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.
摘要翻译：为了实现低功耗的快速且高度可靠的相变存储器系统，半导体器件包括：存储器件，其包括具有包括多个第一存储器单元的第一区域的第一存储器阵列和包括多个第一存储器单元的第二区域第二存储单元; 控制器，其耦合到所述存储器设备以向所述存储器设备发出命令; 以及用于存储多个试写条件的条件表。控制器基于存储在条件表中的多个试写条件，在多个第二存储单元中执行多次尝试写入，并且基于试写的结果来确定多个第一存储单元中的写入条件。存储器件基于从控制器指示的写入条件在多个第一存储器单元中执行写入。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式