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1. 发明授权

US08471235B2 Nonvolatile memory element having a resistance variable layer and manufacturing method thereof 有权
标题翻译：具有电阻变化层的非易失性存储元件及其制造方法
公开(公告)号：US08471235B2
公开(公告)日：2013-06-25
申请号：US13132822
申请日：2009-12-04
申请人： Yoshio Kawashima , Takumi Mikawa , Zhiqiang Wei , Atsushi Himeno
发明人： Yoshio Kawashima , Takumi Mikawa , Zhiqiang Wei , Atsushi Himeno
IPC分类号： H01L29/02
CPC分类号： H01L27/0688 , H01L27/101 , H01L27/2409 , H01L27/2418 , H01L27/2436 , H01L27/2472 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1608
摘要： A nonvolatile memory element includes a substrate; a lower electrode layer and a resistive layer sequentially formed on the substrate; a resistance variable layer formed on the resistive layer; a wire layer formed above the lower electrode layer; an interlayer insulating layer disposed between the substrate and the wire layer and covering at least the lower electrode layer and the resistive layer, the interlayer insulating layer being provided with a contact hole extending from the wire layer to the resistance variable layer; and an upper electrode layer formed inside the contact hole such that the upper electrode layer is connected to the resistance variable layer and to the wire layer; resistance values of the resistance variable layer changing reversibly in response to electric pulses applied between the lower electrode layer and the upper electrode layer.
摘要翻译：非易失性存储元件包括：基板; 在基板上依次形成下电极层和电阻层; 形成在电阻层上的电阻变化层; 形成在所述下电极层的上方的导线层; 层间绝缘层，设置在所述基板和所述线层之间，并且至少覆盖所述下电极层和所述电阻层，所述层间绝缘层设置有从所述导线层延伸到所述电阻变化层的接触孔; 以及形成在所述接触孔内部的上电极层，使得所述上电极层连接到所述电阻变化层和所述导线层; 电阻变化层的电阻值响应于施加在下电极层和上电极层之间的电脉冲而可逆地改变。

2. 发明申请

US20110233511A1 NONVOLATILE MEMORY ELEMENT AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性存储元件及其制造方法
公开(公告)号：US20110233511A1
公开(公告)日：2011-09-29
申请号：US13132822
申请日：2009-12-04
申请人： Yoshio Kawashima , Takumi Mikawa , Zhiqiang Wei , Atsushi Himeno
发明人： Yoshio Kawashima , Takumi Mikawa , Zhiqiang Wei , Atsushi Himeno
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L27/0688 , H01L27/101 , H01L27/2409 , H01L27/2418 , H01L27/2436 , H01L27/2472 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1608
摘要： A nonvolatile memory element (10) of the present invention comprises a substrate (11); a lower electrode layer (15) and a resistive layer (16) sequentially formed on the substrate (11); a resistance variable layer (31) formed on the resistive layer (16); a wire layer (20) formed above the lower electrode layer (15); an interlayer insulating layer (17) disposed between the substrate (11) and the wire layer (20) and covering at least the lower electrode layer (15) and the resistive layer (16), the interlayer insulating layer being provided with a contact hole (26) extending from the wire layer (20) to the resistance variable layer (31); and an upper electrode layer (19) formed inside the contact hole (26) such that the upper electrode layer is connected to the resistance variable layer (31) and to the wire layer (20); resistance values of the resistance variable layer (31) changing reversibly in response to electric pulses applied between the lower electrode layer (15) and the upper electrode layer (19).
摘要翻译：本发明的非易失性存储元件（10）包括衬底（11）; 依次形成在所述基板（11）上的下电极层（15）和电阻层（16）。形成在电阻层（16）上的电阻变化层（31）; 在所述下电极层（15）的上方形成的导线层（20）。设置在所述基板（11）和所述导线层（20）之间并且至少覆盖所述下电极层（15）和所述电阻层（16）的层间绝缘层（17），所述层间绝缘层设置有接触孔（26）从所述导线层（20）延伸到所述电阻变化层（31）; 以及形成在所述接触孔（26）内部的上电极层（19），使得所述上电极层连接到所述电阻变化层（31）和所述导线层（20）; 电阻变化层（31）的电阻值响应于施加在下电极层（15）和上电极层（19）之间的电脉冲而可逆地变化。

3. 发明授权

US08445883B2 Nonvolatile semiconductor memory device and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08445883B2
公开(公告)日：2013-05-21
申请号：US13126975
申请日：2009-07-16
申请人： Atsushi Himeno , Takumi Mikawa , Yoshio Kawashima
发明人： Atsushi Himeno , Takumi Mikawa , Yoshio Kawashima
IPC分类号： H01L29/02
CPC分类号： H01L27/0688 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1683
摘要： A nonvolatile semiconductor memory device which can achieve miniaturization and a larger capacity in a cross-point structure in which memory cells are formed inside contact holes at cross points of word lines and bit lines, respectively, and a manufacturing method thereof are provided. A nonvolatile semiconductor memory device comprises a substrate; a plurality of stripe-shaped lower copper wires (70) formed on the substrate; an interlayer insulating layer (76) formed on the substrate provided with the lower copper wires (70), a plurality of contact holes penetrating interlayer insulating layer (76) to surfaces of the lower copper wires (70), respectively; electrode seed layers (77) and precious metal electrode layers (78) formed only at bottoms of the contact holes, respectively; resistance variable layers (73) filled into the contact holes such that the resistance variable layers are connected to the precious metal electrode layers (73), respectively; a plurality of stripe-shaped upper copper wires (74) connected to the resistance variable layers (73), respectively, and cross the lower copper wires (70), respectively, and the electrode seed layers (77) and the precious metal electrode layers (78) are formed by selective growth plating.
摘要翻译：提供一种非易失性半导体存储器件及其制造方法，该非易失性半导体存储器件分别在字线和位线的交叉点处的接触孔内部形成存储单元的交叉点结构中的小型化和较大容量。非易失性半导体存储器件包括衬底; 形成在所述基板上的多个条状下部铜线（70）形成在设置有下铜线（70）的基板上的层间绝缘层（76），分别向下铜线（70）的表面贯穿层间绝缘层（76）的多个接触孔; 电极种子层（77）和仅在接触孔的底部形成的贵金属电极层（78）; 电阻变化层（73）填充到接触孔中，使得电阻变化层分别连接到贵金属电极层（73）; 分别连接到电阻变化层（73）的多个条状上部铜线（74），分别与下部铜线（70）交叉，电极种子层（77）和贵金属电极层（78）通过选择性生长电镀形成。

4. 发明申请

US20110220862A1 RESISTANCE VARIABLE ELEMENT AND RESISTANCE VARIABLE MEMORY DEVICE 有权
标题翻译：电阻可变元件和电阻可变存储器件
公开(公告)号：US20110220862A1
公开(公告)日：2011-09-15
申请号：US13128575
申请日：2010-07-12
申请人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
发明人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1666 , H01L45/1675
摘要： A resistance variable element (100) used in a through-hole cross-point structure memory device, according to the present invention, and a resistance variable memory device including the resistance variable element, includes a substrate (7) and an interlayer insulating layer (3) formed on the substrate, and have a configuration in which a through-hole (4) is formed to penetrate the interlayer insulating layer, a first resistance variable layer (2) comprising transition metal oxide is formed outside the through-hole, a second resistance variable layer (5) comprising transition metal oxide is formed inside the through-hole, the first resistance variable layer is different in resistivity from the second resistance variable layer, and the first resistance variable layer and the second resistance variable layer are in contact with each other only in an opening (20) of the through-hole which is closer to the substrate.
摘要翻译：在根据本发明的通孔交叉点结构存储装置中使用的电阻可变元件（100）和包括电阻可变元件的电阻变化存储装置包括基板（7）和层间绝缘层（ 3），并且具有形成贯通层间绝缘层的通孔（4）的构造，在通孔的外侧形成有包含过渡金属氧化物的第一电阻变化层（2），在通孔内形成有包含过渡金属氧化物的第二电阻变化层（5），第一电阻变化层的电阻率与第二电阻变化层不同，第一电阻变化层和第二电阻变化层接触彼此仅在更靠近基板的通孔的开口（20）中。

5. 发明申请

US20110220861A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20110220861A1
公开(公告)日：2011-09-15
申请号：US13126975
申请日：2009-07-16
申请人： Atsushi Himeno , Takumi Mikawa , Yoshio Kawashima
发明人： Atsushi Himeno , Takumi Mikawa , Yoshio Kawashima
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L27/0688 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1683
摘要： A nonvolatile semiconductor memory device which can achieve miniaturization and a larger capacity in a cross-point structure in which memory cells are formed inside contact holes at cross points of word lines and bit lines, respectively, and a manufacturing method thereof are provided. A nonvolatile semiconductor memory device comprises a substrate; a plurality of stripe-shaped lower copper wires (70) formed on the substrate; an interlayer insulating layer (76) formed on the substrate provided with the lower copper wires (70), a plurality of contact holes penetrating interlayer insulating layer (76) to surfaces of the lower copper wires (70), respectively; electrode seed layers (77) and precious metal electrode layers (78) formed only at bottoms of the contact holes, respectively; resistance variable layers (73) filled into the contact holes such that the resistance variable layers are connected to the precious metal electrode layers (73), respectively; a plurality of stripe-shaped upper copper wires (74) connected to the resistance variable layers (73), respectively, and cross the lower copper wires (70), respectively, and the electrode seed layers (77) and the precious metal electrode layers (78) are formed by selective growth plating.
摘要翻译：提供一种非易失性半导体存储器件及其制造方法，该非易失性半导体存储器件分别在字线和位线的交叉点处的接触孔内部形成存储单元的交叉点结构中的小型化和较大容量。非易失性半导体存储器件包括衬底; 形成在所述基板上的多个条状下部铜线（70）形成在设置有下铜线（70）的基板上的层间绝缘层（76），分别向下铜线（70）的表面贯穿层间绝缘层（76）的多个接触孔; 电极种子层（77）和仅在接触孔的底部形成的贵金属电极层（78）; 电阻变化层（73）填充到接触孔中，使得电阻变化层分别连接到贵金属电极层（73）; 分别连接到电阻变化层（73）的多个条状上部铜线（74），并分别与下部铜线（70）交叉，电极种子层（77）和贵金属电极层（78）通过选择性生长电镀形成。

6. 发明申请

US20130149815A1 NONVOLATILE MEMORY ELEMENT MANUFACTURING METHOD AND NONVOLATILE MEMORY ELEMENT 审中-公开
标题翻译：非易失性存储元件制造方法和非易失性存储元件
公开(公告)号：US20130149815A1
公开(公告)日：2013-06-13
申请号：US13810465
申请日：2012-09-10
申请人： Hideaki Murase , Takumi Mikawa , Yoshio Kawashima , Atsushi Himeno
发明人： Hideaki Murase , Takumi Mikawa , Yoshio Kawashima , Atsushi Himeno
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： A method of manufacturing a nonvolatile memory element includes: forming a first conductive film above a substrate; forming, above the first conductive film, a first metal oxide layer and a second metal oxide layer having different degrees of oxygen deficiency and a second conductive film; forming a second electrode by patterning the second conductive film; forming a variable resistance layer by patterning the first metal oxide layer and the second metal oxide layer; removing a side portion of the variable resistance layer in a surface parallel to a main surface of the substrate to a position that is further inward than an edge of the second electrode; and forming a first electrode by patterning the first conductive film after or during the removing.
摘要翻译：一种制造非易失性存储元件的方法包括：在衬底上形成第一导电膜; 在第一导电膜上方形成具有不同程度的氧缺陷的第一金属氧化物层和第二金属氧化物层和第二导电膜; 通过图案化第二导电膜形成第二电极; 通过图案化第一金属氧化物层和第二金属氧化物层来形成可变电阻层; 将平行于所述基板的主表面的表面中的所述可变电阻层的侧部移除到比所述第二电极的边缘更靠内侧的位置; 以及通过在去除之后或期间对第一导电膜进行图案化而形成第一电极。

7. 发明授权

US08394669B2 Resistance variable element and resistance variable memory device 有权
标题翻译：电阻可变元件和电阻变量存储器件
公开(公告)号：US08394669B2
公开(公告)日：2013-03-12
申请号：US13128575
申请日：2010-07-12
申请人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
发明人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
IPC分类号： H01L21/02 , H01L45/00
CPC分类号： H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1666 , H01L45/1675
摘要： A resistance variable element (100) used in a through-hole cross-point structure memory device, according to the present invention, and a resistance variable memory device including the resistance variable element, includes a substrate (7) and an interlayer insulating layer (3) formed on the substrate, and have a configuration in which a through-hole (4) is formed to penetrate the interlayer insulating layer, a first resistance variable layer (2) comprising transition metal oxide is formed outside the through-hole, a second resistance variable layer (5) comprising transition metal oxide is formed inside the through-hole, the first resistance variable layer is different in resistivity from the second resistance variable layer, and the first resistance variable layer and the second resistance variable layer are in contact with each other only in an opening (20) of the through-hole which is closer to the substrate.
摘要翻译：在根据本发明的通孔交叉点结构存储装置中使用的电阻可变元件（100）和包括电阻可变元件的电阻变化存储装置包括基板（7）和层间绝缘层（ 3），并且具有形成贯通层间绝缘层的通孔（4）的构造，在通孔的外侧形成有包含过渡金属氧化物的第一电阻变化层（2），在通孔内形成有包含过渡金属氧化物的第二电阻变化层（5），第一电阻变化层的电阻率与第二电阻变化层不同，第一电阻变化层和第二电阻变化层接触彼此仅在更靠近基板的通孔的开口（20）中。

8. 发明授权

US08426836B2 Nonvolatile memory device and manufacturing method thereof 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US08426836B2
公开(公告)日：2013-04-23
申请号：US13132544
申请日：2009-06-30
申请人： Takumi Mikawa , Yoshio Kawashima , Atsushi Himeno
发明人： Takumi Mikawa , Yoshio Kawashima , Atsushi Himeno
IPC分类号： H01L29/02
CPC分类号： H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/1683
摘要： There are provided a resistance variable nonvolatile memory device which changes its resistance stably at low voltages and is suitable for a miniaturized configuration, and a manufacturing method thereof. The nonvolatile memory device comprises: a substrate (100); a first electrode (101); an interlayer insulating layer (102); a memory cell hole (103) formed in the interlayer insulating layer; a first resistance variable layer (104a) formed in at least a bottom portion of the memory cell hole and connected to the first electrode; a second resistance variable layer (104b) formed inside the memory cell hole (103) and located on the first resistance variable layer (104a); and a second electrode (105); the first resistance variable layer (104a) and the second resistance variable layer (104b) respectively comprising metal oxides of the same kind; and the first resistance variable layer (104a) having a higher oxygen content than the second resistance variable layer (104b).
摘要翻译：提供了一种电阻可变非易失性存储器件，其在低电压下稳定地改变其电阻并且适合于小型化构造及其制造方法。非易失性存储器件包括：衬底（100）; 第一电极（101）; 层间绝缘层（102）; 形成在所述层间绝缘层中的记忆单元孔（103）形成在所述存储单元孔的至少底部并连接到所述第一电极的第一电阻变化层（104a）形成在所述存储单元孔内并位于所述第一电阻变化层上的第二电阻变化层，和第二电极（105）; 分别包含相同种类的金属氧化物的第一电阻变化层（104a）和第二电阻变化层（104b）和具有比第二电阻变化层（104b）高的氧含量的第一电阻变化层（104a）。

9. 发明申请

US20120097915A1 NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20120097915A1
公开(公告)日：2012-04-26
申请号：US13132544
申请日：2009-06-30
申请人： Takumi Mikawa , Yoshio Kawashima , Atsushi Himeno
发明人： Takumi Mikawa , Yoshio Kawashima , Atsushi Himeno
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/1683
摘要： There are provided a resistance variable nonvolatile memory device which changes its resistance stably at low voltages and is suitable for a miniaturized configuration, and a manufacturing method thereof. The nonvolatile memory device comprises: a substrate (100); a first electrode (101); an interlayer insulating layer (102); a memory cell hole (103) formed in the interlayer insulating layer; a first resistance variable layer (104a) formed in at least a bottom portion of the memory cell hole and connected to the first electrode; a second resistance variable layer (104b) formed inside the memory cell hole (103) and located on the first resistance variable layer (104a); and a second electrode (105); the first resistance variable layer (104a) and the second resistance variable layer (104b) respectively comprising metal oxides of the same kind; and the first resistance variable layer (104a) having a higher oxygen content than the second resistance variable layer (104b).
摘要翻译：提供了一种电阻可变非易失性存储器件，其在低电压下稳定地改变其电阻并且适合于小型化构造及其制造方法。非易失性存储器件包括：衬底（100）; 第一电极（101）; 层间绝缘层（102）; 形成在所述层间绝缘层中的记忆单元孔（103）形成在所述存储单元孔的至少底部并连接到所述第一电极的第一电阻变化层（104a）形成在所述存储单元孔内并位于所述第一电阻变化层上的第二电阻变化层，和第二电极（105）; 分别包含相同种类的金属氧化物的第一电阻变化层（104a）和第二电阻变化层（104b）和具有比第二电阻变化层（104b）高的氧含量的第一电阻变化层（104a）。

10. 发明申请

US20090014710A1 NONVOLATILE MEMORY ELEMENT, NONVOLATILE MEMORY APPARATUS, AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：非易失性存储元件，非易失性存储器件及其制造方法
公开(公告)号：US20090014710A1
公开(公告)日：2009-01-15
申请号：US12281034
申请日：2007-03-06
申请人： Yoshio Kawashima , Takeshi Takagi , Takumi Mikawa , Zhiqiang Wei
发明人： Yoshio Kawashima , Takeshi Takagi , Takumi Mikawa , Zhiqiang Wei
IPC分类号： H01L45/00
CPC分类号： H01L27/101 , H01L27/2409 , H01L27/2463 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1658 , H01L45/1675
摘要： A lower electrode layer 2, an upper electrode layer 4 formed above the lower electrode layer 2, and a metal oxide thin film layer 3 formed between the lower electrode layer 2 and the upper electrode layer 4 are provided. The metal oxide thin film layer 3 includes a first region 3a whose value of resistance increases or decreases by an electric pulse that is applied between the lower electrode layer 2 and the upper electrode layer 4 and a second region 3b arranged around the first region 3a and having a larger content of oxygen than the first region 3a, wherein the lower and upper electrode layers 2 and 4 and at least a part of the first region 3a are arranged so as to overlap as viewed from the direction of the thickness of the first region 3a.
摘要翻译：设置下电极层2，形成在下电极层2上的上电极层4和形成在下电极层2和上电极层4之间的金属氧化物薄膜层3。金属氧化物薄膜层3包括第一区域3a，其第一区域3a的电阻值通过施加在下电极层2和上电极层4之间的电脉冲和围绕第一区域3a布置的第二区域3b而增大或减小，以及具有比第一区域3a更大的氧含量，其中下电极层2和上电极层4以及第一区域3a的至少一部分从第一区域的厚度方向观察而重叠 3a。

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