专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 再颁专利

USRE41235E1 Phase locked loop circuit 有权
标题翻译：锁相环电路
公开(公告)号：USRE41235E1
公开(公告)日：2010-04-20
申请号：US11653419
申请日：2007-01-16
申请人： Yoshinori Miyada , Seiji Watanabe
发明人： Yoshinori Miyada , Seiji Watanabe
IPC分类号： H03L7/00
CPC分类号： H03L7/113 , H03L7/087 , H03L7/0891
摘要： A PLL circuit comprises a frequency comparator for detecting a phase difference based on a difference in frequencies between a reproduced data pulse and a clock generated by a VCO; a phase comparator for detecting a difference in phases between the reproduced data pulse and the VCO clock; a selector for selectively outputting a signal supplied from the frequency comparator, a first charge pump for increasing/decreasing the output voltage on the basis of the output from the selector; a second charge pump for increasing/decreasing the output voltage on the basis of the output from the phase comparator; a loop filter for eliminating unnecessary components included in a signal obtained by adding the output from the first charge pump and the output from the second charge pump; and a VCO for generating a clock of a frequency corresponding to the output voltage of the loop filter. In this PLL circuit, when the phase difference between the reproduced data pulse and the VCO clock is within the pull-in range of the phase comparator, the operation of the frequency comparator is restricted by the output of the phase comparator. Therefore, the PLL circuit can perform stable data reading even when the reproduced data pulse has a large amount of clock jitter.
摘要翻译： PLL电路包括：频率比较器，用于基于再现的数据脉冲和由VCO产生的时钟之间的频率差来检测相位差; 用于检测再现数据脉冲和VCO时钟之间的相位差的相位比较器; 选择器，用于选择性地输出从频率比较器提供的信号;第一电荷泵，用于根据选择器的输出增加/减少输出电压; 第二电荷泵，用于根据相位比较器的输出增加/减少输出电压; 环路滤波器，用于消除通过将来自第一电荷泵的输出和来自第二电荷泵的输出相加而获得的信号中包含的不必要的分量; 以及用于产生与环路滤波器的输出电压相对应的频率的时钟的VCO。在该PLL电路中，当再现的数据脉冲和VCO时钟之间的相位差在相位比较器的拉入范围内时，频率比较器的操作受到相位比较器的输出的限制。因此，即使当再现的数据脉冲具有大量的时钟抖动时，PLL电路也可以执行稳定的数据读取。

2. 发明授权

US06489851B1 Phase locked loop circuit 有权
标题翻译：锁相环电路
公开(公告)号：US06489851B1
公开(公告)日：2002-12-03
申请号：US09721874
申请日：2000-11-27
申请人： Yoshinori Miyada , Seiji Watanabe
发明人： Yoshinori Miyada , Seiji Watanabe
IPC分类号： H03L700
CPC分类号： H03L7/113 , H03L7/087 , H03L7/0891
摘要： A PLL circuit comprises a frequency comparator for detecting a phase difference based on a difference in frequencies between a reproduced data pulse and a clock generated by a VCO; a phase comparator for detecting a difference in phases between the reproduced data pulse and the VCO clock; a selector for selectively outputting a signal supplied from the frequency comparator; a first charge pump for increasing/decreasing the output voltage on the basis of the output from the selector; a second charge pump for increasing/decreasing the output voltage on the basis of the output from the phase comparator; a loop filter for eliminating unnecessary components included in a signal obtained by adding the output from the first charge pump and the output from the second charge pump; and a VCO for generating a clock of a frequency corresponding to the output voltage of the loop filter. In this PLL circuit, when the phase difference between the reproduced data pulse and the VCO clock is within the pull-in range of the phase comparator, the operation of the frequency comparator is restricted by the output of the phase comparator. Therefore, the PLL circuit can perform stable data reading even when the reproduced data pulse has a large amount of clock jitter.
摘要翻译： PLL电路包括：频率比较器，用于基于再现的数据脉冲和由VCO产生的时钟之间的频率差来检测相位差; 用于检测再现数据脉冲和VCO时钟之间的相位差的相位比较器; 选择器，用于选择性地输出从频率比较器提供的信号; 第一电荷泵，用于根据选择器的输出增加/减少输出电压; 第二电荷泵，用于根据相位比较器的输出增加/减小输出电压; 环路滤波器，用于消除通过将来自第一电荷泵的输出和来自第二电荷泵的输出相加而获得的信号中包含的不必要的分量; 以及用于产生与环路滤波器的输出电压相对应的频率的时钟的VCO。在该PLL电路中，当再现的数据脉冲和VCO时钟之间的相位差在相位比较器的拉入范围内时，频率比较器的操作受到相位比较器的输出的限制。因此，即使当再现的数据脉冲具有大量的时钟抖动时，PLL电路也可以执行稳定的数据读取。

3. 再颁专利

USRE39807E1 Phase locked loop circuit 有权
标题翻译：锁相环电路
公开(公告)号：USRE39807E1
公开(公告)日：2007-09-04
申请号：US10635534
申请日：2003-08-07
申请人： Yoshinori Miyada , Seiji Watanabe
发明人： Yoshinori Miyada , Seiji Watanabe
IPC分类号： H03L7/00
CPC分类号： H03L7/113 , H03L7/087 , H03L7/0891
摘要： A PLL circuit comprises a frequency comparator for detecting a phase difference based on a difference in frequencies between a reproduced data pulse and a clock generated by a VCO; a phase comparator for detecting a difference in phases between the reproduced data pulse and the VCO clock; a selector for selectively outputting a signal supplied from the frequency comparator; a first charge pump for increasing/decreasing the output voltage on the basis of the output from the selector; a second charge pump for increasing/decreasing the output voltage on the basis of the output from the phase comparator; a loop filter for eliminating unnecessary components included in a signal obtained by adding the output from the first charge pump and the output from the second charge pump; and a VCO for generating a clock of a frequency corresponding to the output voltage of the loop filter. In this PLL circuit, when the phase difference between the reproduced data pulse and the VCO clock is within the pull-in range of the phase comparator, the operation of the frequency comparator is restricted by the output of the phase comparator. Therefore, the PLL circuit can perform stable data reading even when the reproduced data pulse has a large amount of clock jitter.
摘要翻译： PLL电路包括：频率比较器，用于基于再现的数据脉冲和由VCO产生的时钟之间的频率差来检测相位差; 用于检测再现数据脉冲和VCO时钟之间的相位差的相位比较器; 选择器，用于选择性地输出从频率比较器提供的信号; 第一电荷泵，用于根据选择器的输出增加/减少输出电压; 第二电荷泵，用于根据相位比较器的输出增加/减少输出电压; 环路滤波器，用于消除通过将来自第一电荷泵的输出和来自第二电荷泵的输出相加而获得的信号中包含的不必要的分量; 以及用于产生与环路滤波器的输出电压相对应的频率的时钟的VCO。在该PLL电路中，当再现的数据脉冲和VCO时钟之间的相位差在相位比较器的拉入范围内时，频率比较器的操作受到相位比较器的输出的限制。因此，即使当再现的数据脉冲具有大量的时钟抖动时，PLL电路也可以执行稳定的数据读取。

4. 发明授权

US06777775B2 Semiconductor integrated circuit, D-A converter device, and A-D converter device 有权
标题翻译：半导体集成电路，D-A转换器和A-D转换器
公开(公告)号：US06777775B2
公开(公告)日：2004-08-17
申请号：US10187378
申请日：2002-07-02
申请人： Yoshinori Miyada , Kenji Murata , Daisuke Nomasaki
发明人： Yoshinori Miyada , Kenji Murata , Daisuke Nomasaki
IPC分类号： H01L2900
CPC分类号： H01L27/0805 , H01L23/5225 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.
摘要翻译：半导体集成电路具有多个电容器单元，并且每个电容器单元具有上电极和下电极。这些电极分别连接到上电极布线和下电极。当例如上电极连接到上电极布线并且电极布线位于另一个电容器单元的下电极的一侧或连接这些电极的下电极布线的一侧时，屏蔽布线设置在上电极布线和另一个电容器单元的相邻位置的下电极或上电极布线和相邻位置的下电极布线之间。因此，利用该屏蔽布线，可以有效地抑制电容器单元的各布线与电容器单元的每个上电极或每个下电极之间的电容耦合。

5. 发明授权

US06300891B1 D/A conversion apparatus 失效
标题翻译： D / A转换装置
公开(公告)号：US06300891B1
公开(公告)日：2001-10-09
申请号：US09266601
申请日：1999-03-11
申请人： Yasunori Tani , Yoshinori Miyada , Kazuyuki Hyobu
发明人： Yasunori Tani , Yoshinori Miyada , Kazuyuki Hyobu
IPC分类号： H03M166
CPC分类号： H03M1/0665 , H03M1/66
摘要： To provide a D/A conversion apparatus that can minimize the increase in the amount of circuitry if the number of output levels is increased, a digital input value, input for each sampling clock, is first converted by a digital filter and a noise shaper into a word length limited digital signal with a high sampling frequency. The output of the noise shaper is mapped by a decoder to n m-valued signals a “1” at a time in a cyclic fashion progressing from one signal to the next so that the sum of the n m-valued signals becomes equal to the digital input value; thereafter, the n m-valued signals are converted by n m-valued D/A converters into corresponding analog signals which are then summed together by an analog adder to produce an analog output signal. The term “cyclic” means not only that one digital input value is mapped to the n m-valued signals a “1” at a time in a cyclic fashion progressing from one signal to the next, but also that the mapping of the present digital input value to the n m-valued signals is performed starting with the m-valued signal that immediately follows the m-valued signal to which the preceding digital input value was last mapped.
摘要翻译：为了提供D / A转换装置，如果输出电平的数量增加，可以最小化电路量的增加，则每个采样时钟的输入的数字输入值首先由数字滤波器和噪声整形器转换成具有高采样频率的字长限制数字信号。噪声整形器的输出由解码器以从一个信号到下一个信号的循环方式一次映射到n个m值信号a“1”，使得n个m值信号的和变为等于数字输入值; 此后，n个m值的信号由n个m值D / A转换器转换成相应的模拟信号，然后由模拟加法器将它们相加在一起以产生模拟输出信号。术语“循环”不仅意味着一个数字输入值以一个从一个信号到下一个信号的循环方式一次被映射到n个m值信号a“1”，而且表示当前数字从n个m值信号的输入值开始，以与上一个数字输入值最后映射到的m值信号紧邻的m值信号开始。

6. 发明授权

US07777293B2 Semiconductor integrated circuit, D-A converter device, and A-D converter device 有权
标题翻译：半导体集成电路，D-A转换器和A-D转换器
公开(公告)号：US07777293B2
公开(公告)日：2010-08-17
申请号：US10898965
申请日：2004-07-27
申请人： Yoshinori Miyada , Kenji Murata , Daisuke Nomasaki
发明人： Yoshinori Miyada , Kenji Murata , Daisuke Nomasaki
IPC分类号： H01L29/93
CPC分类号： H01L27/0805 , H01L23/5225 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.
摘要翻译：半导体集成电路具有多个电容器单元，并且每个电容器单元具有上电极和下电极。这些电极分别连接到上电极布线和下电极。当例如上电极连接到上电极布线并且电极布线位于另一个电容器单元的下电极的一侧或连接这些电极的下电极布线的一侧时，屏蔽布线设置在上电极布线和另一个电容器单元的相邻位置的下电极或上电极布线和相邻位置的下电极布线之间。因此，利用该屏蔽布线，可以有效地抑制电容器单元的各布线与电容器单元的每个上电极或每个下电极之间的电容耦合。

7. 发明授权

US06927723B2 A/D converter and A/D conversion method 失效
标题翻译： A / D转换器和A / D转换方法
公开(公告)号：US06927723B2
公开(公告)日：2005-08-09
申请号：US10855397
申请日：2004-05-28
申请人： Daisuke Nomasaki , Kenji Murata , Hideki Tanaka , Yoshinori Miyada
发明人： Daisuke Nomasaki , Kenji Murata , Hideki Tanaka , Yoshinori Miyada
IPC分类号： H03M1/12 , H03M1/46
CPC分类号： H03M1/124 , H03M1/468
摘要： In a charge redistribution type A/D converter, an input-side capacitor terminal and a comparator-side capacitor terminal are connected through first and second analog switches to a fixed-voltage supply circuit, and the input-side capacitor terminal is connected through a third analog switch to the outside. Immediately before sampling an analog signal, the first and second analog switches are closed while the third analog switch is opened, according to a RESET signal. Thereby, fixed voltages are supplied to the input-side capacitor terminal and the comparator-side capacitor terminal, respectively, and charge stored in a weighting capacitor unit is initialized to a predetermined value.
摘要翻译：在电荷再分配型A / D转换器中，输入侧电容器端子和比较器侧电容器端子通过第一和第二模拟开关连接到固定电压电源电路，并且输入侧电容器端子通过第三个模拟开关到外面。在采样模拟信号之前，根据RESET信号，第三模拟开关打开时，第一和第二模拟开关闭合。由此，固定电压分别被提供给输入侧电容器端子和比较器侧电容器端子，并将存储在加权电容器单元中的电荷初始化为预定值。

8. 发明申请

US20050110530A1 Differential output circuit 审中-公开
标题翻译：差分输出电路
公开(公告)号：US20050110530A1
公开(公告)日：2005-05-26
申请号：US10988524
申请日：2004-11-16
申请人： Masahiro Aoike , Yoshinori Miyada , Takahiro Bokui
发明人： Masahiro Aoike , Yoshinori Miyada , Takahiro Bokui
IPC分类号： H03K5/003 , H03K5/22 , H03K19/0175 , H04L25/02
CPC分类号： H04L25/0274 , H03K5/003 , H04L25/028
摘要： A differential output circuit which performs data transmission by means of a differential current comprises: a first current source for outputting an electric current to the outside of the circuit; a second current source for introducing an electric current from the outside of the circuit; an output polarity switching circuit for switching the polarity of the differential current generated by the first and second current sources; a voltage source for supplying a predetermined voltage; and a resistor connected between a predetermined node and the voltage source, the predetermined node being interposed between the first and second current sources.
摘要翻译：通过差分电流进行数据传输的差分输出电路包括：用于向电路外部输出电流的第一电流源; 用于从电路的外部引入电流的第二电流源; 输出极性切换电路，用于切换由第一和第二电流源产生的差动电流的极性; 用于提供预定电压的电压源; 以及连接在预定节点和电压源之间的电阻器，所述预定节点插在第一和第二电流源之间。

9. 发明申请

US20050001291A1 Semiconductor integrated circuit, D-A converter device, and A-D converter device 有权
标题翻译：半导体集成电路，D-A转换器和A-D转换器
公开(公告)号：US20050001291A1
公开(公告)日：2005-01-06
申请号：US10898965
申请日：2004-07-27
申请人： Yoshinori Miyada , Kenji Murata , Daisuke Nomasaki
发明人： Yoshinori Miyada , Kenji Murata , Daisuke Nomasaki
IPC分类号： H01L27/04 , H01L21/822 , H01L23/522 , H01L27/08 , H01L23/552
CPC分类号： H01L27/0805 , H01L23/5225 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.
摘要翻译：半导体集成电路具有多个电容器单元，并且每个电容器单元具有上电极和下电极。这些电极分别连接到上电极布线和下电极。当例如上电极连接到上电极布线并且电极布线位于另一个电容器单元的下电极的一侧或连接这些电极的下电极布线的一侧时，屏蔽布线设置在上电极布线和另一个电容器单元的相邻位置的下电极或上电极布线和相邻位置的下电极布线之间。因此，利用该屏蔽布线，可以有效地抑制电容器单元的各布线与电容器单元的每个上电极或每个下电极之间的电容耦合。

10. 发明授权

US06674330B2 Recording clock generation circuit 有权
标题翻译：录制时钟发生电路
公开(公告)号：US06674330B2
公开(公告)日：2004-01-06
申请号：US10215159
申请日：2002-08-08
申请人： Takahiro Bokui , Takahiro Ochi , Yoshinori Miyada , Yutaka Murata
发明人： Takahiro Bokui , Takahiro Ochi , Yoshinori Miyada , Yutaka Murata
IPC分类号： H03L700
CPC分类号： G11B20/1403 , G11B7/0053 , G11B20/10222 , G11B20/22 , H03L7/081 , H03L7/087
摘要： A recording clock generation circuit includes a first phase comparator for detecting a phase difference between a wobble signal and a PLL internal signal; a first filter for smoothing an output from the first phase comparator; a VCO circuit for oscillating in accordance with the output smoothed by the first filter; a frequency divider for dividing a frequency of an output from the VCO circuit; a phase adjusting circuit for adjusting a phase of an output from the frequency divider; and a second phase comparator for detecting a phase difference between the wobble signal and a pre-pit signal, and outputting the phase difference to the phase adjusting circuit.
摘要翻译：记录时钟产生电路包括用于检测摆动信号和PLL内部信号之间的相位差的第一相位比较器; 用于平滑来自第一相位比较器的输出的第一滤波器; VCO电路，用于根据由第一滤波器平滑的输出振荡; 用于分频来自VCO电路的输出频率的分频器; 相位调整电路，用于调节来自分频器的输出的相位; 以及第二相位比较器，用于检测摆动信号和预凹陷信号之间的相位差，并将相位差输出到相位调整电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式