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    • 2. 发明申请
    • Communication control device, information processing device and computer program product
    • 通讯控制装置,信息处理装置及电脑程式产品
    • US20090210586A1
    • 2009-08-20
    • US12320954
    • 2009-02-10
    • Noboru Tanabe
    • Noboru Tanabe
    • G06F3/00
    • H04L49/9063H04L45/745H04L49/90H04L49/9021H04L49/9073
    • A communication control device includes a plurality of receive buffers each storing therein received information that corresponds to all or a part of a received message or an argument of a receive function, a hash-value generating unit that generates a hash value from a receive key contained in the received message in accordance with a hash-value generation rule, a storing unit that stores the received information in a selected one of the receive buffers corresponding to the hash value, and an output unit that outputs the received information from one of the receive buffers corresponding to the hash value in response to a transmission request from a receiving unit that performs a receiving operation by determining a matching based on a receive key specified by the receive function.
    • 通信控制装置包括多个接收缓冲器,每个接收缓冲器存储其中接收到的与接收到的消息的全部或一部分或接收功能的参数相对应的信息,散列值生成单元,其从包含的接收密钥生成散列值 在根据哈希值生成规则的接收到的消息中,存储单元,其将所接收的信息存储在与所述散列值相对应的所述接收缓冲器中的所选择的一个中;以及输出单元,其从所述接收 响应于来自执行接收操作的接收单元的发送请求,基于由接收功能指定的接收键确定匹配,对应于散列值的缓冲器。
    • 4. 发明授权
    • Memory access control device with prefetch and read out block length
control functions
    • 具有预取和读出块长度控制功能的存储器访问控制装置
    • US5752272A
    • 1998-05-12
    • US729319
    • 1996-10-15
    • Noboru Tanabe
    • Noboru Tanabe
    • G06F12/08G06F9/38G06F12/00G06F12/02G06F12/04
    • G06F9/383G06F12/0862
    • A memory access control device capable of reducing the cache miss penalty and taking an advantage of the DRAM with a high transmission bandwidth. In this device, a high speed memory for storing block data read from the memory device is provided, Then, when an access request is received from the master device, data requested by the access request is returned from the high speed memory to the master device whenever the data requested by the access request are contained in the block data stored in the high speed memory. Otherwise new block data of a variable block length to be stored in the high speed memory is read from the memory device according to the access request received from the master device. The block data includes prefetch data which have a possibility for being requested by a next access request from the master device. The device may include an access continuity judging unit for judging an access continuity for memory accesses made by the master device such that the read out block length of the new block data is controlled according to the access continuity.
    • 一种存储器访问控制装置,其能够降低高速缓存未命中并利用具有高传输带宽的DRAM的优点。 在该装置中,提供用于存储从存储装置读取的块数据的高速存储器,然后,当从主装置接收到访问请求时,由访问请求请求的数据从高速存储器返回到主装置 每当访问请求所请求的数据被包含在存储在高速存储器中的块数据中时。 否则,根据从主设备接收的访问请求,从存储设备读取要存储在高速存储器中的可变块长度的新块数据。 块数据包括预取数据,其具有可能被来自主设备的下一访问请求请求。 该设备可以包括访问连续性判断单元,用于判断由主设备进行的存储器访问的访问连续性,使得根据访问连续​​性来控制新的块数据的读出块长度。