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    • 6. 发明授权
    • Image display apparatus
    • 图像显示装置
    • US07358936B2
    • 2008-04-15
    • US10860036
    • 2004-06-04
    • Yoshinao KobayashiShinya Ono
    • Yoshinao KobayashiShinya Ono
    • G09G3/30
    • G09G3/325G09G2300/0417G09G2300/0842G09G2300/0861
    • An image display apparatus includes a current-controlled light emitting; a transistor which controls a first current flowing through the current-controlled light emitting diode, based on a first voltage applied between the gate and the source of the transistor at a light emitting phase; a capacitor arranged between the gate and the source. The image display apparatus also includes a current determining unit which controls a second current flowing between the source and the drain, based on a third voltage applied thereto at the writing phase. The second voltage is written in the capacitor at a writing phase and depends on the second current.
    • 图像显示装置包括电流控制的发光; 基于在发光相位处施加在晶体管的栅极和源极之间的第一电压来控制流过电流控制的发光二极管的第一电流的晶体管; 设置在栅极和源极之间的电容器。 图像显示装置还包括电流确定单元,其基于在写入阶段施加到其上的第三电压来控制在源极和漏极之间流动的第二电流。 第二电压以写入阶段写入电容器,并取决于第二电流。
    • 10. 发明授权
    • Carry skip adder
    • 携带跳过加法器
    • US06199091B1
    • 2001-03-06
    • US09102532
    • 1998-06-22
    • Yoshinao KobayashiAkashi SatohSeiji Munetoh
    • Yoshinao KobayashiAkashi SatohSeiji Munetoh
    • G06F750
    • G06F7/508
    • A carry skip adder comprises a plurality of ripple adders, wherein at least one part of the plurality of ripple adders is divided into a plurality of groups, and a carry signal is transferred from one group to one upper group. In addition, a circuit for calculating C=C2+F*C1 is included, wherein the C1 denotes a carry signal from the one group to the one upper group, and the F denotes a signal indicating whether or not outputs of all adders in the one upper group are is, and the C2 denotes a carry signal associated with the most upper ripple adder in the one upper group. In a group including two or more ripple adders, a plurality of ripple adders in the group are organized into a plurality of sub-groups, and a carry signal is transferred from one sub-group to one upper sub-group, a circuit for calculating C5=C4+F1*C3 is included, wherein the C3 denotes a carry signal from the one sub-group to the one upper sub-group, and the F1 denotes a signal indicating whether or not outputs of all adder in the one upper sub-group are is, and the C4 denotes a carry signal associated with the most upper ripple adder in the one upper sub-group.
    • 进位跳跃加法器包括多个纹波加法器,其中多个波纹加法器的至少一部分被分成多个组,并且进位信号从一组传送到一个上组。 此外,包括用于计算C = C2 + F * C1的电路,其中C1表示从一个组到一个上位组的进位信号,F表示指示是否存在所有加法器的输出的信号 一个上部组是,并且C2表示与一个上部组中的最上部纹波加法器相关联的进位信号。 在包括两个或多个波纹加法器的组中,组中的多个波纹加法器被组织成多个子组,并且进位信号从一个子组传送到一个上部子组,计算电路 C5 = C4 + F1 * C3,其中C3表示从一个子组到一个上部子组的进位信号,F1表示指示上一个子组中所有加法器的输出是否为 - 组是,并且C4表示与一个上部子组中的最上部纹波加法器相关联的进位信号。