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1. 发明申请

US20120226861A1 STORAGE CONTROLLER AND METHOD OF CONTROLLING STORAGE CONTROLLER 有权
标题翻译：存储控制器及控制存储控制器的方法
公开(公告)号：US20120226861A1
公开(公告)日：2012-09-06
申请号：US13119292
申请日：2011-03-03
申请人： Yoshihiro Yoshii , Mitsuru Inoue , Kentaro Shimada , Sadahiro Sugimoto
发明人： Yoshihiro Yoshii , Mitsuru Inoue , Kentaro Shimada , Sadahiro Sugimoto
IPC分类号： G06F12/08
CPC分类号： G06F12/0871 , G06F12/0868
摘要： Provided is a storage controller and method of controlling same which, if part of a storage area of a local memory is used as cache memory, enable an access conflict for access to a parallel bus connected to the local memory to be avoided.A storage controller which exercises control of data between a host system and a storage apparatus, comprising a data transfer control unit which exercises control to transfer the data on the basis of a read/write request from the host system; a cache memory which is connected to the data transfer control unit via a parallel bus; a control unit which is connected to the data transfer control unit via a serial bus; and a local memory which is connected to the control unit via a parallel bus, wherein the control unit decides to assign, from a cache segment of either the cache memory or the local memory, a storage area which stores the data on the basis of a CPU operating rate and a path utilization of the parallel bus connected to the cache memory.
摘要翻译：提供了一种存储控制器及其控制方法，如果将本地存储器的存储区域的一部分用作高速缓存存储器，则能够访问与本地存储器相连的并行总线的访问冲突以避免。一种在主机系统和存储装置之间执行数据控制的存储控制器，包括：数据传输控制单元，其执行基于来自主机系统的读/写请求传送数据的控制; 高速缓冲存储器，其通过并行总线连接到数据传送控制单元; 控制单元，经由串行总线连接到数据传送控制单元; 以及经由并行总线连接到所述控制单元的本地存储器，其中，所述控制单元决定从所述高速缓冲存储器或所述本地存储器的高速缓存段中分配存储所述数据的存储区域，所述存储区域基于 CPU运行速率和连接到缓存的并行总线的路径利用率。

2. 发明授权

US08370578B2 Storage controller and method of controlling storage controller 有权
标题翻译：存储控制器和控制存储控制器的方法
公开(公告)号：US08370578B2
公开(公告)日：2013-02-05
申请号：US13119292
申请日：2011-03-03
申请人： Yoshihiro Yoshii , Mitsuru Inoue , Kentaro Shimada , Sadahiro Sugimoto
发明人： Yoshihiro Yoshii , Mitsuru Inoue , Kentaro Shimada , Sadahiro Sugimoto
IPC分类号： G06F12/00
CPC分类号： G06F12/0871 , G06F12/0868
摘要： Provided is a storage controller and method of controlling same which, if part of a storage area of a local memory is used as cache memory, enable an access conflict for access to a parallel bus connected to the local memory to be avoided.A storage controller which exercises control of data between a host system and a storage apparatus, comprising a data transfer control unit which exercises control to transfer the data on the basis of a read/write request from the host system; a cache memory which is connected to the data transfer control unit via a parallel bus; a control unit which is connected to the data transfer control unit via a serial bus; and a local memory which is connected to the control unit via a parallel bus, wherein the control unit decides to assign, from a cache segment of either the cache memory or the local memory, a storage area which stores the data on the basis of a CPU operating rate and a path utilization of the parallel bus connected to the cache memory.
摘要翻译：提供了一种存储控制器及其控制方法，如果将本地存储器的存储区域的一部分用作高速缓存存储器，则能够访问与本地存储器相连的并行总线的访问冲突以避免。一种在主机系统和存储装置之间执行数据控制的存储控制器，包括：数据传输控制单元，其执行基于来自主机系统的读/写请求传送数据的控制; 高速缓冲存储器，其通过并行总线连接到数据传送控制单元; 控制单元，经由串行总线连接到数据传送控制单元; 以及经由并行总线连接到所述控制单元的本地存储器，其中，所述控制单元决定从所述高速缓冲存储器或所述本地存储器的高速缓存段中分配存储所述数据的存储区域，所述存储区域基于 CPU运行速率和连接到缓存的并行总线的路径利用率。

3. 发明授权

US08341348B2 Computer system and load equalization control method for the same where cache memory is allocated to controllers 有权
标题翻译：同样的计算机系统和负载均衡控制方法，其中缓存存储器被分配给控制器
公开(公告)号：US08341348B2
公开(公告)日：2012-12-25
申请号：US12665080
申请日：2009-11-19
申请人： Yoshihiro Yoshii , Shintaro Kudo , Kazuyoshi Serizawa , Masayuki Yamamoto , Sadahiro Sugimoto
发明人： Yoshihiro Yoshii , Shintaro Kudo , Kazuyoshi Serizawa , Masayuki Yamamoto , Sadahiro Sugimoto
IPC分类号： G06F13/00
CPC分类号： G06F3/0631 , G06F3/0605 , G06F3/0613 , G06F3/067
摘要： A computer system having a plurality of controllers for data input/output control is provided, wherein even if a control authority of a processor is transferred to another processor and the computer system migrates control information necessary for a controller to execute data input/output processing, from a shared memory to a local memory for the relevant controller, the computer system prevents the occurrence of unbalanced allocation of a control function necessary for data input/output control between the plurality of controllers; and a load equalization method for such a computer system is also provided.
摘要翻译：提供一种具有用于数据输入/输出控制的多个控制器的计算机系统，其中即使处理器的控制权限被传送到另一处理器，并且计算机系统迁移控制器执行数据输入/输出处理所需的控制信息，从共享存储器到相关控制器的本地存储器，计算机系统防止在多个控制器之间数据输入/输出控制所需的控制功能的不平衡分配的发生; 并且还提供了一种用于这种计算机系统的负载均衡方法。

4. 发明申请

US20110191547A1 COMPUTER SYSTEM AND LOAD EQUALIZATION CONTROL METHOD FOR THE SAME 有权
标题翻译：计算机系统和负载均衡控制方法
公开(公告)号：US20110191547A1
公开(公告)日：2011-08-04
申请号：US12665080
申请日：2009-11-19
申请人： Yoshihiro Yoshii , Shintaro Kudo , Kazuyoshi Serizawa , Masayuki Yamamoto , Sadahiro Sugimoto
发明人： Yoshihiro Yoshii , Shintaro Kudo , Kazuyoshi Serizawa , Masayuki Yamamoto , Sadahiro Sugimoto
IPC分类号： G06F12/00
CPC分类号： G06F3/0631 , G06F3/0605 , G06F3/0613 , G06F3/067
摘要： A computer system having a plurality of controllers for data input/output control is provided, wherein even if a control authority of a processor is transferred to another processor and the computer system migrates control information necessary for a controller to execute data input/output processing, from a shared memory to a local memory for the relevant controller, the computer system prevents the occurrence of unbalanced allocation of a control function necessary for data input/output control between the plurality of controllers; and a load equalization method for such a computer system is also provided.
摘要翻译：提供一种具有用于数据输入/输出控制的多个控制器的计算机系统，其中即使处理器的控制权限被传送到另一处理器，并且计算机系统迁移控制器执行数据输入/输出处理所需的控制信息，从共享存储器到相关控制器的本地存储器，计算机系统防止在多个控制器之间数据输入/输出控制所需的控制功能的不平衡分配的发生; 并且还提供了一种用于这种计算机系统的负载均衡方法。

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