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    • 1. 发明申请
    • STORAGE CONTROLLER AND METHOD OF CONTROLLING STORAGE CONTROLLER
    • 存储控制器及控制存储控制器的方法
    • US20120226861A1
    • 2012-09-06
    • US13119292
    • 2011-03-03
    • Yoshihiro YoshiiMitsuru InoueKentaro ShimadaSadahiro Sugimoto
    • Yoshihiro YoshiiMitsuru InoueKentaro ShimadaSadahiro Sugimoto
    • G06F12/08
    • G06F12/0871G06F12/0868
    • Provided is a storage controller and method of controlling same which, if part of a storage area of a local memory is used as cache memory, enable an access conflict for access to a parallel bus connected to the local memory to be avoided.A storage controller which exercises control of data between a host system and a storage apparatus, comprising a data transfer control unit which exercises control to transfer the data on the basis of a read/write request from the host system; a cache memory which is connected to the data transfer control unit via a parallel bus; a control unit which is connected to the data transfer control unit via a serial bus; and a local memory which is connected to the control unit via a parallel bus, wherein the control unit decides to assign, from a cache segment of either the cache memory or the local memory, a storage area which stores the data on the basis of a CPU operating rate and a path utilization of the parallel bus connected to the cache memory.
    • 提供了一种存储控制器及其控制方法,如果将本地存储器的存储区域的一部分用作高速缓存存储器,则能够访问与本地存储器相连的并行总线的访问冲突以避免。 一种在主机系统和存储装置之间执行数据控制的存储控制器,包括:数据传输控制单元,其执行基于来自主机系统的读/写请求传送数据的控制; 高速缓冲存储器,其通过并行总线连接到数据传送控制单元; 控制单元,经由串行总线连接到数据传送控制单元; 以及经由并行总线连接到所述控制单元的本地存储器,其中,所述控制单元决定从所述高速缓冲存储器或所述本地存储器的高速缓存段中分配存储所述数据的存储区域,所述存储区域基于 CPU运行速率和连接到缓存的并行总线的路径利用率。
    • 2. 发明授权
    • Storage controller and method of controlling storage controller
    • 存储控制器和控制存储控制器的方法
    • US08370578B2
    • 2013-02-05
    • US13119292
    • 2011-03-03
    • Yoshihiro YoshiiMitsuru InoueKentaro ShimadaSadahiro Sugimoto
    • Yoshihiro YoshiiMitsuru InoueKentaro ShimadaSadahiro Sugimoto
    • G06F12/00
    • G06F12/0871G06F12/0868
    • Provided is a storage controller and method of controlling same which, if part of a storage area of a local memory is used as cache memory, enable an access conflict for access to a parallel bus connected to the local memory to be avoided.A storage controller which exercises control of data between a host system and a storage apparatus, comprising a data transfer control unit which exercises control to transfer the data on the basis of a read/write request from the host system; a cache memory which is connected to the data transfer control unit via a parallel bus; a control unit which is connected to the data transfer control unit via a serial bus; and a local memory which is connected to the control unit via a parallel bus, wherein the control unit decides to assign, from a cache segment of either the cache memory or the local memory, a storage area which stores the data on the basis of a CPU operating rate and a path utilization of the parallel bus connected to the cache memory.
    • 提供了一种存储控制器及其控制方法,如果将本地存储器的存储区域的一部分用作高速缓存存储器,则能够访问与本地存储器相连的并行总线的访问冲突以避免。 一种在主机系统和存储装置之间执行数据控制的存储控制器,包括:数据传输控制单元,其执行基于来自主机系统的读/写请求传送数据的控制; 高速缓冲存储器,其通过并行总线连接到数据传送控制单元; 控制单元,经由串行总线连接到数据传送控制单元; 以及经由并行总线连接到所述控制单元的本地存储器,其中,所述控制单元决定从所述高速缓冲存储器或所述本地存储器的高速缓存段中分配存储所述数据的存储区域,所述存储区域基于 CPU运行速率和连接到缓存的并行总线的路径利用率。
    • 5. 发明授权
    • Storage device, and data path failover method of internal network of storage controller
    • 存储设备和存储控制器内部网络的数据路径故障转移方法
    • US08082466B2
    • 2011-12-20
    • US12338173
    • 2008-12-18
    • Katsuya TanakaKentaro Shimada
    • Katsuya TanakaKentaro Shimada
    • G06F11/00
    • G06F11/201
    • A storage device in which the MR-IOV is applied to an internal network of a storage controller. Data path failover can be executed in the storage device. The internal network of the storage controller is configured to enable the access of a virtual function (VF) “VF 0:0, 1” of each endpoint device (ED0-ED2) from a root port RP0. Likewise, “VF 1:0, 1” of each endpoint device can be accessed from a root port RP1. In a first data path from the RP0 to ED0 in a normal state, “VF 0:0, 1” and “MVF 0, 0” are connected by VF mapping. When a failure occurs on the first data path, the MR-PCIM executes the VF migration, whereby in the second data path from the RP1 to ED0, “VF 1:0, 1” and “MVF 0, 0” are connected by VF mapping. As a result, failover to the second data path is realized.
    • 将MR-IOV应用于存储控制器的内部网络的存储装置。 可以在存储设备中执行数据路径故障切换。 存储控制器的内部网络被配置为使得能够从根端口RP0访问每个端点设备(ED0-ED2)的虚拟功能(VF)“VF 0:0,1”。 同样地,可以从根端口RP1访问每个端点设备的“VF 1:0,1”。 在正常状态下从RP0到ED0的第一条数据路径中,通过VF映射连接“VF 0:0,1”和“MVF 0,0”。 当第一条数据路径出现故障时,MR-PCIM执行VF迁移,在RP1至ED0的第二条数据通路中,VF(VF1:0,1)和“MVF 0,0” 映射。 结果,实现到第二数据路径的故障切换。
    • 6. 发明授权
    • Storage systems and methods of controlling cache memory of storage systems
    • 控制存储系统缓存的存储系统和方法
    • US07814270B2
    • 2010-10-12
    • US11812112
    • 2007-06-15
    • Kentaro Shimada
    • Kentaro Shimada
    • G06F12/08
    • G06F12/0866
    • A storage system is arranged to speed up the operation and easily duplicate data without the capacity of the cache memory being so large even if lots of host computers are connected with the storage system. This storage system includes channel adapters, disk drives, disk adapters, and network switches. Further, the front side cache memories connected with the channel adapters and the back side cache memories connected with the disk adapters are provided as two layered cache system. When a request for writing data is given to the storage system by the host computer, the data is written in both the front side cache memory and the back side cache memory. The write data is duplicated by placing the write data in one of the front side cache memories and one of the back side cache memories or two of the back side cache memories.
    • 存储系统被设置为加速操作并且容易地复制数据,而没有高速缓存存储器的容量如此大,即使许多主机与存储系统连接。 该存储系统包括通道适配器,磁盘驱动器,磁盘适配器和网络交换机。 此外,与通道适配器连接的前侧缓存存储器和与盘适配器连接的后侧高速缓存存储器被提供为两层缓存系统。 当由主机向存储系统提供写入数据的请求时,数据被写入前侧缓存存储器和后端缓存存储器中。 通过将写入数据放置在前端缓存存储器之一和背面缓存存储器中的一个或背面缓存存储器中的两个之间来复制写入数据。