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1. 发明授权

US07301178B2 Pressed-contact type semiconductor device 失效
标题翻译：压接式半导体器件
公开(公告)号：US07301178B2
公开(公告)日：2007-11-27
申请号：US11212602
申请日：2005-08-29
申请人： Yoshihiro Yamaguchi , Kenji Oota
发明人： Yoshihiro Yamaguchi , Kenji Oota
IPC分类号： H01L29/74
CPC分类号： H01L29/0661 , H01L24/72 , H01L29/0615 , H01L29/0657 , H01L29/32 , H01L29/74 , H01L2924/0102 , H01L2924/1301 , H01L2924/00
摘要： A P++-type first diffusion layer is formed by diffusing P-type impurities on a front side of an N−-type semiconductor substrate, and an N-type fourth diffusion layer which is shallower than the first diffusion layer is formed by diffusing N-type impurities on the front side, and a P-type second diffusion layer is locally formed in a ring-shape so as to be exposed on the lateral side by diffusing P-type impurities on the back side, and P-type impurities are diffused on the back side of the substrate and a P+-type third diffusion layer is locally formed so as to be distributed inward from the second diffusion layer and not to be exposed to the lateral side, and the P-type second diffusion layer and the P+-type third diffusion layer are formed in the two-stage structure, thereby various characteristics can be improved.
摘要翻译： AP ++类型的第一扩散层是通过在N +型半导体衬底的正面扩散P型杂质形成的，N型第四扩散层通过在前侧扩散N型杂质而形成比第一扩散层浅的层，并且P型第二扩散层局部形成为环状，以便通过扩散P而暴露在侧面型杂质，P型杂质扩散到基板的背面，局部地形成P +型第三扩散层，以从第二层向内分布扩散层并且不暴露于侧面，并且P型第二扩散层和P + +型第三扩散层形成在两级结构中，因此可以有各种特性改进。

2. 发明申请

US20060043413A1 Pressed-contact type semiconductor device 失效
公开(公告)号：US20060043413A1
公开(公告)日：2006-03-02
申请号：US11212602
申请日：2005-08-29
申请人： Yoshihiro Yamaguchi , Kenji Oota
发明人： Yoshihiro Yamaguchi , Kenji Oota
IPC分类号： H01L29/74
CPC分类号： H01L29/0661 , H01L24/72 , H01L29/0615 , H01L29/0657 , H01L29/32 , H01L29/74 , H01L2924/0102 , H01L2924/1301 , H01L2924/00
摘要： A P++-type first diffusion layer is formed by diffusing P-type impurities on a front side of an N−-type semiconductor substrate, and an N-type fourth diffusion layer which is shallower than the first diffusion layer is formed by diffusing N-type impurities on the front side, and a P-type second diffusion layer is locally formed in a ring-shape so as to be exposed on the lateral side by diffusing P-type impurities on the back side, and P-type impurities are diffused on the back side of the substrate and a P+-type third diffusion layer is locally formed so as to be distributed inward from the second diffusion layer and not to be exposed to the lateral side, and the P-type second diffusion layer and the P+-type third diffusion layer are formed in the two-stage structure, thereby various characteristics can be improved.

3. 发明授权

US06943382B2 Pressed-contact type semiconductor device 失效
标题翻译：压接式半导体器件
公开(公告)号：US06943382B2
公开(公告)日：2005-09-13
申请号：US10648232
申请日：2003-08-27
申请人： Yoshihiro Yamaguchi , Kenji Oota
发明人： Yoshihiro Yamaguchi , Kenji Oota
IPC分类号： H01L29/744 , H01L21/322 , H01L23/48 , H01L29/06 , H01L29/74
CPC分类号： H01L29/0661 , H01L24/72 , H01L29/0615 , H01L29/0657 , H01L29/32 , H01L29/74 , H01L2924/0102 , H01L2924/1301 , H01L2924/00
摘要： A P++-type first diffusion layer is formed by diffusing P-type impurities on a front side of an N−-type semiconductor substrate, and an N-type fourth diffusion layer which is shallower than the first diffusion layer is formed by diffusing N-type impurities on the front side, and a P-type second diffusion layer is locally formed in a ring-shape so as to be exposed on the lateral side by diffusing P-type impurities on the back side, and P-type impurities are diffused on the back side of the substrate and a P+-type third diffusion layer is locally formed so as to be distributed inward from the second diffusion layer and not to be exposed to the lateral side, and the P-type second diffusion layer and the P+-type third diffusion layer are formed in the two-stage structure, thereby various characteristics can be improved.
摘要翻译： AP ++类型的第一扩散层是通过在N +型半导体衬底的正面扩散P型杂质形成的，N型第四扩散层通过在前侧扩散N型杂质而形成比第一扩散层浅的层，并且P型第二扩散层局部形成为环状，以便通过扩散P而暴露在侧面型杂质，P型杂质扩散到基板的背面，局部地形成P +型第三扩散层，以从第二层向内分布扩散层并且不暴露于侧面，并且P型第二扩散层和P + +型第三扩散层形成在两级结构中，因此可以有各种特性改进。

4. 发明授权

US07307289B2 Pressed-contact type semiconductor device 失效
公开(公告)号：US07307289B2
公开(公告)日：2007-12-11
申请号：US11212562
申请日：2005-08-29
申请人： Yoshihiro Yamaguchi , Kenji Oota
发明人： Yoshihiro Yamaguchi , Kenji Oota
IPC分类号： H01L29/74
CPC分类号： H01L29/0661 , H01L24/72 , H01L29/0615 , H01L29/0657 , H01L29/32 , H01L29/74 , H01L2924/0102 , H01L2924/1301 , H01L2924/00
摘要： A P++-type first diffusion layer is formed by diffusing P-type impurities on a front side of an N−-type semiconductor substrate, and an N-type fourth diffusion layer which is shallower than the first diffusion layer is formed by diffusing N-type impurities on the front side, and a P-type second diffusion layer is locally formed in a ring-shape so as to be exposed on the lateral side by diffusing P-type impurities on the back side, and P-type impurities are diffused on the back side of the substrate and a P+-type third diffusion layer is locally formed so as to be distributed inward from the second diffusion layer and not to be exposed to the lateral side, and the P-type second diffusion layer and the P+-type third diffusion layer are formed in the two-stage structure, thereby various characteristics can be improved.

5. 发明授权

US07244969B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US07244969B2
公开(公告)日：2007-07-17
申请号：US11194593
申请日：2005-08-02
申请人： Kenji Oota , Yoshihiro Yamaguchi , Hiroshi Yamaguchi
发明人： Kenji Oota , Yoshihiro Yamaguchi , Hiroshi Yamaguchi
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L29/0661 , H01L29/0619 , H01L29/0834 , H01L29/74
摘要： A power semiconductor device comprises a semiconductor substrate, a gate electrode region (control electrode region), a cathode electrode region (first main electrode region), an anode electrode region (second main electrode region) and a guard ring. The semiconductor substrate has a side surface portion having a vertical portion formed substantially vertical to a main surface and a mesa portion connected to the vertical portion in a cross section. The gate electrode region is formed in a first main surface of the semiconductor substrate. The cathode electrode region is formed in part of a surface of the gate electrode region. The anode electrode region is formed in a second main surface of the semiconductor substrate. The guard ring is formed in the second main surface of the semiconductor substrate and annularly surrounds the anode electrode region. With this constitution provided is a power semiconductor device which makes the impurity diffusion length of the anode electrode region shallower in order to ensure reduction in recovery loss.
摘要翻译：功率半导体器件包括半导体衬底，栅电极区域（控制电极区域），阴极电极区域（第一主电极区域），阳极电极区域（第二主电极区域）和保护环。半导体衬底具有侧表面部分，该侧表面部分具有基本上垂直于主表面的垂直部分和在横截面中连接到垂直部分的台面部分。栅电极区域形成在半导体衬底的第一主表面中。阴极电极区域形成在栅电极区域的一部分表面。阳极电极区域形成在半导体衬底的第二主表面中。保护环形成在半导体衬底的第二主表面中并且环形地围绕阳极电极区域。通过这样构成，为了确保降低回收损失，能够使阳极电极区域的杂质扩散长度变浅的功率半导体装置。

6. 发明申请

US20060038253A1 Pressed-contact type semiconductor device 失效
标题翻译：压接式半导体器件
公开(公告)号：US20060038253A1
公开(公告)日：2006-02-23
申请号：US11212562
申请日：2005-08-29
申请人： Yoshihiro Yamaguchi , Kenji Oota
发明人： Yoshihiro Yamaguchi , Kenji Oota
IPC分类号： H01L31/105
CPC分类号： H01L29/0661 , H01L24/72 , H01L29/0615 , H01L29/0657 , H01L29/32 , H01L29/74 , H01L2924/0102 , H01L2924/1301 , H01L2924/00
摘要： A P++-type first diffusion layer is formed by diffusing P-type impurities on a front side of an N−-type semiconductor substrate, and an N-type fourth diffusion layer which is shallower than the first diffusion layer is formed by diffusing N-type impurities on the front side, and a P-type second diffusion layer is locally formed in a ring-shape so as to be exposed on the lateral side by diffusing P-type impurities on the back side, and P-type impurities are diffused on the back side of the substrate and a P+-type third diffusion layer is locally formed so as to be distributed inward from the second diffusion layer and not to be exposed to the lateral side, and the P-type second diffusion layer and the P+-type third diffusion layer are formed in the two-stage structure, thereby various characteristics can be improved.
摘要翻译： AP ++类型的第一扩散层是通过在N +型半导体衬底的正面扩散P型杂质形成的，N型第四扩散层通过在前侧扩散N型杂质而形成比第一扩散层浅的层，并且P型第二扩散层局部形成为环状，以便通过扩散P而暴露在侧面型杂质，P型杂质扩散到基板的背面，局部地形成P +型第三扩散层，以从第二层向内分布扩散层并且不暴露于侧面，并且P型第二扩散层和P + +型第三扩散层形成在两级结构中，因此可以有各种特性改进。

7. 发明申请

US20060151805A1 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US20060151805A1
公开(公告)日：2006-07-13
申请号：US11194593
申请日：2005-08-02
申请人： Kenji Oota , Yoshihiro Yamaguchi , Hiroshi Yamaguchi
发明人： Kenji Oota , Yoshihiro Yamaguchi , Hiroshi Yamaguchi
IPC分类号： H01L29/45 , H01L29/76
CPC分类号： H01L29/0661 , H01L29/0619 , H01L29/0834 , H01L29/74
摘要： A power semiconductor device comprises a semiconductor substrate, a gate electrode region (control electrode region), a cathode electrode region (first main electrode region), an anode electrode region (second main electrode region) and a guard ring. The semiconductor substrate has a side surface portion having a vertical portion formed substantially vertical to a main surface and a mesa portion connected to the vertical portion in a cross section. The gate electrode region is formed in a first main surface of the semiconductor substrate. The cathode electrode region is formed in part of a surface of the gate electrode region. The anode electrode region is formed in a second main surface of the semiconductor substrate. The guard ring is formed in the second main surface of the semiconductor substrate and annularly surrounds the anode electrode region. With this constitution provided is a power semiconductor device which makes the impurity diffusion length of the anode electrode region shallower in order to ensure reduction in recovery loss.
摘要翻译：功率半导体器件包括半导体衬底，栅电极区域（控制电极区域），阴极电极区域（第一主电极区域），阳极电极区域（第二主电极区域）和保护环。半导体衬底具有侧表面部分，该侧表面部分具有基本上垂直于主表面的垂直部分和在横截面中连接到垂直部分的台面部分。栅电极区域形成在半导体衬底的第一主表面中。阴极电极区域形成在栅电极区域的一部分表面。阳极电极区域形成在半导体衬底的第二主表面中。保护环形成在半导体衬底的第二主表面中并且环形地围绕阳极电极区域。通过这样构成，为了确保降低回收损失，能够使阳极电极区域的杂质扩散长度变浅的功率半导体装置。

8. 发明申请

US20090286054A1 Decorative Sheet 审中-公开
标题翻译：装饰板
公开(公告)号：US20090286054A1
公开(公告)日：2009-11-19
申请号：US12440760
申请日：2007-09-26
申请人： Yoshiyuki Meiki , Hiroyuki Atake , Kenji Oota
发明人： Yoshiyuki Meiki , Hiroyuki Atake , Kenji Oota
IPC分类号： B32B3/10
CPC分类号： B29C45/14827 , B32B7/12 , B32B15/09 , B32B15/20 , B32B27/08 , B32B27/20 , B32B27/36 , B32B2255/10 , B32B2255/26 , B32B2255/28 , B32B2264/025 , B32B2264/10 , B32B2264/102 , B32B2264/104 , B32B2307/4026 , B32B2307/414 , B32B2307/422 , B32B2307/51 , B32B2307/518 , B32B2307/702 , B32B2307/71 , B32B2457/00 , B32B2605/003 , B44C1/1729 , Y10T428/24843
摘要： Provided is a sheet for decoration which is excellent in an impact resistance in molding a surface form having a three-dimensional curved surface having a high deep-drawing degree and which has a good followability toward a molding surface of a metal die and is suited to decorated moldings. The above sheet for decoration comprises a peel layer, a picture layer and a heat adhesive resin layer which are laminated in order on the surface of a base film comprising a polyester film, wherein a dynamic elastic modulus of the above base film is 1.0×106 Pa or more at any temperature falling in a range of 190 to 240° C.
摘要翻译：本发明提供一种装饰用片材，其具有在具有高深拉深度的三维曲面的成型中具有优异的耐冲击性，并且对金属模具的成型面具有良好的追随性，并且适合于装饰造型。上述装饰用片材包括剥离层，图案层和热粘树脂层，其依次层压在包含聚酯膜的基膜的表面上，其中上述基膜的动态弹性模量为1.0×10 6 Pa 或更高的温度落在190-240℃的范围内。

9. 发明授权

US06640775B2 Air-fuel ratio control system for internal combustion engine 失效
公开(公告)号：US06640775B2
公开(公告)日：2003-11-04
申请号：US10042212
申请日：2002-01-11
申请人： Hiroyuki Itoyama , Hiroshi Iwano , Kensuke Osamura , Kenji Oota
发明人： Hiroyuki Itoyama , Hiroshi Iwano , Kensuke Osamura , Kenji Oota
IPC分类号： F02D4100
CPC分类号： F02D41/1497 , F02D21/08 , F02D35/0007 , F02D41/005 , F02D41/0072 , F02D2041/0017 , F02D2041/1418 , F02D2041/389 , F02D2200/0402 , F02D2200/0406 , F02D2200/0408 , F02D2200/1004 , F02D2200/703 , F02D2250/18 , F02M26/05 , F02M26/10 , Y02T10/47
摘要： An air-fuel ratio control system for an internal combustion engine is comprised of an engine condition detecting unit and a control unit. The control unit is arranged to calculate a target engine torque on the basis of an engine operating condition, to calculate a target EGR ratio, a target excess air ratio and a target intake air quantity on the basis of the engine operating condition and the target engine torque, to calculate a target equivalence ratio on the basis of the target EGR ratio and the target excess air ratio, to calculate a target injection quantity on the basis of the engine operating condition and the target equivalence ratio, and to control an air-fuel ratio by bringing a real intake air quantity to the target intake air quantity and by bringing a real fuel injection quantity to the target fuel injection quantity.

10. 发明授权

US07837918B2 Method of forming a coating layer on the surface of a molded product within a mold 失效
标题翻译：在模具内的模制品的表面上形成涂层的方法
公开(公告)号：US07837918B2
公开(公告)日：2010-11-23
申请号：US12285441
申请日：2008-10-06
申请人： Kenji Yonemochi , Yoshiaki Yamamoto , Kenji Oota , Toshio Arai , Etsuo Okahara , Kazuaki Kobayashi
发明人： Kenji Yonemochi , Yoshiaki Yamamoto , Kenji Oota , Toshio Arai , Etsuo Okahara , Kazuaki Kobayashi
IPC分类号： B29C33/10
CPC分类号： B29C45/2669 , B29C37/0028 , B29C45/0025 , B29C45/1679 , B29C45/661 , B29C45/681 , B29C45/73 , B29C45/7653 , B29C2045/1687 , B29C2945/76006 , B29C2945/76287 , B29C2945/76943 , B29K2101/10 , B29K2101/12
摘要： An in-mold coating method providing a mold having a specifically formed auxiliary cavity and an in-mold coating formation method which employs said mold, so that it is possible to prevent a coating material from leaking out of the mold, thereby shortening the molding formation cycle, and making it possible to manufacture a molded product having a stabilized quality. In addition, by using a mold having a specifically shaped sub-cavity, there is provided a still further in-mold coating formation method which can keep mold temperature at a relatively low value, cause the coating material to cure at a predetermined temperature and within a predetermined time period thereby shortening the molding formation cycle, improving the productivity, improving the physical properties of a coating layer, thus obtaining a good molded product.
摘要翻译：提供具有特定形成的辅助空腔的模具和采用所述模具的模内涂层形成方法的模内涂布方法，使得可以防止涂料从模具中泄漏出来，从而缩短模制形成循环，并且可以制造具有稳定质量的模制产品。此外，通过使用具有特定形状的子腔的模具，还提供了另外的模内涂层形成方法，其可以将模具温度保持在较低的值，使涂层材料在预定温度和内部固化从而缩短成型周期，提高生产率，提高涂层的物理性能，从而获得良好的模制品。

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