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    • 1. 发明申请
    • SEMICONDUCTOR MEMORY
    • 半导体存储器
    • US20120320665A1
    • 2012-12-20
    • US13422110
    • 2012-03-16
    • Yoshihiro UEDAKosuke HATSUDA
    • Yoshihiro UEDAKosuke HATSUDA
    • G11C11/00
    • G11C11/1673
    • A semiconductor memory includes a first memory cell including: a first resistance change element and a first select transistor. The semiconductor memory includes a second memory cell including: a second select transistor and a second resistance change element. The semiconductor memory includes a third memory cell including: a third select transistor and a third resistance change element, the third memory cell acting as a reference cell. The semiconductor memory includes a fourth memory cell including: a fourth resistance change element and a fourth select transistor, the fourth memory cell acting as a reference cell.
    • 半导体存储器包括:第一存储单元,包括:第一电阻变化元件和第一选择晶体管。 半导体存储器包括第二存储单元,其包括:第二选择晶体管和第二电阻变化元件。 半导体存储器包括第三存储单元,第三存储单元包括:第三选择晶体管和第三电阻变化元件,第三存储单元用作参考单元。 半导体存储器包括:第四存储单元,包括:第四电阻变化元件和第四选择晶体管,第四存储单元用作参考单元。
    • 3. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE
    • 半导体存储器件
    • US20090201710A1
    • 2009-08-13
    • US12367792
    • 2009-02-09
    • Yoshihiro UEDA
    • Yoshihiro UEDA
    • G11C5/02G11C7/06
    • G11C7/14G11C7/062G11C11/5614G11C11/5678G11C11/5685G11C13/0004G11C13/0007G11C13/0011G11C13/0023G11C13/004G11C13/0069G11C13/0097G11C2013/0054G11C2213/31G11C2213/71G11C2213/72
    • A semiconductor memory device comprises a plurality of cell arrays, each cell array including a plurality of mutually parallel word lines, a plurality of mutually parallel bit lines disposed to cross these word lines, and a plurality of cells connected to the intersections of these word lines and bit lines, respectively, one portion of the cell arrays forming a memory cell array that has the cells as memory cells, and another portion of the cell arrays forming a reference cell array that has the cells as reference cells. A cell selection circuit is operative to select from the memory cell array a memory cell whose data is to be read, and to select from the reference cell array a reference cell at a position corresponding to a position of the memory cell selected in the memory cell array. A sense amplifier circuit is operative to detect and compare a current or a voltage of the selected memory cell with a current or a voltage of the selected reference cell, and thereby read data of the memory cell.
    • 一种半导体存储器件包括多个单元阵列,每个单元阵列包括多个相互平行的字线,多个相互平行的位线布置成与这些字线交叉,以及多个单元,连接到这些字线的交点 和位线,分别形成具有作为存储单元的单元的存储单元阵列的单元阵列的一部分,以及形成具有单元作为参考单元的参考单元阵列的单元阵列的另一部分。 小区选择电路可操作以从存储单元阵列中选择要读取其数据的存储单元,并从参考单元阵列中选择与在存储单元中选择的存储单元的位置对应的位置处的参考单元 数组。 读出放大器电路用于检测并比较所选存储单元的电流或电压与所选参考单元的电流或电压,从而读取存储单元的数据。
    • 4. 发明申请
    • MAGNETORESISTIVE RANDOM ACCESS MEMORY
    • 磁力随机访问存储器
    • US20090190391A1
    • 2009-07-30
    • US12356722
    • 2009-01-21
    • Kiyotaro ITAGAKIYoshihiro UEDA
    • Kiyotaro ITAGAKIYoshihiro UEDA
    • G11C11/02G11C11/416G11C8/08
    • G11C11/1675G11C11/1673
    • A word line voltage is applied to a plurality of word lines. A read/write voltage is applied to a plurality of bit lines. The read/write voltage is applied to a plurality of source lines. A word line selector selects the word line and applies the word line voltage. A driver applies a predetermined voltage to the bit line and the source line, thereby supplying a current to the memory cell. A read circuit reads a first current having flowed through the memory cell, and determines data stored in the memory cell. When performing the read, the driver supplies a second current to second bit lines among other bit lines, which are adjacent to the first bit line through which the first current has flowed. The second current generates a magnetic field in a direction to suppress a write error in the memory cell from which data is to be read.
    • 字线电压被施加到多个字线。 读/写电压施加到多个位线。 读/写电压被施加到多条源极线。 字线选择器选择字线并施加字线电压。 驱动器将预定电压施加到位线和源极线,从而向存储器单元提供电流。 读取电路读取已经流过存储器单元的第一电流,并且确定存储在存储单元中的数据。 当执行读取时,驱动器向与第一电流流过的第一位线相邻的其它位线中的第二位线提供第二电流。 第二电流在抑制要从其读取数据的存储单元中的写入错误的方向上产生磁场。
    • 6. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH RESISTANCE CHANGE ELEMENT
    • 具有电阻变化元件的半导体存储器件
    • US20100208512A1
    • 2010-08-19
    • US12709256
    • 2010-02-19
    • Yoshihiro UEDA
    • Yoshihiro UEDA
    • G11C11/00
    • G11C17/12G11C13/0002G11C14/0081G11C14/009
    • A latch circuit is connected to a first common node, a first, second output node, and a first, second connection node. A first resistance change element is connected to the first connection node, and a second common node. A second resistance change element is connected to the second connection node, and the second common node. When a first data is stored, voltages of the first common node, second common node, and first output node are set at a first reference voltage, and a voltage of the second output node is set at a second reference voltage. When a second data is stored, voltages of the first common node, second common node, and second output node are set at the first reference voltage, and a voltage of the first output node is set at the second reference voltage.
    • 锁存电路连接到第一公共节点,第一,第二输出节点和第一,第二连接节点。 第一电阻变化元件连接到第一连接节点和第二公共节点。 第二电阻变化元件连接到第二连接节点和第二公共节点。 当存储第一数据时,将第一公共节点,第二公共节点和第一输出节点的电压设置为第一参考电压,并将第二输出节点的电压设置为第二参考电压。 当存储第二数据时,将第一公共节点,第二公共节点和第二输出节点的电压设置为第一参考电压,并且将第一输出节点的电压设置为第二参考电压。
    • 7. 发明申请
    • MAGNETORESISTIVE RANDOM ACCESS MEMORY
    • 磁力随机访问存储器
    • US20090010045A1
    • 2009-01-08
    • US12164410
    • 2008-06-30
    • Yoshihiro UEDA
    • Yoshihiro UEDA
    • G11C11/02
    • G11C11/15G11C11/1673
    • A MRAM includes a first magnetoresistive effect (MR) element that takes a low and high resistance states. A second MR element is fixed to a low or high resistance state. First and second MOSFETs are connected to the first and second MR elements, respectively. A sense amplifier amplifies a difference between values of current flowing through the first and second MOSFETs. A current circuit outputs reference current whose value lies between current flowing through the first MR element of the low and high resistance states. A third MOSFET has one end that receives the reference current and is connected to its own gate terminal. The gate terminal of the second MOSFET receives the same potential as the gate terminal of the third MOSFET. A first resistance element is connected to the others end of the third MOSFET and has the same resistance as the second magnetoresistive effect element.
    • MRAM包括采用低和高电阻状态的第一磁阻效应(MR)元件。 第二MR元件固定为低电阻或高电阻状态。 第一和第二MOSFET分别连接到第一和第二MR元件。 读出放大器放大流经第一和第二MOSFET的电流值之差。 电流电路输出其值位于流过低电阻状态和高电阻状态的第一MR元件的电流之间的参考电流。 第三个MOSFET的一端接收参考电流并连接到其自己的栅极端子。 第二MOSFET的栅极端子接收与第三MOSFET的栅极端子相同的电位。 第一电阻元件连接到第三MOSFET的另一端,并且具有与第二磁阻效应元件相同的电阻。
    • 8. 发明申请
    • SEMICONDUCTOR MEMORY HAVING RESISTANCE CHANGE ELEMENT
    • 具有电阻变化元件的半导体存储器
    • US20080043514A1
    • 2008-02-21
    • US11781443
    • 2007-07-23
    • Yoshihiro UEDA
    • Yoshihiro UEDA
    • G11C11/00
    • G11C7/02G11C7/18G11C11/1675G11C13/0004
    • A semiconductor memory according to examples of the present invention includes a word line extending in a first direction, first, second and third bit lines extending in a second direction, a first cell unit connected between the first and second bit lines, a second cell unit connected between the first and third bit lines, and a controller CNT which executes write to a first resistance change element under the condition that the word line is made active and potentials of the first and third bit lines are equalized, and which executes write to a second resistance change element under the condition that the word line is made active and potentials of the first and second bit lines are equalized.
    • 根据本发明的示例的半导体存储器包括在第一方向上延伸的字线,在第二方向上延伸的第一,第二和第三位线,连接在第一和第二位线之间的第一单元单元,第二单元单元 连接在第一和第三位线之间的控制器CNT,以及在使字线有效并且第一和第三位线的电位相等的条件下执行写入第一电阻变化元件的控制器CNT,并且执行写入到 第二电阻变化元件在使字线有效并且第一和第二位线的电位相等的条件下。
    • 10. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE INCLUDING A PLURALITY OF MEMORY CELL ARRAYS
    • 半导体存储器件,包括大量存储器单元阵列
    • US20100277972A1
    • 2010-11-04
    • US12769523
    • 2010-04-28
    • Yoshihiro UEDA
    • Yoshihiro UEDA
    • G11C11/00G11C7/06
    • G11C11/1673G11C11/1659
    • First and second memory cell arrays are adjacent in a first direction. First and second areas are positioned adjacent to one and the other side of the first memory array in a second direction. Third and fourth areas are positioned adjacent to one and the other side of the second memory array in a second direction. A sense amplifier is arranged in the first area and a current sink is arranged in the fourth area. The sense amplifier compares a read current which flows into the current sink via a memory cell in the first memory cell array and the second area from the sense amplifier with a reference current which flows into the current sink via the third area and a reference memory cell in the second memory cell array from the sense amplifier.
    • 第一和第二存储单元阵列在第一方向上相邻。 第一和第二区域在第二方向上与第一存储器阵列的一侧和另一侧相邻。 第三和第四区域在第二方向上与第二存储器阵列的一侧和另一侧相邻。 读出放大器布置在第一区域中,并且电流吸收器布置在第四区域中。 读出放大器经由第一存储单元阵列中的存储单元和来自读出放大器的第二区域经由第三区域和参考存储单元比较流入电流宿中的参考电流来流入流入电流宿的读取电流, 在来自读出放大器的第二存储单元阵列中。