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1. 发明授权

US5489860A Semiconductor circuit having improved layout pattern 失效
标题翻译：具有改进布局图案的半导体电路
公开(公告)号：US5489860A
公开(公告)日：1996-02-06
申请号：US138081
申请日：1993-10-20
申请人： Masaya Kitagawa , Shigeru Fujii
发明人： Masaya Kitagawa , Shigeru Fujii
IPC分类号： H01L27/118 , H01L25/00
CPC分类号： H01L27/11807
摘要： A semiconductor circuit includes a plurality of first power supply lines which are arranged parallel to each other, a plurality of second power supply lines which are arranged parallel to each other and supplying a power supply voltage different from that supplied by the first power supply lines, where the first and second power supply lines run parallel to each other in a first direction, a first cell made up of the same number of first p-channel transistors and first n-channel transistors which are respectively coupled to the first and second power supply lines, where the first p-channel transistors and the first n-channel transistors are alternately arranged in a second direction and have the same size, and a second cell made up of a different number of second p-channel transistors and second n-channel transistors which are respectively coupled to the first and second power supply lines. The second p-channel transistors and the second n-channel transistors are alternately arranged in the second direction, and the second p-channel transistors are electrically coupled in parallel, so that the second p-channel transistors have a predetermined driving capability.
摘要翻译：半导体电路包括彼此平行布置的多个第一电源线，多个第二电源线，彼此并联布置并提供与由第一电源线提供的电源电压不同的电源电压，其中第一和第二电源线在第一方向上彼此平行地延伸，由相同数量的第一p沟道晶体管和第一n沟道晶体管组成的第一单元，第一p沟道晶体管和第一n沟道晶体管分别耦合到第一和第二电源线，其中第一p沟道晶体管和第一n沟道晶体管沿第二方向交替布置并具有相同的尺寸，以及由不同数量的第二p沟道晶体管和第二n沟道晶体管构成的第二单元分别耦合到第一和第二电源线的晶体管。第二p沟道晶体管和第二n沟道晶体管沿第二方向交替布置，并且第二p沟道晶体管并联电耦合，使得第二p沟道晶体管具有预定的驱动能力。

2. 发明授权

US5581109A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5581109A
公开(公告)日：1996-12-03
申请号：US392159
申请日：1995-02-22
申请人： Kuniyuki Hayashi , Masaya Kitagawa , Tetsu Tanizawa
发明人： Kuniyuki Hayashi , Masaya Kitagawa , Tetsu Tanizawa
IPC分类号： H01L21/822 , H01L23/528 , H01L27/04 , H01L29/00
CPC分类号： H01L24/06 , H01L23/5286 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/4847 , H01L2224/49171 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/30105 , H01L2924/3011 , Y10S257/909
摘要： A semiconductor device includes a semiconductor chip, an I/O-cell circuit having a transistor-array part. The semiconductor device further includes a first group of bonding pads and a second group of bonding pads. The first group of bonding pads is connected with the I/O-cell circuit and is formed in a first pad-forming area arranged along an outer side of the transistor-array part in the I/O-cell circuit. And the second group of bonding pads is connected with the I/O-cell circuit and is formed in a second pad-forming area along an inner side of the transistor-array part in the I/O-cell circuit.
摘要翻译：半导体器件包括半导体芯片，具有晶体管阵列部分的I / O单元电路。半导体器件还包括第一组焊盘和第二组焊盘。第一组接合焊盘与I / O单元电路连接，并且形成在沿着I / O单元电路中的晶体管阵列部分的外侧布置的第一焊盘形成区域中。并且第二组接合焊盘与I / O单元电路连接，并且沿着I / O单元电路中的晶体管阵列部分的内侧形成在第二焊盘形成区域中。

3. 发明授权

US07206239B2 Semiconductor device and skew adjusting method 失效
标题翻译：半导体器件和偏斜调整方法
公开(公告)号：US07206239B2
公开(公告)日：2007-04-17
申请号：US11260199
申请日：2005-10-28
申请人： Kazuhiko Kikuchi , Masaya Kitagawa , Jun Masuko
发明人： Kazuhiko Kikuchi , Masaya Kitagawa , Jun Masuko
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C7/22 , G11C5/04 , G11C7/222 , G11C29/02 , G11C29/023 , G11C29/028
摘要： Function circuits composing one function macro are divided and mounted on plural chips, plural internal clock signals having different phases with one another are generated based on a clock signal to be a reference, a phase of a clock signal supplied to the function circuits within the chips is adjusted based on a result of a test operation performed by using a selected internal clock signal, a clock signal with an optimal phase is obtained from among the plural internal clock signals having the different phases with one another, and a skew generated by being divided into the plural chips is adjusted automatically to thereby realize a proper operation of the circuits as a whole.
摘要翻译：构成一个功能宏的功能电路被分割并安装在多个芯片上，基于作为参考的时钟信号产生彼此具有不同相位的多个内部时钟信号，提供给芯片内的功能电路的时钟信号的相位基于通过使用所选择的内部时钟信号进行的测试操作的结果进行调整，从具有彼此不同相位的多个内部时钟信号中获得具有最佳相位的时钟信号，并且由分割产生的偏斜自动调整多个芯片，从而实现电路整体的正常操作。

4. 发明申请

US20060215469A1 Semiconductor device and skew adjusting method 失效
标题翻译：半导体器件和偏斜调整方法
公开(公告)号：US20060215469A1
公开(公告)日：2006-09-28
申请号：US11260199
申请日：2005-10-28
申请人： Kazuhiko Kikuchi , Masaya Kitagawa , Jun Masuko
发明人： Kazuhiko Kikuchi , Masaya Kitagawa , Jun Masuko
IPC分类号： G11C29/00
CPC分类号： G11C7/22 , G11C5/04 , G11C7/222 , G11C29/02 , G11C29/023 , G11C29/028
摘要： Function circuits composing one function macro are divided and mounted on plural chips, plural internal clock signals having different phases with one another are generated based on a clock signal to be a reference, a phase of a clock signal supplied to the function circuits within the chips is adjusted based on a result of a test operation performed by using a selected internal clock signal, a clock signal with an optimal phase is obtained from among the plural internal clock signals having the different phases with one another, and a skew generated by being divided into the plural chips is adjusted automatically to thereby realize a proper operation of the circuits as a whole.
摘要翻译：构成一个功能宏的功能电路被分割并安装在多个芯片上，基于作为参考的时钟信号产生彼此具有不同相位的多个内部时钟信号，提供给芯片内的功能电路的时钟信号的相位基于通过使用所选择的内部时钟信号进行的测试操作的结果进行调整，从具有彼此不同相位的多个内部时钟信号中获得具有最佳相位的时钟信号，并且由分割产生的偏斜自动调整多个芯片，从而实现电路整体的正常操作。

5. 发明授权

US6065141A Self-diagnosable semiconductor memory device having a redundant circuit and semiconductor apparatus having the same in which the memory device cannot be accessed from outside the semiconductor apparatus 失效
标题翻译：具有冗余电路的自诊断半导体存储器件和具有这样的半导体装置的半导体装置，其中存储器件不能从半导体器件的外部访问
公开(公告)号：US6065141A
公开(公告)日：2000-05-16
申请号：US96261
申请日：1993-07-26
申请人： Masaya Kitagawa
发明人： Masaya Kitagawa
IPC分类号： G11C11/413 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/12 , G11C29/44 , G11C29/48 , H01L21/66 , H01L21/82 , H02H3/05
CPC分类号： G11C29/4401 , G11C2029/0401 , G11C2029/4402
摘要： An object of the present invention is that, in a semiconductor memory device having both a redundant circuit and a diagnostic circuit, a memory test for detecting positions of defective memory cells in order to replace the defective memory cells with the redundant circuit can be easily carried out by using the diagnostic circuit. A semiconductor memory device of the present invention includes a normal memory portion, a redundant circuit to replace defective memory cells of the normal memory portion by a units of a word line or a bit line, and a self-diagnostic circuit, and further, in order to realize the object, the device includes a defective cell position storage circuit for storing position information of each defective memory cell when the self-diagnostic circuit detects defective memory cells, and an output circuit for converting position information stored in the defective cell position storage circuit into serial data and outputting the position information.
摘要翻译：本发明的目的在于，在具有冗余电路和诊断电路的半导体存储器件中，可以容易地携带用于检测故障存储器单元的位置以便用冗余电路替换有缺陷的存储器单元的存储器测试通过使用诊断电路。本发明的半导体存储器件包括通常的存储器部分，用字线或位线的单元代替正常存储器部分的不良存储单元的冗余电路和自诊断电路，此外，为了实现该目的，该装置包括一缺陷单元位置存储电路，用于当该自诊断电路检测到有缺陷的存储单元时，存储每个不良存储单元的位置信息;以及输出电路，用于转换存储在该缺陷单元位置存储器电路转换为串行数据并输出位置信息。

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