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1. 发明授权

US06441935B1 Optical packet exchange system and optical switch 失效
公开(公告)号：US06441935B1
公开(公告)日：2002-08-27
申请号：US09210277
申请日：1998-12-11
申请人： Soichiro Araki , Yoshihiko Suemura , Akio Tajima , Seigo Takahashi , Yoshiharu Maeno , Naoya Henmi
发明人： Soichiro Araki , Yoshihiko Suemura , Akio Tajima , Seigo Takahashi , Yoshiharu Maeno , Naoya Henmi
IPC分类号： H04J1408
CPC分类号： H04Q11/0001 , H04L49/25 , H04L49/30 , H04L49/50 , H04Q2011/0024 , H04Q2011/0039 , H04Q2011/0045 , H04Q2011/005
摘要： An optical packet exchange apparatus and an optical switch in which search for a connection pattern between an input unit devoid of a packet to be transmitted and an output unit devoid of a packet to be received is reduced to enable fast switch control even in cases wherein the number of channels of the exchange apparatus is increased or network speed is higher. A plurality of input units, a plurality of output units and an optical switch are provided. Each input unit includes an input buffer unit, a parallel/serial conversion unit, an electrical/optical conversion unit, and a dummy packet insertion unit for sending a dummy packet if there is no packet to be transmitted. Each output unit includes an exchange counterpart contention resolution unit for controlling the exchange counterpart, an optical/electrical conversion unit, a serial/parallel conversion unit, and a packet eliminating unit. The exchange counterpart contention resolution unit controls the packet eliminating unit to eliminate a dummy packet.

2. 发明授权

US5812290A Optical switching unit and control method for same 失效
标题翻译：光开关单元及其控制方法相同
公开(公告)号：US5812290A
公开(公告)日：1998-09-22
申请号：US764484
申请日：1996-12-12
申请人： Yoshiharu Maeno , Yoshihiko Suemura , Naoya Henmi
发明人： Yoshiharu Maeno , Yoshihiko Suemura , Naoya Henmi
IPC分类号： H04B10/27 , H04B10/077 , H04B10/29 , H04Q11/00 , H04B10/12 , H04B10/24
CPC分类号： H04Q11/0062 , H04Q2011/0039 , H04Q2011/0043 , H04Q2011/0047 , H04Q2011/0081 , H04Q2011/0083
摘要： The present invention provides means by which a switch controller that manages lines directly notifies receivers of ineffectiveness of received data upon line disconnection instead of any transmitter indirectly notifying receivers; and according to the invention, an optical transmitter is provided within the optical switching unit, and a switch controller controls the optical transmitter within the optical switching unit and an optical switch having at its input ports one or more dummy ports capable of multicast-transmission. According to this control, upon line disconnection, receivers are connected to the optical transmitter within the optical switching unit that transmits control code in real time, thereby preventing receivers from receiving ineffective data and obviating superfluous signal lines and communication processes between the switch controller and transmitters.
摘要翻译：本发明提供了一种管理线路的开关控制器直接通知接收机线路断开时接收数据无效而不是任何发射机间接通知接收机的装置; 并且根据本发明，在光学开关单元内提供光发射器，并且开关控制器控制光开关单元内的光发射机，以及在其输入端口具有能够进行组播传输的一个或多个虚拟端口的光开关。根据该控制，在线路断开时，接收机连接到实际发送控制码的光交换单元内的光发射机，从而防止接收机收到无效数据，消除交换控制器与发射机之间的多余信号线和通信过程。

3. 发明授权

US06760552B1 Optical receiving circuit and optical communication device 失效
标题翻译：光接收电路和光通信设备
公开(公告)号：US06760552B1
公开(公告)日：2004-07-06
申请号：US09532420
申请日：2000-03-23
申请人： Akio Tajima , Hiroaki Takahashi , Soichiro Araki , Naoya Henmi , Yoshihiko Suemura , Yoshiharu Maeno , Seigo Takahashi
发明人： Akio Tajima , Hiroaki Takahashi , Soichiro Araki , Naoya Henmi , Yoshihiko Suemura , Yoshiharu Maeno , Seigo Takahashi
IPC分类号： H04B1006
CPC分类号： H04B10/6931
摘要： An optical receiving circuit 1 is composed of a preamplifier circuit 2, an output differential amplifier 3 and a mean value holding circuit 4. The optical receiving circuit 1 is connected to a photodetector 5 for receiving an input optical signal and outputting current. For the preamplifier circuit 2, a transimpedance type circuit may also be used. The preamplifier circuit 2 comprises a feedback resistor 21 and a resistor for detecting output voltage 22, the transimpedance gain is 55 dB &OHgr; and 3 dB bandwidth when the photodetector 5 the capacity of which is 0.2 pF is connected to its output is 8 GHz. The output differential amplifier 3 discriminates and regenerates data by regulating reference voltage Vref between the high level and the low level of the amplitude of an input signal. The mean value holding circuit 4 includes a sample-hold circuit 41 and capacity 42 for holding the mean value of voltage output from the preamplifier circuit 2. As a CR time constant based upon the capacity 42 and the resistor for detection 22 is 1 ns., the mean value level of a received signal can be detected in approximately one byte of the data of 10 Gb/s. The sample-hold circuit 41 samples the detected mean value level according to a sampling pulse from an external device and holds it. The output of the sample-hold circuit 41 is used for the reference voltage of the differential amplifier 3.
摘要翻译：光接收电路1由前置放大电路2，输出差分放大器3和平均值保持电路4组成。光接收电路1连接到用于接收输入光信号并输出电流的光电检测器5。对于前置放大器电路2，也可以使用跨阻型电路。前置放大器电路2包括反馈电阻器21和用于检测输出电压22的电阻器，当其电容为0.2pF的光电检测器5连接到其输出端时，跨阻增益为55dBΩ和3dB带宽为8GHz。输出差分放大器3通过调节输入信号的幅度的高电平和低电平之间的参考电压Vref来识别和再生数据。平均值保持电路4包括采样保持电路41和用于保持从前置放大器电路2输出的电压的平均值的电容42.由于基于电容42和检测电阻22的CR时间常数为1ns。可以在10Gb / s的数据的大约一个字节中检测接收信号的平均值电平。采样保持电路41根据来自外部设备的采样脉冲对检测到的平均值电平进行采样并保持。采样保持电路41的输出用于差分放大器3的参考电压。

4. 发明授权

US06429955B1 Optical network 失效
标题翻译：光网络
公开(公告)号：US06429955B1
公开(公告)日：2002-08-06
申请号：US09218102
申请日：1998-12-22
申请人： Yoshihiko Suemura , Soichiro Araki , Akio Tajima , Seigo Takahashi , Yoshiharu Maeno , Naoya Henmi
发明人： Yoshihiko Suemura , Soichiro Araki , Akio Tajima , Seigo Takahashi , Yoshiharu Maeno , Naoya Henmi
IPC分类号： H04J1402
CPC分类号： H04Q11/0001
摘要： Disclosed is an optical network which has: wavelength tunable optical transmitters of number MN, where N is an integer of two or more, each of which outputs an optical signal with arbitrary one of M wavelengths &lgr;1, &lgr;2, . . . , &lgr;M, where M is an integer of two or more, that are different from one another; a MN×N optical switch whose input ports are connected to the respective wavelength tunable optical transmitters of number MN, and which allows optical signals input to different input ports to be output form its same output port; 1×M optical wavelength demultiplexers of number N which output demultiplexing optical signal with wavelengths &lgr;1, &lgr;2, . . . , &lgr;M input from output ports of the MN×N optical switch into each wavelength; and optical receivers of number MN which receive optical signals input from the 1×M optical wavelength demultiplexers of number N.
摘要翻译：公开了一种光网络，其具有：号MN的波长可调光发射机，其中N是两个或更多个的整数，每个都输出具有M个波长lambd1，lambd2的任意一个的光信号。。。，lambdM，其中M是两个或更多个彼此不同的整数; 一个MNxN光开关，其输入端口连接到MN号的各波长可调光发射机，并允许输入到不同输入端口的光信号从其相同的输出端口输出; 数字N的1xM光学波长解复用器，其输出具有波长lambd1，lambd2的解复用光信号。。。，将MNxN光开关的输出端口的lambdM输入到每个波长; 数字MN的光接收器接收从数字N的1MM光波分复用器输入的光信号。

5. 发明授权

US06957018B2 Optical packet exchange system and optical switch 失效
标题翻译：光分组交换系统和光开关
公开(公告)号：US06957018B2
公开(公告)日：2005-10-18
申请号：US10151789
申请日：2002-05-21
申请人： Soichiro Araki , Yoshihiko Suemura , Akio Tajima , Seigo Takahashi , Yoshiharu Maeno , Naoya Henmi
发明人： Soichiro Araki , Yoshihiko Suemura , Akio Tajima , Seigo Takahashi , Yoshiharu Maeno , Naoya Henmi
IPC分类号： H04B10/27 , H04B10/00 , H04L12/931 , H04Q3/00 , H04Q3/52 , H04Q11/00 , H04J14/00
CPC分类号： H04Q11/0001 , H04L49/25 , H04L49/30 , H04L49/50 , H04Q2011/0024 , H04Q2011/0039 , H04Q2011/0045 , H04Q2011/005
摘要： An optical packet exchange apparatus and an optical switch in which search for a connection pattern between an input unit devoid of a packet to be transmitted and an output unit devoid of a packet to be received is reduced to enable fast switch control even in cases wherein the number of channels of the exchange apparatus is increased or network speed is higher. A plurality of input units, a plurality of output units and an optical switch are provided. Each input unit includes an input buffer unit, a parallel/serial conversion unit, an electrical/optical conversion unit, and a dummy packet insertion unit for sending a dummy packet if there is no packet to be transmitted. Each output unit includes an exchange counterpart contention resolution unit for controlling the exchange counterpart, an optical/electrical conversion unit, a serial/parallel conversion unit, and a packet eliminating unit. The exchange counterpart contention resolution unit controls the packet eliminating unit to eliminate a dummy packet.
摘要翻译：一种光分组交换装置和光开关，其中，在没有要发送的分组的输入单元和没有要接收的分组的输出单元之间的连接模式的搜索被减少以便能够快速切换控制，即使在交换装置的信道数量增加或网络速度较高。提供多个输入单元，多个输出单元和光学开关。每个输入单元包括输入缓冲器单元，并行/串行转换单元，电/光转换单元和用于在不存在要发送的分组的情况下发送虚拟分组的虚拟分组插入单元。每个输出单元包括用于控制交换对方的交换对方争用解决单元，光/电转换单元，串行/并行转换单元和分组消除单元。交换对手争用解决单元控制分组消除单元以消除虚拟分组。

6. 发明授权

US06570687B2 Optical packet exchange system and optical switch 失效
公开(公告)号：US06570687B2
公开(公告)日：2003-05-27
申请号：US10123444
申请日：2002-04-16
申请人： Soichiro Araki , Yoshihiko Suemura , Akio Tajima , Seigo Takahashi , Yoshiharu Maeno , Naoya Henmi
发明人： Soichiro Araki , Yoshihiko Suemura , Akio Tajima , Seigo Takahashi , Yoshiharu Maeno , Naoya Henmi
IPC分类号： H04J1408
CPC分类号： H04Q11/0001 , H04L49/25 , H04L49/30 , H04L49/50 , H04Q2011/0024 , H04Q2011/0039 , H04Q2011/0045 , H04Q2011/005
摘要： An optical packet exchange apparatus and an optical switch in which search for a connection pattern between an input unit devoid of a packet to be transmitted and an output unit devoid of a packet to be received is reduced to enable fast switch control even in cases wherein the number of channels of the exchange apparatus is increased or network speed is higher. A plurality of input units, a plurality of output units and an optical switch are provided. Each input unit includes an input buffer unit, a parallel/serial conversion unit, an electrical/optical conversion unit, and a dummy packet insertion unit for sending a dummy packet if there is no packet to be transmitted. Each output unit includes an exchange counterpart contention resolution unit for controlling the exchange counterpart, an optical/electrical conversion unit, a serial/parallel conversion unit, and a packet eliminating unit. The exchange counterpart contention resolution unit controls the packet eliminating unit to eliminate a dummy packet.

7. 发明授权

US06373911B1 Bit synchronization circuit 有权
标题翻译：位同步电路
公开(公告)号：US06373911B1
公开(公告)日：2002-04-16
申请号：US09239090
申请日：1999-01-27
申请人： Akio Tajima , Yoshihiko Suemura , Soichiro Araki , Seigo Takahashi , Yoshiharu Maeno , Naoya Henmi
发明人： Akio Tajima , Yoshihiko Suemura , Soichiro Araki , Seigo Takahashi , Yoshiharu Maeno , Naoya Henmi
IPC分类号： H03D324
CPC分类号： H04L7/02 , H03L7/0812 , H04L7/0083 , H04L7/0337 , H04L7/0338 , H04L7/10
摘要： A bit synchronization circuit operates at high speed range as high as Gb/s or higher and can establish synchronization within 10 bits with rejecting jitter to permit accurate bit synchronization. The bit synchronization circuit thus generates a plurality of clocks having mutually different phases in synchronism with an input reference clock. A phase relationship between a plurality of clocks and an input data to be decided is discriminated by a phase comparator circuit. The clock having optimal phase relationship, namely clock having level transition timing having at a substantially center portion of mutually adjacent level transition timing of the input data, is determined by a phase determination circuit. An decision circuit and selector are provided for deciding input data at the level transition timing of the determined clock.
摘要翻译：位同步电路在高达Gb / s或更高的高速范围内工作，并且可以在10位内建立同步，同时抑制抖动以允许精确的位同步。因此，比特同步电路产生与输入参考时钟同步的具有相互不同相位的多个时钟。通过相位比较器电路鉴别多个时钟与待决定的输入数据之间的相位关系。具有最佳相位关系的时钟，即具有在输入数据的相互相邻电平转换定时的大致中心部分处的电平转换定时的时钟由相位确定电路确定。提供决定电路和选择器，用于在所确定的时钟的电平转换定时处决定输入数据。

8. 发明授权

US06445473B1 Optical switching apparatus using wavelength division multiplexing technology 失效
标题翻译：光开关器件采用波分复用技术
公开(公告)号：US06445473B1
公开(公告)日：2002-09-03
申请号：US09276671
申请日：1999-03-26
申请人： Yoshihiko Suemura , Naoya Henmi
发明人： Yoshihiko Suemura , Naoya Henmi
IPC分类号： H04B1000
CPC分类号： H04Q11/0005 , H04Q2011/0009 , H04Q2011/0011 , H04Q2011/0013 , H04Q2011/0016 , H04Q2011/0058 , H04Q2011/0075
摘要： To optimize the number of optical gate switches required by an optical switching apparatus which comprises an optical space switch and wavelength selectors, the following process as a preliminary process of introducing optical signals into the optical space switch, is carried out. In detail, the preliminary process is optically converting the optical signals in relation to the number of input ports of the optical space switch, by optically processing the optical signals. As the results, the number of processed optical signals responding to the input ports and the processed number of wavelengths of each processed optical signal is equal to each other, and thereby, the optimization is achieved.
摘要翻译：为了优化包括光学空间开关和波长选择器的光学开关装置所需的光栅开关的数量，作为将光信号引入光空间开关的初步处理的以下处理被执行。详细地说，通过光学处理光信号，初步过程是光学地转换光信号相对于光空间开关的输入端口的数量。结果，响应于输入端口的处理后的光信号的数量和处理后的光信号的经处理的波长数彼此相等，从而实现优化。

9. 发明授权

US5887039A Data transmission system using specific pattern for synchronization 失效
标题翻译：数据传输系统采用特定的模式进行同步
公开(公告)号：US5887039A
公开(公告)日：1999-03-23
申请号：US356555
申请日：1994-12-15
申请人： Yoshihiko Suemura , Naoya Henmi , Akio Tajima
发明人： Yoshihiko Suemura , Naoya Henmi , Akio Tajima
IPC分类号： H04J3/00 , H04J3/06 , H04L7/00 , H04L7/04 , H04L25/14
CPC分类号： H04L25/14 , H04J3/0602
摘要： Parallel digital data are transmitted along with a specific synchronization pattern added thereto. Each synchronization pattern adder adds the synchronization pattern at an equal timing for each channel. Parallel data after the synchronization pattern addition, are converted in parallel-to-serial converters into serial data which are in turn converted in an optical transmitter into optical signal. On the receiving side, the optical signal is converted in an optical receiver into an electric signal, from which the parallel data are restored in serial-to-parallel converters to be inputted to synchronization pattern detectors. The synchronization pattern detectors compare their shift register data and synchronization pattern and hold their synchronization pattern detection signal to be "1" for one time slot if the number of non-accord bits is within one. In the next time slot, a controller recognizes synchronization pattern detection when and only when all the synchronization pattern detection signals are "1". In this way, reliable synchronization pattern detection can be made regardless of the occurrence of any transmission error in the synchronization pattern.
摘要翻译：平行数字数据与添加到其中的特定同步模式一起发送。每个同步模式加法器在每个通道的相同定时添加同步模式。在同步模式添加之后的并行数据被并行转换为串行数据转换为串行数据，这些数据依次在光发射机中转换为光信号。在接收侧，光信号在光接收机中被转换成电信号，并行数据在并行转换器中被还原，以被输入到同步模式检测器。同步模式检测器比较它们的移位寄存器数据和同步模式，并且如果非协调位的数目在一个之内，则将它们的同步模式检测信号保持为一个时隙的“1”。在下一个时隙中，当且当所有同步模式检测信号为“1”时，控制器识别同步模式检测。以这种方式，可以进行可靠的同步模式检测，而不管同步模式中是否发生任何传输错误。

10. 发明授权

US5687181A Parallel data transmission unit using byte error correcting code 失效
标题翻译：并行数据传输单元采用字节纠错码
公开(公告)号：US5687181A
公开(公告)日：1997-11-11
申请号：US412720
申请日：1995-03-29
申请人： Yoshihiko Suemura , Naoya Henmi
发明人： Yoshihiko Suemura , Naoya Henmi
IPC分类号： H03M7/14 , H03M9/00 , H03M13/27 , H04L1/00 , H04L25/14 , H04L29/00 , H03M13/22
CPC分类号： H04L1/0057 , H03M13/27 , H04L1/0043 , H04L1/0052 , H04L1/0071 , H04L25/14
摘要： A parallel signal of a k bit width is converted such that every m bits of width is made a byte. It is then coded by a plurality i of encoders into a t byte error correcting code in which a byte length is of m bits and a code length is of 1 bytes. The coded parallel signal is interleaved by an interleaver and is distributed into a plurality 1 of transmitters. Each transmitter converts the parallel signal of an mi bit width into a serial signal and transmits the converted signal. Each receiver converts the received serial signal into a parallel signal of an mi bit width and outputs the signal thus converted. The signals outputted from a plurality i of receivers are deinterleaved by a de-interleaver, and the deinterleaved signals are inputted to a plurality i of decoders. The decoders carry out correction of a t byte error in which one byte is of m bits, and integrates the signals outputted therefrom and outputs a parallel signal of a k bit width. By making use of the byte error correcting code, the interleaver, and the deinterleaver, the parallel data transmission unit provides for the correction of a byte error having a byte length longer than that of the code, and also provides for the reduction in scale of the encoders and decoders. Each of i, k, l, and m is an integer not less than 2.
摘要翻译：转换k比特宽度的并行信号，使得每m个宽度的比特成为一个字节。然后将其由编码器的多个i编码为字节长度为m位且码长为1字节的t字节纠错码。编码并行信号由交织器进行交织，并被分配到多个发送器中。每个发射机将mi比特宽度的并行信号转换为串行信号，并发送转换的信号。每个接收机将接收到的串行信号转换成mi比特宽度的并行信号，并输出这样转换的信号。由多个i个接收机输出的信号由解交织器进行解交织，并且解交织的信号被输入到多个解码器。解码器执行一个字节为m位的t字节错误的校正，并且对从其输出的信号进行积分并输出k位宽的并行信号。通过使用字节纠错码，交织器和解交织器，并行数据发送单元提供字节长度比代码长度更长的字节错误的校正，并且还提供了缩小编码器和解码器。 i，k，l和m中的每一个是不小于2的整数。

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