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1. 发明授权

US08476708B2 Semiconductor memory device having a circuit formed on a single crystal semiconductor layer with varied germanium concentration 有权
标题翻译：具有形成在具有不同锗浓度的单晶半导体层上的电路的半导体存储器件
公开(公告)号：US08476708B2
公开(公告)日：2013-07-02
申请号：US13346888
申请日：2012-01-10
申请人： Yoshiaki Fukuzumi , Hideaki Aochi , Masaru Kito , Kiyotaka Miyano , Shinji Mori , Ichiro Mizushima
发明人： Yoshiaki Fukuzumi , Hideaki Aochi , Masaru Kito , Kiyotaka Miyano , Shinji Mori , Ichiro Mizushima
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/792
CPC分类号： H01L27/11582 , H01L27/0688 , H01L27/11573 , H01L27/11578 , H01L27/1207
摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes memory cells. The semiconductor layer is formed on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the memory cell array portion.The circuit portion is formed on the semiconductor layer. The Ge concentration in the lower portion of the semiconductor layer is higher than that in the upper portion of the semiconductor layer.
摘要翻译：根据一个实施例，半导体存储器件包括半导体衬底，存储单元阵列部分，单晶半导体层和电路部分。存储单元阵列部分形成在半导体衬底上，并且包括存储单元。半导体层形成在存储单元阵列部分上，并且通过形成在延伸穿过存储单元阵列部分的孔中而连接到半导体衬底。电路部分形成在半导体层上。半导体层的下部的Ge浓度高于半导体层的上部的Ge浓度。

2. 发明申请

US20120181602A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120181602A1
公开(公告)日：2012-07-19
申请号：US13346888
申请日：2012-01-10
申请人： Yoshiaki Fukuzumi , Hideaki Aochi , Masaru Kito , Kiyotaka Miyano , Shinji Mori , Ichiro Mizushima
发明人： Yoshiaki Fukuzumi , Hideaki Aochi , Masaru Kito , Kiyotaka Miyano , Shinji Mori , Ichiro Mizushima
IPC分类号： H01L27/105 , H01L21/8239
CPC分类号： H01L27/11582 , H01L27/0688 , H01L27/11573 , H01L27/11578 , H01L27/1207
摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes memory cells. The semiconductor layer is formed on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the memory cell array portion.The circuit portion is formed on the semiconductor layer. The Ge concentration in the lower portion of the semiconductor layer is higher than that in the upper portion of the semiconductor layer.
摘要翻译：根据一个实施例，半导体存储器件包括半导体衬底，存储单元阵列部分，单晶半导体层和电路部分。存储单元阵列部分形成在半导体衬底上，并且包括存储单元。半导体层形成在存储单元阵列部分上，并且通过形成在延伸穿过存储单元阵列部分的孔中而连接到半导体衬底。电路部分形成在半导体层上。半导体层的下部的Ge浓度高于半导体层的上部的Ge浓度。

3. 发明授权

US08653577B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08653577B2
公开(公告)日：2014-02-18
申请号：US13003644
申请日：2009-07-01
申请人： Yoshiaki Fukuzumi , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Masaru Kito , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh
发明人： Yoshiaki Fukuzumi , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Masaru Kito , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/7926 , G11C16/0466 , H01L27/11565 , H01L27/11578 , H01L27/11582
摘要： A nonvolatile semiconductor memory device includes: a stacked body in which insulating films and electrode films are alternately stacked; selection gate electrodes provided on the stacked body; bit lines provided on the selection gate electrodes; semiconductor pillars; connective members separated from one another; and a charge storage layer provided between the electrode film and the semiconductor pillar. One of the connective members is connected between a lower part of one of the semiconductor pillars and a lower part of another of the semiconductor pillars. The one of the semiconductor pillars passes through one of the selection gate electrodes and is connected to one of the bit lines, and the another of the semiconductor pillars passes through another of the selection gate electrodes and is connected to another of the bit lines.
摘要翻译：非易失性半导体存储器件包括：绝缘膜和电极膜交替层叠的层叠体; 设置在层叠体上的选择栅电极; 设置在选择栅电极上的位线; 半导体柱连接成员彼此分离; 以及设置在电极膜和半导体柱之间的电荷存储层。一个连接构件连接在一个半导体柱的下部和另一个半导体柱的下部之间。半导体柱中的一个穿过选择栅极之一并连接到一个位线，并且另一个半导体柱通过另一个选择栅电极并连接到另一个位线。

4. 发明授权

US08598643B2 Nonvolatile semiconductor memory device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08598643B2
公开(公告)日：2013-12-03
申请号：US13235425
申请日：2011-09-18
申请人： Kaori Kawasaki , Yoshiaki Fukuzumi , Masaru Kito , Tomoko Fujiwara , Takeshi Imamura , Ryouhei Kirisawa , Hideaki Aochi
发明人： Kaori Kawasaki , Yoshiaki Fukuzumi , Masaru Kito , Tomoko Fujiwara , Takeshi Imamura , Ryouhei Kirisawa , Hideaki Aochi
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/7926
摘要： According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括第一导电层，第二导电层，第一电极间绝缘膜和堆叠在第一导电层上方的第三导电层，存储膜，半导体层，绝缘构件和硅化物层。存储膜和半导体层形成在设置在第二导电层，第一电极间绝缘膜和第三导电层中的通孔的内表面上。绝缘构件埋设在分割第二导电层，第一电极间绝缘膜和第三导电层的狭缝中。硅化物层形成在狭缝中的第二导电层和第三导电层的表面上。沿着狭缝的内表面，第二导电层和第三导电层之间的距离比层叠方向长。

5. 发明授权

US08350326B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08350326B2
公开(公告)日：2013-01-08
申请号：US12839895
申请日：2010-07-20
申请人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Hideaki Aochi
发明人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Hideaki Aochi
IPC分类号： H01L29/792
CPC分类号： H01L29/7926 , H01L21/28282 , H01L27/11578 , H01L27/11582 , H01L29/42344 , H01L29/66833
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked structural bodies, first and second semiconductor pillars, a memory unit connection portion, a selection unit stacked structural body, first and second selection unit semiconductor pillars, a selection unit connection portion, and first to fifth interconnections. The semiconductor pillars pierce the stacked structural bodies. The first and second interconnections are connected to the first and second semiconductor pillars, respectively. The memory unit connection portion connects the first and second semiconductor pillars. The selection unit semiconductor pillars pierce the selection unit stacked structural body. The third and fourth interconnections are connected to the first and second selection unit semiconductor pillars, respectively. The selection unit connection portion connects the first and second selection unit semiconductor pillars. The fifth interconnection is connected to the third interconnection on a side opposite to the selection unit stacked structural body.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括第一和第二堆叠结构体，第一和第二半导体柱，存储单元连接部分，选择单元堆叠结构体，第一和第二选择单元半导体柱，选择单元连接部分，以及第一至第五互连。半导体支柱刺穿堆叠的结构体。第一和第二互连分别连接到第一和第二半导体柱。存储单元连接部连接第一和第二半导体柱。选择单元半导体柱刺穿选择单元堆叠结构体。第三和第四互连分别连接到第一和第二选择单元半导体柱。选择单元连接部分连接第一和第二选择单元半导体柱。第五互连在与选择单元堆叠结构体相反的一侧连接到第三互连。

6. 发明授权

US08338882B2 Semiconductor memory device and method for manufacturing same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08338882B2
公开(公告)日：2012-12-25
申请号：US12841662
申请日：2010-07-22
申请人： Hiroyasu Tanaka , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Hideaki Aochi
发明人： Hiroyasu Tanaka , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Hideaki Aochi
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, an interconnection, and a contact plug. The base includes a substrate and a peripheral circuit formed on a surface of the substrate. The stacked body includes a plurality of conductive layers and a plurality of insulating layers alternately stacked above the base. The memory film is provided on an inner wall of a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers. The memory film includes a charge storage film. The interconnection is provided below the stacked body. The interconnection electrically connects the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region and the peripheral circuit. The contact plug pierces the stacked body in the interconnection region to reach the lowermost layer of the conductive layers in the interconnection region.
摘要翻译：根据一个实施例，半导体存储器件包括基底，堆叠体，存储膜，通道体，互连和接触插塞。基底包括形成在基片的表面上的基片和外围电路。堆叠体包括多个导电层和交替堆叠在基底之上的多个绝缘层。记忆膜设置在通过层叠体冲压的存储孔的内壁上，以到达导电层的最下层。记忆膜包括电荷存储膜。互连设置在堆叠体的下方。互连电连接布置在存储单元阵列区域的外部的互连区域中的导电层的最下层和外围电路。接触插塞刺穿互连区域中的层叠体到达互连区域中的导电层的最下层。

7. 发明授权

US08218358B2 Nonvolatile semiconductor memory device and method for driving same 有权
标题翻译：非易失性半导体存储器件及其驱动方法
公开(公告)号：US08218358B2
公开(公告)日：2012-07-10
申请号：US12851054
申请日：2010-08-05
申请人： Ryota Katsumata , Hideaki Aochi , Hiroyasu Tanaka , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Ryota Katsumata , Hideaki Aochi , Hiroyasu Tanaka , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： G11C11/14
CPC分类号： H01L27/11578 , G11C16/0466 , G11C16/06 , H01L27/11565 , H01L27/11582
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括衬底，堆叠体，半导体柱，电荷存储膜和驱动电路。层叠体设置在基板上。层叠体包括交替层叠有多个电极膜的多个绝缘膜。在堆叠体中形成通孔，以在堆叠方向上对齐。半导体柱被埋在通孔的内部。电荷存储膜设置在电极膜和半导体柱之间。驱动电路为电极膜提供电位。通孔的直径与层叠方向的位置不同。当穿透电极膜的通孔的直径减小时，驱动电路提供降低与半导体柱的电位差的电位。

8. 发明授权

US08193571B2 Stacked type nonvolatile semiconductor memory device and method of manufacturing same 有权
标题翻译：堆叠型非易失性半导体存储器件及其制造方法
公开(公告)号：US08193571B2
公开(公告)日：2012-06-05
申请号：US12542276
申请日：2009-08-17
申请人： Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Megumi Ishiduki , Yosuke Komori , Hideaki Aochi , Yasuyuki Matsuoka
发明人： Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Megumi Ishiduki , Yosuke Komori , Hideaki Aochi , Yasuyuki Matsuoka
IPC分类号： H01L29/10 , H01L21/336
CPC分类号： H01L27/11578 , H01L27/11565 , H01L27/11575 , H01L27/11582 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A stacked body is formed on a silicon substrate by stacking a plurality of insulating films and a plurality of electrode films alternately and through-holes are formed to extend in the stacking direction. Next, gaps are formed between the electrode films using etching the insulating films via the through-holes. Charge storage layers are formed along side faces of the through-holes and inner faces of the gaps, and silicon pillars are filled into the through-holes. Thereby, a nonvolatile semiconductor memory device is manufactured.
摘要翻译：通过交替堆叠多个绝缘膜和多个电极膜，在硅基板上形成层叠体，并且形成贯通孔，以在层叠方向上延伸。接下来，通过通孔蚀刻绝缘膜，在电极膜之间形成间隙。电荷存储层沿着通孔的侧面和间隙的内表面形成，硅柱填充到通孔中。由此，制造非易失性半导体存储器件。

9. 发明授权

US08178919B2 Nonvolatile semiconductor memory device and method for manufacturing same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08178919B2
公开(公告)日：2012-05-15
申请号：US12727830
申请日：2010-03-19
申请人： Tomoko Fujiwara , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Tomoko Fujiwara , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： H01L21/00
CPC分类号： H01L27/11551 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L27/11556
摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including electrode films alternately stacked with inter-electrode insulating films; first and second semiconductor pillars piercing the stacked structural unit; a connection portion semiconductor layer electrically connect the first and second semiconductor pillars; a connection portion conductive layer provided to oppose the connection portion semiconductor layer; a memory layer and an inner insulating film provided between the first and semiconductor pillars and each of the electrode films, and between the connection portion conductive layer and the connection portion semiconductor layer; an outer insulating film provided between the memory layer and each of the electrode films; and a connection portion outer insulating film provided between the memory layer and the connection portion conductive layer. The connection portion outer insulating film has a film thickness thicker than a film thickness of the outer insulating film.
摘要翻译：一种非易失性半导体存储器件，包括：堆叠结构单元，其包括交替层叠有电极间绝缘膜的电极膜; 第一和第二半导体柱刺穿堆叠结构单元; 连接部分半导体层电连接第一和第二半导体柱; 连接部分导电层，设置成与连接部分半导体层相对; 设置在所述第一半导体柱和所述半导体柱之间以及所述电极膜之间并且位于所述连接部分导电层和所述连接部半导体层之间的存储层和内部绝缘膜; 设置在所述存储层和每个所述电极膜之间的外部绝缘膜; 以及设置在存储层和连接部分导电层之间的连接部分外绝缘膜。连接部外绝缘膜的膜厚比外绝缘膜的膜厚厚。

10. 发明授权

US08178917B2 Non-volatile semiconductor storage device having memory cells disposed three-dimensionally, and method of manufacturing the same 有权
标题翻译：具有三维配置存储单元的非易失性半导体存储装置及其制造方法
公开(公告)号：US08178917B2
公开(公告)日：2012-05-15
申请号：US12408249
申请日：2009-03-20
申请人： Hiroyasu Tanaka , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Hideaki Aochi , Megumi Ishiduki , Yasuyuki Matsuoka
发明人： Hiroyasu Tanaka , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Hideaki Aochi , Megumi Ishiduki , Yasuyuki Matsuoka
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L27/105 , H01L27/115 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes a first layer and a second layer. The first layer includes: a plurality of first conductive layers extending in parallel to a substrate and laminated in a direction perpendicular to the substrate; a first insulation layer formed on an upper layer of the plurality of first conductive layers; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and a charge accumulation layer formed between the first conductive layers and the first semiconductor layer. Respective ends of the first conductive layers are formed in a stepwise manner in relation to each other in a first direction. The second layer includes: a plurality of second conductive layers extending in parallel to the substrate and laminated in a direction perpendicular to the substrate, the second conductive layers being formed in the same layer as the plurality of first conductive layers; and a second insulation layer formed on an upper layer of the plurality of second conductive layers. Respective ends of the second conductive layers are formed to align along a straight line extending in a direction substantially perpendicular to the substrate at a predetermined area.
摘要翻译：非易失性半导体存储装置包括第一层和第二层。第一层包括：多个第一导电层，其平行于衬底延伸并且在垂直于衬底的方向上层压; 形成在所述多个第一导电层的上层上的第一绝缘层; 形成为穿透所述多个第一导电层的第一半导体层; 以及形成在第一导电层和第一半导体层之间的电荷累积层。第一导电层的相应端部在第一方向上相对于彼此以逐步的方式形成。第二层包括：多个第二导电层，其平行于衬底延伸并且在垂直于衬底的方向上层叠，第二导电层形成在与多个第一导电层相同的层中; 以及形成在所述多个第二导电层的上层上的第二绝缘层。形成第二导电层的相应端，沿着在预定区域上基本上垂直于衬底的方向延伸的直线对齐。

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